1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 /* External CAN clock - to be overridden by boards that provide it */ 29 can_clk: can { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 a53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0>; 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 45 next-level-cache = <&L2_CA53>; 46 enable-method = "psci"; 47 }; 48 49 a53_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <1>; 53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 55 next-level-cache = <&L2_CA53>; 56 enable-method = "psci"; 57 }; 58 59 a53_2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <2>; 63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 a53_3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <3>; 73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 }; 78 79 L2_CA53: cache-controller { 80 compatible = "cache"; 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 82 cache-unified; 83 cache-level = <2>; 84 }; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 /* External PCIe clock - can be overridden by the board */ 102 pcie_bus_clk: pcie_bus { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 pmu_a53 { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0", "arm,psci-0.2"; 119 method = "smc"; 120 }; 121 122 /* External SCIF clock - to be overridden by boards that provide it */ 123 scif_clk: scif { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 interrupt-parent = <&gic>; 132 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 rwdt: watchdog@e6020000 { 138 compatible = "renesas,r8a77980-wdt", 139 "renesas,rcar-gen3-wdt"; 140 reg = <0 0xe6020000 0 0x0c>; 141 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&cpg CPG_MOD 402>; 143 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 144 resets = <&cpg 402>; 145 status = "disabled"; 146 }; 147 148 gpio0: gpio@e6050000 { 149 compatible = "renesas,gpio-r8a77980", 150 "renesas,rcar-gen3-gpio"; 151 reg = <0 0xe6050000 0 0x50>; 152 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 153 #gpio-cells = <2>; 154 gpio-controller; 155 gpio-ranges = <&pfc 0 0 22>; 156 #interrupt-cells = <2>; 157 interrupt-controller; 158 clocks = <&cpg CPG_MOD 912>; 159 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 160 resets = <&cpg 912>; 161 }; 162 163 gpio1: gpio@e6051000 { 164 compatible = "renesas,gpio-r8a77980", 165 "renesas,rcar-gen3-gpio"; 166 reg = <0 0xe6051000 0 0x50>; 167 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 32 28>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 911>; 174 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 175 resets = <&cpg 911>; 176 }; 177 178 gpio2: gpio@e6052000 { 179 compatible = "renesas,gpio-r8a77980", 180 "renesas,rcar-gen3-gpio"; 181 reg = <0 0xe6052000 0 0x50>; 182 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 183 #gpio-cells = <2>; 184 gpio-controller; 185 gpio-ranges = <&pfc 0 64 30>; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 clocks = <&cpg CPG_MOD 910>; 189 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 190 resets = <&cpg 910>; 191 }; 192 193 gpio3: gpio@e6053000 { 194 compatible = "renesas,gpio-r8a77980", 195 "renesas,rcar-gen3-gpio"; 196 reg = <0 0xe6053000 0 0x50>; 197 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 96 17>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&cpg CPG_MOD 909>; 204 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 205 resets = <&cpg 909>; 206 }; 207 208 gpio4: gpio@e6054000 { 209 compatible = "renesas,gpio-r8a77980", 210 "renesas,rcar-gen3-gpio"; 211 reg = <0 0xe6054000 0 0x50>; 212 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 213 #gpio-cells = <2>; 214 gpio-controller; 215 gpio-ranges = <&pfc 0 128 25>; 216 #interrupt-cells = <2>; 217 interrupt-controller; 218 clocks = <&cpg CPG_MOD 908>; 219 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 220 resets = <&cpg 908>; 221 }; 222 223 gpio5: gpio@e6055000 { 224 compatible = "renesas,gpio-r8a77980", 225 "renesas,rcar-gen3-gpio"; 226 reg = <0 0xe6055000 0 0x50>; 227 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 228 #gpio-cells = <2>; 229 gpio-controller; 230 gpio-ranges = <&pfc 0 160 15>; 231 #interrupt-cells = <2>; 232 interrupt-controller; 233 clocks = <&cpg CPG_MOD 907>; 234 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 235 resets = <&cpg 907>; 236 }; 237 238 pfc: pinctrl@e6060000 { 239 compatible = "renesas,pfc-r8a77980"; 240 reg = <0 0xe6060000 0 0x50c>; 241 }; 242 243 cmt0: timer@e60f0000 { 244 compatible = "renesas,r8a77980-cmt0", 245 "renesas,rcar-gen3-cmt0"; 246 reg = <0 0xe60f0000 0 0x1004>; 247 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cpg CPG_MOD 303>; 250 clock-names = "fck"; 251 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 252 resets = <&cpg 303>; 253 status = "disabled"; 254 }; 255 256 cmt1: timer@e6130000 { 257 compatible = "renesas,r8a77980-cmt1", 258 "renesas,rcar-gen3-cmt1"; 259 reg = <0 0xe6130000 0 0x1004>; 260 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cpg CPG_MOD 302>; 269 clock-names = "fck"; 270 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 271 resets = <&cpg 302>; 272 status = "disabled"; 273 }; 274 275 cmt2: timer@e6140000 { 276 compatible = "renesas,r8a77980-cmt1", 277 "renesas,rcar-gen3-cmt1"; 278 reg = <0 0xe6140000 0 0x1004>; 279 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&cpg CPG_MOD 301>; 288 clock-names = "fck"; 289 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 290 resets = <&cpg 301>; 291 status = "disabled"; 292 }; 293 294 cmt3: timer@e6148000 { 295 compatible = "renesas,r8a77980-cmt1", 296 "renesas,rcar-gen3-cmt1"; 297 reg = <0 0xe6148000 0 0x1004>; 298 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&cpg CPG_MOD 300>; 307 clock-names = "fck"; 308 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 309 resets = <&cpg 300>; 310 status = "disabled"; 311 }; 312 313 cpg: clock-controller@e6150000 { 314 compatible = "renesas,r8a77980-cpg-mssr"; 315 reg = <0 0xe6150000 0 0x1000>; 316 clocks = <&extal_clk>, <&extalr_clk>; 317 clock-names = "extal", "extalr"; 318 #clock-cells = <2>; 319 #power-domain-cells = <0>; 320 #reset-cells = <1>; 321 }; 322 323 rst: reset-controller@e6160000 { 324 compatible = "renesas,r8a77980-rst"; 325 reg = <0 0xe6160000 0 0x200>; 326 }; 327 328 sysc: system-controller@e6180000 { 329 compatible = "renesas,r8a77980-sysc"; 330 reg = <0 0xe6180000 0 0x440>; 331 #power-domain-cells = <1>; 332 }; 333 334 tsc: thermal@e6198000 { 335 compatible = "renesas,r8a77980-thermal"; 336 reg = <0 0xe6198000 0 0x100>, 337 <0 0xe61a0000 0 0x100>; 338 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&cpg CPG_MOD 522>; 342 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 343 resets = <&cpg 522>; 344 #thermal-sensor-cells = <1>; 345 }; 346 347 intc_ex: interrupt-controller@e61c0000 { 348 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 349 #interrupt-cells = <2>; 350 interrupt-controller; 351 reg = <0 0xe61c0000 0 0x200>; 352 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cpg CPG_MOD 407>; 359 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 360 resets = <&cpg 407>; 361 }; 362 363 tmu0: timer@e61e0000 { 364 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 365 reg = <0 0xe61e0000 0 0x30>; 366 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&cpg CPG_MOD 125>; 370 clock-names = "fck"; 371 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 372 resets = <&cpg 125>; 373 status = "disabled"; 374 }; 375 376 tmu1: timer@e6fc0000 { 377 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 378 reg = <0 0xe6fc0000 0 0x30>; 379 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cpg CPG_MOD 124>; 383 clock-names = "fck"; 384 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 385 resets = <&cpg 124>; 386 status = "disabled"; 387 }; 388 389 tmu2: timer@e6fd0000 { 390 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 391 reg = <0 0xe6fd0000 0 0x30>; 392 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cpg CPG_MOD 123>; 396 clock-names = "fck"; 397 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 398 resets = <&cpg 123>; 399 status = "disabled"; 400 }; 401 402 tmu3: timer@e6fe0000 { 403 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 404 reg = <0 0xe6fe0000 0 0x30>; 405 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&cpg CPG_MOD 122>; 409 clock-names = "fck"; 410 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 411 resets = <&cpg 122>; 412 status = "disabled"; 413 }; 414 415 tmu4: timer@ffc00000 { 416 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 417 reg = <0 0xffc00000 0 0x30>; 418 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 121>; 422 clock-names = "fck"; 423 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 424 resets = <&cpg 121>; 425 status = "disabled"; 426 }; 427 428 i2c0: i2c@e6500000 { 429 compatible = "renesas,i2c-r8a77980", 430 "renesas,rcar-gen3-i2c"; 431 reg = <0 0xe6500000 0 0x40>; 432 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cpg CPG_MOD 931>; 434 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 435 resets = <&cpg 931>; 436 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 437 <&dmac2 0x91>, <&dmac2 0x90>; 438 dma-names = "tx", "rx", "tx", "rx"; 439 i2c-scl-internal-delay-ns = <6>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 i2c1: i2c@e6508000 { 446 compatible = "renesas,i2c-r8a77980", 447 "renesas,rcar-gen3-i2c"; 448 reg = <0 0xe6508000 0 0x40>; 449 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&cpg CPG_MOD 930>; 451 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 452 resets = <&cpg 930>; 453 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 454 <&dmac2 0x93>, <&dmac2 0x92>; 455 dma-names = "tx", "rx", "tx", "rx"; 456 i2c-scl-internal-delay-ns = <6>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 status = "disabled"; 460 }; 461 462 i2c2: i2c@e6510000 { 463 compatible = "renesas,i2c-r8a77980", 464 "renesas,rcar-gen3-i2c"; 465 reg = <0 0xe6510000 0 0x40>; 466 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&cpg CPG_MOD 929>; 468 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 469 resets = <&cpg 929>; 470 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 471 <&dmac2 0x95>, <&dmac2 0x94>; 472 dma-names = "tx", "rx", "tx", "rx"; 473 i2c-scl-internal-delay-ns = <6>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 }; 478 479 i2c3: i2c@e66d0000 { 480 compatible = "renesas,i2c-r8a77980", 481 "renesas,rcar-gen3-i2c"; 482 reg = <0 0xe66d0000 0 0x40>; 483 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&cpg CPG_MOD 928>; 485 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 486 resets = <&cpg 928>; 487 i2c-scl-internal-delay-ns = <6>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 status = "disabled"; 491 }; 492 493 i2c4: i2c@e66d8000 { 494 compatible = "renesas,i2c-r8a77980", 495 "renesas,rcar-gen3-i2c"; 496 reg = <0 0xe66d8000 0 0x40>; 497 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cpg CPG_MOD 927>; 499 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 500 resets = <&cpg 927>; 501 i2c-scl-internal-delay-ns = <6>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 status = "disabled"; 505 }; 506 507 i2c5: i2c@e66e0000 { 508 compatible = "renesas,i2c-r8a77980", 509 "renesas,rcar-gen3-i2c"; 510 reg = <0 0xe66e0000 0 0x40>; 511 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&cpg CPG_MOD 919>; 513 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 514 resets = <&cpg 919>; 515 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 516 <&dmac2 0x9b>, <&dmac2 0x9a>; 517 dma-names = "tx", "rx", "tx", "rx"; 518 i2c-scl-internal-delay-ns = <6>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 status = "disabled"; 522 }; 523 524 hscif0: serial@e6540000 { 525 compatible = "renesas,hscif-r8a77980", 526 "renesas,rcar-gen3-hscif", 527 "renesas,hscif"; 528 reg = <0 0xe6540000 0 0x60>; 529 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cpg CPG_MOD 520>, 531 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 532 <&scif_clk>; 533 clock-names = "fck", "brg_int", "scif_clk"; 534 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 535 <&dmac2 0x31>, <&dmac2 0x30>; 536 dma-names = "tx", "rx", "tx", "rx"; 537 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 538 resets = <&cpg 520>; 539 status = "disabled"; 540 }; 541 542 hscif1: serial@e6550000 { 543 compatible = "renesas,hscif-r8a77980", 544 "renesas,rcar-gen3-hscif", 545 "renesas,hscif"; 546 reg = <0 0xe6550000 0 0x60>; 547 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 519>, 549 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 550 <&scif_clk>; 551 clock-names = "fck", "brg_int", "scif_clk"; 552 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 553 <&dmac2 0x33>, <&dmac2 0x32>; 554 dma-names = "tx", "rx", "tx", "rx"; 555 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 556 resets = <&cpg 519>; 557 status = "disabled"; 558 }; 559 560 hscif2: serial@e6560000 { 561 compatible = "renesas,hscif-r8a77980", 562 "renesas,rcar-gen3-hscif", 563 "renesas,hscif"; 564 reg = <0 0xe6560000 0 0x60>; 565 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&cpg CPG_MOD 518>, 567 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 568 <&scif_clk>; 569 clock-names = "fck", "brg_int", "scif_clk"; 570 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 571 <&dmac2 0x35>, <&dmac2 0x34>; 572 dma-names = "tx", "rx", "tx", "rx"; 573 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 574 resets = <&cpg 518>; 575 status = "disabled"; 576 }; 577 578 hscif3: serial@e66a0000 { 579 compatible = "renesas,hscif-r8a77980", 580 "renesas,rcar-gen3-hscif", 581 "renesas,hscif"; 582 reg = <0 0xe66a0000 0 0x60>; 583 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&cpg CPG_MOD 517>, 585 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 586 <&scif_clk>; 587 clock-names = "fck", "brg_int", "scif_clk"; 588 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 589 <&dmac2 0x37>, <&dmac2 0x36>; 590 dma-names = "tx", "rx", "tx", "rx"; 591 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 592 resets = <&cpg 517>; 593 status = "disabled"; 594 }; 595 596 pcie_phy: pcie-phy@e65d0000 { 597 compatible = "renesas,r8a77980-pcie-phy"; 598 reg = <0 0xe65d0000 0 0x8000>; 599 #phy-cells = <0>; 600 clocks = <&cpg CPG_MOD 319>; 601 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 602 resets = <&cpg 319>; 603 status = "disabled"; 604 }; 605 606 canfd: can@e66c0000 { 607 compatible = "renesas,r8a77980-canfd", 608 "renesas,rcar-gen3-canfd"; 609 reg = <0 0xe66c0000 0 0x8000>; 610 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cpg CPG_MOD 914>, 613 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 614 <&can_clk>; 615 clock-names = "fck", "canfd", "can_clk"; 616 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 617 assigned-clock-rates = <40000000>; 618 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 619 resets = <&cpg 914>; 620 status = "disabled"; 621 622 channel0 { 623 status = "disabled"; 624 }; 625 626 channel1 { 627 status = "disabled"; 628 }; 629 }; 630 631 avb: ethernet@e6800000 { 632 compatible = "renesas,etheravb-r8a77980", 633 "renesas,etheravb-rcar-gen3"; 634 reg = <0 0xe6800000 0 0x800>; 635 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 660 interrupt-names = "ch0", "ch1", "ch2", "ch3", 661 "ch4", "ch5", "ch6", "ch7", 662 "ch8", "ch9", "ch10", "ch11", 663 "ch12", "ch13", "ch14", "ch15", 664 "ch16", "ch17", "ch18", "ch19", 665 "ch20", "ch21", "ch22", "ch23", 666 "ch24"; 667 clocks = <&cpg CPG_MOD 812>; 668 clock-names = "fck"; 669 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 670 resets = <&cpg 812>; 671 phy-mode = "rgmii"; 672 rx-internal-delay-ps = <0>; 673 tx-internal-delay-ps = <2000>; 674 iommus = <&ipmmu_ds1 33>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 status = "disabled"; 678 }; 679 680 pwm0: pwm@e6e30000 { 681 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 682 reg = <0 0xe6e30000 0 0x10>; 683 #pwm-cells = <2>; 684 clocks = <&cpg CPG_MOD 523>; 685 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 686 resets = <&cpg 523>; 687 status = "disabled"; 688 }; 689 690 pwm1: pwm@e6e31000 { 691 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 692 reg = <0 0xe6e31000 0 0x10>; 693 #pwm-cells = <2>; 694 clocks = <&cpg CPG_MOD 523>; 695 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 696 resets = <&cpg 523>; 697 status = "disabled"; 698 }; 699 700 pwm2: pwm@e6e32000 { 701 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 702 reg = <0 0xe6e32000 0 0x10>; 703 #pwm-cells = <2>; 704 clocks = <&cpg CPG_MOD 523>; 705 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 706 resets = <&cpg 523>; 707 status = "disabled"; 708 }; 709 710 pwm3: pwm@e6e33000 { 711 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 712 reg = <0 0xe6e33000 0 0x10>; 713 #pwm-cells = <2>; 714 clocks = <&cpg CPG_MOD 523>; 715 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 716 resets = <&cpg 523>; 717 status = "disabled"; 718 }; 719 720 pwm4: pwm@e6e34000 { 721 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 722 reg = <0 0xe6e34000 0 0x10>; 723 #pwm-cells = <2>; 724 clocks = <&cpg CPG_MOD 523>; 725 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 726 resets = <&cpg 523>; 727 status = "disabled"; 728 }; 729 730 scif0: serial@e6e60000 { 731 compatible = "renesas,scif-r8a77980", 732 "renesas,rcar-gen3-scif", 733 "renesas,scif"; 734 reg = <0 0xe6e60000 0 0x40>; 735 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cpg CPG_MOD 207>, 737 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 738 <&scif_clk>; 739 clock-names = "fck", "brg_int", "scif_clk"; 740 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 741 <&dmac2 0x51>, <&dmac2 0x50>; 742 dma-names = "tx", "rx", "tx", "rx"; 743 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 744 resets = <&cpg 207>; 745 status = "disabled"; 746 }; 747 748 scif1: serial@e6e68000 { 749 compatible = "renesas,scif-r8a77980", 750 "renesas,rcar-gen3-scif", 751 "renesas,scif"; 752 reg = <0 0xe6e68000 0 0x40>; 753 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cpg CPG_MOD 206>, 755 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 756 <&scif_clk>; 757 clock-names = "fck", "brg_int", "scif_clk"; 758 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 759 <&dmac2 0x53>, <&dmac2 0x52>; 760 dma-names = "tx", "rx", "tx", "rx"; 761 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 762 resets = <&cpg 206>; 763 status = "disabled"; 764 }; 765 766 scif3: serial@e6c50000 { 767 compatible = "renesas,scif-r8a77980", 768 "renesas,rcar-gen3-scif", 769 "renesas,scif"; 770 reg = <0 0xe6c50000 0 0x40>; 771 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&cpg CPG_MOD 204>, 773 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 774 <&scif_clk>; 775 clock-names = "fck", "brg_int", "scif_clk"; 776 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 777 <&dmac2 0x57>, <&dmac2 0x56>; 778 dma-names = "tx", "rx", "tx", "rx"; 779 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 780 resets = <&cpg 204>; 781 status = "disabled"; 782 }; 783 784 scif4: serial@e6c40000 { 785 compatible = "renesas,scif-r8a77980", 786 "renesas,rcar-gen3-scif", 787 "renesas,scif"; 788 reg = <0 0xe6c40000 0 0x40>; 789 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&cpg CPG_MOD 203>, 791 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 792 <&scif_clk>; 793 clock-names = "fck", "brg_int", "scif_clk"; 794 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 795 <&dmac2 0x59>, <&dmac2 0x58>; 796 dma-names = "tx", "rx", "tx", "rx"; 797 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 798 resets = <&cpg 203>; 799 status = "disabled"; 800 }; 801 802 tpu: pwm@e6e80000 { 803 compatible = "renesas,tpu-r8a77980", "renesas,tpu"; 804 reg = <0 0xe6e80000 0 0x148>; 805 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cpg CPG_MOD 304>; 807 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 808 resets = <&cpg 304>; 809 #pwm-cells = <3>; 810 status = "disabled"; 811 }; 812 813 msiof0: spi@e6e90000 { 814 compatible = "renesas,msiof-r8a77980", 815 "renesas,rcar-gen3-msiof"; 816 reg = <0 0xe6e90000 0 0x64>; 817 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&cpg CPG_MOD 211>; 819 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 820 resets = <&cpg 211>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 msiof1: spi@e6ea0000 { 827 compatible = "renesas,msiof-r8a77980", 828 "renesas,rcar-gen3-msiof"; 829 reg = <0 0xe6ea0000 0 0x0064>; 830 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&cpg CPG_MOD 210>; 832 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 833 resets = <&cpg 210>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 status = "disabled"; 837 }; 838 839 msiof2: spi@e6c00000 { 840 compatible = "renesas,msiof-r8a77980", 841 "renesas,rcar-gen3-msiof"; 842 reg = <0 0xe6c00000 0 0x0064>; 843 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&cpg CPG_MOD 209>; 845 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 846 resets = <&cpg 209>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 status = "disabled"; 850 }; 851 852 msiof3: spi@e6c10000 { 853 compatible = "renesas,msiof-r8a77980", 854 "renesas,rcar-gen3-msiof"; 855 reg = <0 0xe6c10000 0 0x0064>; 856 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cpg CPG_MOD 208>; 858 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 859 resets = <&cpg 208>; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 status = "disabled"; 863 }; 864 865 vin0: video@e6ef0000 { 866 compatible = "renesas,vin-r8a77980"; 867 reg = <0 0xe6ef0000 0 0x1000>; 868 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cpg CPG_MOD 811>; 870 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 871 resets = <&cpg 811>; 872 renesas,id = <0>; 873 status = "disabled"; 874 875 ports { 876 #address-cells = <1>; 877 #size-cells = <0>; 878 879 port@1 { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 883 reg = <1>; 884 885 vin0csi40: endpoint@2 { 886 reg = <2>; 887 remote-endpoint = <&csi40vin0>; 888 }; 889 }; 890 }; 891 }; 892 893 vin1: video@e6ef1000 { 894 compatible = "renesas,vin-r8a77980"; 895 reg = <0 0xe6ef1000 0 0x1000>; 896 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&cpg CPG_MOD 810>; 898 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 899 status = "disabled"; 900 renesas,id = <1>; 901 resets = <&cpg 810>; 902 903 ports { 904 #address-cells = <1>; 905 #size-cells = <0>; 906 907 port@1 { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 reg = <1>; 912 913 vin1csi40: endpoint@2 { 914 reg = <2>; 915 remote-endpoint = <&csi40vin1>; 916 }; 917 }; 918 }; 919 }; 920 921 vin2: video@e6ef2000 { 922 compatible = "renesas,vin-r8a77980"; 923 reg = <0 0xe6ef2000 0 0x1000>; 924 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&cpg CPG_MOD 809>; 926 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 927 resets = <&cpg 809>; 928 renesas,id = <2>; 929 status = "disabled"; 930 931 ports { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 port@1 { 936 #address-cells = <1>; 937 #size-cells = <0>; 938 939 reg = <1>; 940 941 vin2csi40: endpoint@2 { 942 reg = <2>; 943 remote-endpoint = <&csi40vin2>; 944 }; 945 }; 946 }; 947 }; 948 949 vin3: video@e6ef3000 { 950 compatible = "renesas,vin-r8a77980"; 951 reg = <0 0xe6ef3000 0 0x1000>; 952 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&cpg CPG_MOD 808>; 954 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 955 resets = <&cpg 808>; 956 renesas,id = <3>; 957 status = "disabled"; 958 959 ports { 960 #address-cells = <1>; 961 #size-cells = <0>; 962 963 port@1 { 964 #address-cells = <1>; 965 #size-cells = <0>; 966 967 reg = <1>; 968 969 vin3csi40: endpoint@2 { 970 reg = <2>; 971 remote-endpoint = <&csi40vin3>; 972 }; 973 }; 974 }; 975 }; 976 977 vin4: video@e6ef4000 { 978 compatible = "renesas,vin-r8a77980"; 979 reg = <0 0xe6ef4000 0 0x1000>; 980 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cpg CPG_MOD 807>; 982 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 983 resets = <&cpg 807>; 984 renesas,id = <4>; 985 status = "disabled"; 986 987 ports { 988 #address-cells = <1>; 989 #size-cells = <0>; 990 991 port@1 { 992 #address-cells = <1>; 993 #size-cells = <0>; 994 995 reg = <1>; 996 997 vin4csi41: endpoint@3 { 998 reg = <3>; 999 remote-endpoint = <&csi41vin4>; 1000 }; 1001 }; 1002 }; 1003 }; 1004 1005 vin5: video@e6ef5000 { 1006 compatible = "renesas,vin-r8a77980"; 1007 reg = <0 0xe6ef5000 0 0x1000>; 1008 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&cpg CPG_MOD 806>; 1010 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1011 resets = <&cpg 806>; 1012 renesas,id = <5>; 1013 status = "disabled"; 1014 1015 ports { 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 1019 port@1 { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 1023 reg = <1>; 1024 1025 vin5csi41: endpoint@3 { 1026 reg = <3>; 1027 remote-endpoint = <&csi41vin5>; 1028 }; 1029 }; 1030 }; 1031 }; 1032 1033 vin6: video@e6ef6000 { 1034 compatible = "renesas,vin-r8a77980"; 1035 reg = <0 0xe6ef6000 0 0x1000>; 1036 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&cpg CPG_MOD 805>; 1038 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1039 resets = <&cpg 805>; 1040 renesas,id = <6>; 1041 status = "disabled"; 1042 1043 ports { 1044 #address-cells = <1>; 1045 #size-cells = <0>; 1046 1047 port@1 { 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 1051 reg = <1>; 1052 1053 vin6csi41: endpoint@3 { 1054 reg = <3>; 1055 remote-endpoint = <&csi41vin6>; 1056 }; 1057 }; 1058 }; 1059 }; 1060 1061 vin7: video@e6ef7000 { 1062 compatible = "renesas,vin-r8a77980"; 1063 reg = <0 0xe6ef7000 0 0x1000>; 1064 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cpg CPG_MOD 804>; 1066 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1067 resets = <&cpg 804>; 1068 renesas,id = <7>; 1069 status = "disabled"; 1070 1071 ports { 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 1075 port@1 { 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 reg = <1>; 1080 1081 vin7csi41: endpoint@3 { 1082 reg = <3>; 1083 remote-endpoint = <&csi41vin7>; 1084 }; 1085 }; 1086 }; 1087 }; 1088 1089 vin8: video@e6ef8000 { 1090 compatible = "renesas,vin-r8a77980"; 1091 reg = <0 0xe6ef8000 0 0x1000>; 1092 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&cpg CPG_MOD 628>; 1094 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1095 resets = <&cpg 628>; 1096 renesas,id = <8>; 1097 status = "disabled"; 1098 }; 1099 1100 vin9: video@e6ef9000 { 1101 compatible = "renesas,vin-r8a77980"; 1102 reg = <0 0xe6ef9000 0 0x1000>; 1103 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&cpg CPG_MOD 627>; 1105 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1106 resets = <&cpg 627>; 1107 renesas,id = <9>; 1108 status = "disabled"; 1109 }; 1110 1111 vin10: video@e6efa000 { 1112 compatible = "renesas,vin-r8a77980"; 1113 reg = <0 0xe6efa000 0 0x1000>; 1114 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&cpg CPG_MOD 625>; 1116 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1117 resets = <&cpg 625>; 1118 renesas,id = <10>; 1119 status = "disabled"; 1120 }; 1121 1122 vin11: video@e6efb000 { 1123 compatible = "renesas,vin-r8a77980"; 1124 reg = <0 0xe6efb000 0 0x1000>; 1125 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&cpg CPG_MOD 618>; 1127 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1128 resets = <&cpg 618>; 1129 renesas,id = <11>; 1130 status = "disabled"; 1131 }; 1132 1133 vin12: video@e6efc000 { 1134 compatible = "renesas,vin-r8a77980"; 1135 reg = <0 0xe6efc000 0 0x1000>; 1136 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&cpg CPG_MOD 612>; 1138 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1139 resets = <&cpg 612>; 1140 renesas,id = <12>; 1141 status = "disabled"; 1142 }; 1143 1144 vin13: video@e6efd000 { 1145 compatible = "renesas,vin-r8a77980"; 1146 reg = <0 0xe6efd000 0 0x1000>; 1147 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&cpg CPG_MOD 608>; 1149 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1150 resets = <&cpg 608>; 1151 renesas,id = <13>; 1152 status = "disabled"; 1153 }; 1154 1155 vin14: video@e6efe000 { 1156 compatible = "renesas,vin-r8a77980"; 1157 reg = <0 0xe6efe000 0 0x1000>; 1158 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&cpg CPG_MOD 605>; 1160 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1161 resets = <&cpg 605>; 1162 renesas,id = <14>; 1163 status = "disabled"; 1164 }; 1165 1166 vin15: video@e6eff000 { 1167 compatible = "renesas,vin-r8a77980"; 1168 reg = <0 0xe6eff000 0 0x1000>; 1169 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&cpg CPG_MOD 604>; 1171 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1172 resets = <&cpg 604>; 1173 renesas,id = <15>; 1174 status = "disabled"; 1175 }; 1176 1177 dmac1: dma-controller@e7300000 { 1178 compatible = "renesas,dmac-r8a77980", 1179 "renesas,rcar-dmac"; 1180 reg = <0 0xe7300000 0 0x10000>; 1181 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupt-names = "error", 1199 "ch0", "ch1", "ch2", "ch3", 1200 "ch4", "ch5", "ch6", "ch7", 1201 "ch8", "ch9", "ch10", "ch11", 1202 "ch12", "ch13", "ch14", "ch15"; 1203 clocks = <&cpg CPG_MOD 218>; 1204 clock-names = "fck"; 1205 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1206 resets = <&cpg 218>; 1207 #dma-cells = <1>; 1208 dma-channels = <16>; 1209 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1210 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1211 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1212 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1213 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1214 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1215 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1216 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1217 }; 1218 1219 dmac2: dma-controller@e7310000 { 1220 compatible = "renesas,dmac-r8a77980", 1221 "renesas,rcar-dmac"; 1222 reg = <0 0xe7310000 0 0x10000>; 1223 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1240 interrupt-names = "error", 1241 "ch0", "ch1", "ch2", "ch3", 1242 "ch4", "ch5", "ch6", "ch7", 1243 "ch8", "ch9", "ch10", "ch11", 1244 "ch12", "ch13", "ch14", "ch15"; 1245 clocks = <&cpg CPG_MOD 217>; 1246 clock-names = "fck"; 1247 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1248 resets = <&cpg 217>; 1249 #dma-cells = <1>; 1250 dma-channels = <16>; 1251 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1252 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1253 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1254 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1255 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1256 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1257 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1258 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1259 }; 1260 1261 gether: ethernet@e7400000 { 1262 compatible = "renesas,gether-r8a77980"; 1263 reg = <0 0xe7400000 0 0x1000>; 1264 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&cpg CPG_MOD 813>; 1266 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1267 resets = <&cpg 813>; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 status = "disabled"; 1271 }; 1272 1273 ipmmu_ds1: iommu@e7740000 { 1274 compatible = "renesas,ipmmu-r8a77980"; 1275 reg = <0 0xe7740000 0 0x1000>; 1276 renesas,ipmmu-main = <&ipmmu_mm 0>; 1277 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1278 #iommu-cells = <1>; 1279 }; 1280 1281 ipmmu_ir: iommu@ff8b0000 { 1282 compatible = "renesas,ipmmu-r8a77980"; 1283 reg = <0 0xff8b0000 0 0x1000>; 1284 renesas,ipmmu-main = <&ipmmu_mm 3>; 1285 power-domains = <&sysc R8A77980_PD_A3IR>; 1286 #iommu-cells = <1>; 1287 }; 1288 1289 ipmmu_mm: iommu@e67b0000 { 1290 compatible = "renesas,ipmmu-r8a77980"; 1291 reg = <0 0xe67b0000 0 0x1000>; 1292 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1294 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1295 #iommu-cells = <1>; 1296 }; 1297 1298 ipmmu_rt: iommu@ffc80000 { 1299 compatible = "renesas,ipmmu-r8a77980"; 1300 reg = <0 0xffc80000 0 0x1000>; 1301 renesas,ipmmu-main = <&ipmmu_mm 10>; 1302 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1303 #iommu-cells = <1>; 1304 }; 1305 1306 ipmmu_vc0: iommu@fe990000 { 1307 compatible = "renesas,ipmmu-r8a77980"; 1308 reg = <0 0xfe990000 0 0x1000>; 1309 renesas,ipmmu-main = <&ipmmu_mm 12>; 1310 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1311 #iommu-cells = <1>; 1312 }; 1313 1314 ipmmu_vi0: iommu@febd0000 { 1315 compatible = "renesas,ipmmu-r8a77980"; 1316 reg = <0 0xfebd0000 0 0x1000>; 1317 renesas,ipmmu-main = <&ipmmu_mm 14>; 1318 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1319 #iommu-cells = <1>; 1320 }; 1321 1322 ipmmu_vip0: iommu@e7b00000 { 1323 compatible = "renesas,ipmmu-r8a77980"; 1324 reg = <0 0xe7b00000 0 0x1000>; 1325 renesas,ipmmu-main = <&ipmmu_mm 4>; 1326 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1327 #iommu-cells = <1>; 1328 }; 1329 1330 ipmmu_vip1: iommu@e7960000 { 1331 compatible = "renesas,ipmmu-r8a77980"; 1332 reg = <0 0xe7960000 0 0x1000>; 1333 renesas,ipmmu-main = <&ipmmu_mm 11>; 1334 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1335 #iommu-cells = <1>; 1336 }; 1337 1338 mmc0: mmc@ee140000 { 1339 compatible = "renesas,sdhi-r8a77980", 1340 "renesas,rcar-gen3-sdhi"; 1341 reg = <0 0xee140000 0 0x2000>; 1342 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1343 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>; 1344 clock-names = "core", "clkh"; 1345 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1346 resets = <&cpg 314>; 1347 max-frequency = <200000000>; 1348 iommus = <&ipmmu_ds1 32>; 1349 status = "disabled"; 1350 }; 1351 1352 rpc: spi@ee200000 { 1353 compatible = "renesas,r8a77980-rpc-if", 1354 "renesas,rcar-gen3-rpc-if"; 1355 reg = <0 0xee200000 0 0x200>, 1356 <0 0x08000000 0 0x4000000>, 1357 <0 0xee208000 0 0x100>; 1358 reg-names = "regs", "dirmap", "wbuf"; 1359 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&cpg CPG_MOD 917>; 1361 clock-names = "rpc"; 1362 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1363 resets = <&cpg 917>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 gic: interrupt-controller@f1010000 { 1370 compatible = "arm,gic-400"; 1371 #interrupt-cells = <3>; 1372 #address-cells = <0>; 1373 interrupt-controller; 1374 reg = <0x0 0xf1010000 0 0x1000>, 1375 <0x0 0xf1020000 0 0x20000>, 1376 <0x0 0xf1040000 0 0x20000>, 1377 <0x0 0xf1060000 0 0x20000>; 1378 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 1379 IRQ_TYPE_LEVEL_HIGH)>; 1380 clocks = <&cpg CPG_MOD 408>; 1381 clock-names = "clk"; 1382 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1383 resets = <&cpg 408>; 1384 }; 1385 1386 pciec: pcie@fe000000 { 1387 compatible = "renesas,pcie-r8a77980", 1388 "renesas,pcie-rcar-gen3"; 1389 reg = <0 0xfe000000 0 0x80000>; 1390 #address-cells = <3>; 1391 #size-cells = <2>; 1392 bus-range = <0x00 0xff>; 1393 device_type = "pci"; 1394 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>, 1395 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, 1396 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, 1397 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; 1398 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1399 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1402 #interrupt-cells = <1>; 1403 interrupt-map-mask = <0 0 0 0>; 1404 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1405 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1406 clock-names = "pcie", "pcie_bus"; 1407 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1408 resets = <&cpg 319>; 1409 phys = <&pcie_phy>; 1410 phy-names = "pcie"; 1411 status = "disabled"; 1412 }; 1413 1414 vspd0: vsp@fea20000 { 1415 compatible = "renesas,vsp2"; 1416 reg = <0 0xfea20000 0 0x5000>; 1417 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1418 clocks = <&cpg CPG_MOD 623>; 1419 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1420 resets = <&cpg 623>; 1421 renesas,fcp = <&fcpvd0>; 1422 }; 1423 1424 fcpvd0: fcp@fea27000 { 1425 compatible = "renesas,fcpv"; 1426 reg = <0 0xfea27000 0 0x200>; 1427 clocks = <&cpg CPG_MOD 603>; 1428 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1429 resets = <&cpg 603>; 1430 }; 1431 1432 csi40: csi2@feaa0000 { 1433 compatible = "renesas,r8a77980-csi2"; 1434 reg = <0 0xfeaa0000 0 0x10000>; 1435 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&cpg CPG_MOD 716>; 1437 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1438 resets = <&cpg 716>; 1439 status = "disabled"; 1440 1441 ports { 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 1445 port@0 { 1446 reg = <0>; 1447 }; 1448 1449 port@1 { 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 1453 reg = <1>; 1454 1455 csi40vin0: endpoint@0 { 1456 reg = <0>; 1457 remote-endpoint = <&vin0csi40>; 1458 }; 1459 csi40vin1: endpoint@1 { 1460 reg = <1>; 1461 remote-endpoint = <&vin1csi40>; 1462 }; 1463 csi40vin2: endpoint@2 { 1464 reg = <2>; 1465 remote-endpoint = <&vin2csi40>; 1466 }; 1467 csi40vin3: endpoint@3 { 1468 reg = <3>; 1469 remote-endpoint = <&vin3csi40>; 1470 }; 1471 }; 1472 }; 1473 }; 1474 1475 csi41: csi2@feab0000 { 1476 compatible = "renesas,r8a77980-csi2"; 1477 reg = <0 0xfeab0000 0 0x10000>; 1478 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1479 clocks = <&cpg CPG_MOD 715>; 1480 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1481 resets = <&cpg 715>; 1482 status = "disabled"; 1483 1484 ports { 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 1488 port@0 { 1489 reg = <0>; 1490 }; 1491 1492 port@1 { 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 1496 reg = <1>; 1497 1498 csi41vin4: endpoint@0 { 1499 reg = <0>; 1500 remote-endpoint = <&vin4csi41>; 1501 }; 1502 csi41vin5: endpoint@1 { 1503 reg = <1>; 1504 remote-endpoint = <&vin5csi41>; 1505 }; 1506 csi41vin6: endpoint@2 { 1507 reg = <2>; 1508 remote-endpoint = <&vin6csi41>; 1509 }; 1510 csi41vin7: endpoint@3 { 1511 reg = <3>; 1512 remote-endpoint = <&vin7csi41>; 1513 }; 1514 }; 1515 }; 1516 }; 1517 1518 du: display@feb00000 { 1519 compatible = "renesas,du-r8a77980"; 1520 reg = <0 0xfeb00000 0 0x80000>; 1521 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1522 clocks = <&cpg CPG_MOD 724>; 1523 clock-names = "du.0"; 1524 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1525 resets = <&cpg 724>; 1526 reset-names = "du.0"; 1527 renesas,vsps = <&vspd0 0>; 1528 1529 status = "disabled"; 1530 1531 ports { 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 1535 port@0 { 1536 reg = <0>; 1537 du_out_rgb: endpoint { 1538 }; 1539 }; 1540 1541 port@1 { 1542 reg = <1>; 1543 du_out_lvds0: endpoint { 1544 remote-endpoint = <&lvds0_in>; 1545 }; 1546 }; 1547 }; 1548 }; 1549 1550 lvds0: lvds-encoder@feb90000 { 1551 compatible = "renesas,r8a77980-lvds"; 1552 reg = <0 0xfeb90000 0 0x14>; 1553 clocks = <&cpg CPG_MOD 727>; 1554 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1555 resets = <&cpg 727>; 1556 status = "disabled"; 1557 1558 ports { 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 port@0 { 1563 reg = <0>; 1564 lvds0_in: endpoint { 1565 remote-endpoint = 1566 <&du_out_lvds0>; 1567 }; 1568 }; 1569 1570 port@1 { 1571 reg = <1>; 1572 lvds0_out: endpoint { 1573 }; 1574 }; 1575 }; 1576 }; 1577 1578 prr: chipid@fff00044 { 1579 compatible = "renesas,prr"; 1580 reg = <0 0xfff00044 0 4>; 1581 }; 1582 }; 1583 1584 thermal-zones { 1585 sensor1_thermal: sensor1-thermal { 1586 polling-delay-passive = <250>; 1587 polling-delay = <1000>; 1588 thermal-sensors = <&tsc 0>; 1589 1590 trips { 1591 sensor1-passive { 1592 temperature = <95000>; 1593 hysteresis = <1000>; 1594 type = "passive"; 1595 }; 1596 sensor1-critical { 1597 temperature = <120000>; 1598 hysteresis = <1000>; 1599 type = "critical"; 1600 }; 1601 }; 1602 }; 1603 1604 sensor2_thermal: sensor2-thermal { 1605 polling-delay-passive = <250>; 1606 polling-delay = <1000>; 1607 thermal-sensors = <&tsc 1>; 1608 1609 trips { 1610 sensor2-passive { 1611 temperature = <95000>; 1612 hysteresis = <1000>; 1613 type = "passive"; 1614 }; 1615 sensor2-critical { 1616 temperature = <120000>; 1617 hysteresis = <1000>; 1618 type = "critical"; 1619 }; 1620 }; 1621 }; 1622 }; 1623 1624 timer { 1625 compatible = "arm,armv8-timer"; 1626 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 1627 IRQ_TYPE_LEVEL_LOW)>, 1628 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 1629 IRQ_TYPE_LEVEL_LOW)>, 1630 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 1631 IRQ_TYPE_LEVEL_LOW)>, 1632 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 1633 IRQ_TYPE_LEVEL_LOW)>; 1634 }; 1635}; 1636