1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 /* External CAN clock - to be overridden by boards that provide it */ 29 can_clk: can { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 a53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0>; 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 45 next-level-cache = <&L2_CA53>; 46 enable-method = "psci"; 47 }; 48 49 a53_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <1>; 53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 55 next-level-cache = <&L2_CA53>; 56 enable-method = "psci"; 57 }; 58 59 a53_2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <2>; 63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 a53_3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <3>; 73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 }; 78 79 L2_CA53: cache-controller { 80 compatible = "cache"; 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 82 cache-unified; 83 cache-level = <2>; 84 }; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 /* External PCIe clock - can be overridden by the board */ 102 pcie_bus_clk: pcie_bus { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 pmu_a53 { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0", "arm,psci-0.2"; 119 method = "smc"; 120 }; 121 122 /* External SCIF clock - to be overridden by boards that provide it */ 123 scif_clk: scif { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 interrupt-parent = <&gic>; 132 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 rwdt: watchdog@e6020000 { 138 compatible = "renesas,r8a77980-wdt", 139 "renesas,rcar-gen3-wdt"; 140 reg = <0 0xe6020000 0 0x0c>; 141 clocks = <&cpg CPG_MOD 402>; 142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 143 resets = <&cpg 402>; 144 status = "disabled"; 145 }; 146 147 gpio0: gpio@e6050000 { 148 compatible = "renesas,gpio-r8a77980", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6050000 0 0x50>; 151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 0 22>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 912>; 158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 159 resets = <&cpg 912>; 160 }; 161 162 gpio1: gpio@e6051000 { 163 compatible = "renesas,gpio-r8a77980", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6051000 0 0x50>; 166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 32 28>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 911>; 173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 174 resets = <&cpg 911>; 175 }; 176 177 gpio2: gpio@e6052000 { 178 compatible = "renesas,gpio-r8a77980", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6052000 0 0x50>; 181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 64 30>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 910>; 188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 189 resets = <&cpg 910>; 190 }; 191 192 gpio3: gpio@e6053000 { 193 compatible = "renesas,gpio-r8a77980", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6053000 0 0x50>; 196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 96 17>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 909>; 203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 204 resets = <&cpg 909>; 205 }; 206 207 gpio4: gpio@e6054000 { 208 compatible = "renesas,gpio-r8a77980", 209 "renesas,rcar-gen3-gpio"; 210 reg = <0 0xe6054000 0 0x50>; 211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 212 #gpio-cells = <2>; 213 gpio-controller; 214 gpio-ranges = <&pfc 0 128 25>; 215 #interrupt-cells = <2>; 216 interrupt-controller; 217 clocks = <&cpg CPG_MOD 908>; 218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 219 resets = <&cpg 908>; 220 }; 221 222 gpio5: gpio@e6055000 { 223 compatible = "renesas,gpio-r8a77980", 224 "renesas,rcar-gen3-gpio"; 225 reg = <0 0xe6055000 0 0x50>; 226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 227 #gpio-cells = <2>; 228 gpio-controller; 229 gpio-ranges = <&pfc 0 160 15>; 230 #interrupt-cells = <2>; 231 interrupt-controller; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 }; 236 237 pfc: pin-controller@e6060000 { 238 compatible = "renesas,pfc-r8a77980"; 239 reg = <0 0xe6060000 0 0x50c>; 240 }; 241 242 cmt0: timer@e60f0000 { 243 compatible = "renesas,r8a77980-cmt0", 244 "renesas,rcar-gen3-cmt0"; 245 reg = <0 0xe60f0000 0 0x1004>; 246 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cpg CPG_MOD 303>; 249 clock-names = "fck"; 250 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 251 resets = <&cpg 303>; 252 status = "disabled"; 253 }; 254 255 cmt1: timer@e6130000 { 256 compatible = "renesas,r8a77980-cmt1", 257 "renesas,rcar-gen3-cmt1"; 258 reg = <0 0xe6130000 0 0x1004>; 259 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 302>; 268 clock-names = "fck"; 269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 270 resets = <&cpg 302>; 271 status = "disabled"; 272 }; 273 274 cmt2: timer@e6140000 { 275 compatible = "renesas,r8a77980-cmt1", 276 "renesas,rcar-gen3-cmt1"; 277 reg = <0 0xe6140000 0 0x1004>; 278 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 301>; 287 clock-names = "fck"; 288 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 289 resets = <&cpg 301>; 290 status = "disabled"; 291 }; 292 293 cmt3: timer@e6148000 { 294 compatible = "renesas,r8a77980-cmt1", 295 "renesas,rcar-gen3-cmt1"; 296 reg = <0 0xe6148000 0 0x1004>; 297 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cpg CPG_MOD 300>; 306 clock-names = "fck"; 307 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 308 resets = <&cpg 300>; 309 status = "disabled"; 310 }; 311 312 cpg: clock-controller@e6150000 { 313 compatible = "renesas,r8a77980-cpg-mssr"; 314 reg = <0 0xe6150000 0 0x1000>; 315 clocks = <&extal_clk>, <&extalr_clk>; 316 clock-names = "extal", "extalr"; 317 #clock-cells = <2>; 318 #power-domain-cells = <0>; 319 #reset-cells = <1>; 320 }; 321 322 rst: reset-controller@e6160000 { 323 compatible = "renesas,r8a77980-rst"; 324 reg = <0 0xe6160000 0 0x200>; 325 }; 326 327 sysc: system-controller@e6180000 { 328 compatible = "renesas,r8a77980-sysc"; 329 reg = <0 0xe6180000 0 0x440>; 330 #power-domain-cells = <1>; 331 }; 332 333 tsc: thermal@e6198000 { 334 compatible = "renesas,r8a77980-thermal"; 335 reg = <0 0xe6198000 0 0x100>, 336 <0 0xe61a0000 0 0x100>; 337 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 522>; 341 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 342 resets = <&cpg 522>; 343 #thermal-sensor-cells = <1>; 344 }; 345 346 intc_ex: interrupt-controller@e61c0000 { 347 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 348 #interrupt-cells = <2>; 349 interrupt-controller; 350 reg = <0 0xe61c0000 0 0x200>; 351 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 352 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 353 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 354 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 355 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 356 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&cpg CPG_MOD 407>; 358 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 359 resets = <&cpg 407>; 360 }; 361 362 i2c0: i2c@e6500000 { 363 compatible = "renesas,i2c-r8a77980", 364 "renesas,rcar-gen3-i2c"; 365 reg = <0 0xe6500000 0 0x40>; 366 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cpg CPG_MOD 931>; 368 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 369 resets = <&cpg 931>; 370 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 371 <&dmac2 0x91>, <&dmac2 0x90>; 372 dma-names = "tx", "rx", "tx", "rx"; 373 i2c-scl-internal-delay-ns = <6>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 status = "disabled"; 377 }; 378 379 i2c1: i2c@e6508000 { 380 compatible = "renesas,i2c-r8a77980", 381 "renesas,rcar-gen3-i2c"; 382 reg = <0 0xe6508000 0 0x40>; 383 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&cpg CPG_MOD 930>; 385 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 386 resets = <&cpg 930>; 387 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 388 <&dmac2 0x93>, <&dmac2 0x92>; 389 dma-names = "tx", "rx", "tx", "rx"; 390 i2c-scl-internal-delay-ns = <6>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 status = "disabled"; 394 }; 395 396 i2c2: i2c@e6510000 { 397 compatible = "renesas,i2c-r8a77980", 398 "renesas,rcar-gen3-i2c"; 399 reg = <0 0xe6510000 0 0x40>; 400 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cpg CPG_MOD 929>; 402 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 403 resets = <&cpg 929>; 404 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 405 <&dmac2 0x95>, <&dmac2 0x94>; 406 dma-names = "tx", "rx", "tx", "rx"; 407 i2c-scl-internal-delay-ns = <6>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 i2c3: i2c@e66d0000 { 414 compatible = "renesas,i2c-r8a77980", 415 "renesas,rcar-gen3-i2c"; 416 reg = <0 0xe66d0000 0 0x40>; 417 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cpg CPG_MOD 928>; 419 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 420 resets = <&cpg 928>; 421 i2c-scl-internal-delay-ns = <6>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 status = "disabled"; 425 }; 426 427 i2c4: i2c@e66d8000 { 428 compatible = "renesas,i2c-r8a77980", 429 "renesas,rcar-gen3-i2c"; 430 reg = <0 0xe66d8000 0 0x40>; 431 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cpg CPG_MOD 927>; 433 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 434 resets = <&cpg 927>; 435 i2c-scl-internal-delay-ns = <6>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 i2c5: i2c@e66e0000 { 442 compatible = "renesas,i2c-r8a77980", 443 "renesas,rcar-gen3-i2c"; 444 reg = <0 0xe66e0000 0 0x40>; 445 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&cpg CPG_MOD 919>; 447 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 448 resets = <&cpg 919>; 449 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 450 <&dmac2 0x9b>, <&dmac2 0x9a>; 451 dma-names = "tx", "rx", "tx", "rx"; 452 i2c-scl-internal-delay-ns = <6>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 status = "disabled"; 456 }; 457 458 hscif0: serial@e6540000 { 459 compatible = "renesas,hscif-r8a77980", 460 "renesas,rcar-gen3-hscif", 461 "renesas,hscif"; 462 reg = <0 0xe6540000 0 0x60>; 463 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cpg CPG_MOD 520>, 465 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 466 <&scif_clk>; 467 clock-names = "fck", "brg_int", "scif_clk"; 468 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 469 <&dmac2 0x31>, <&dmac2 0x30>; 470 dma-names = "tx", "rx", "tx", "rx"; 471 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 472 resets = <&cpg 520>; 473 status = "disabled"; 474 }; 475 476 hscif1: serial@e6550000 { 477 compatible = "renesas,hscif-r8a77980", 478 "renesas,rcar-gen3-hscif", 479 "renesas,hscif"; 480 reg = <0 0xe6550000 0 0x60>; 481 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cpg CPG_MOD 519>, 483 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 484 <&scif_clk>; 485 clock-names = "fck", "brg_int", "scif_clk"; 486 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 487 <&dmac2 0x33>, <&dmac2 0x32>; 488 dma-names = "tx", "rx", "tx", "rx"; 489 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 490 resets = <&cpg 519>; 491 status = "disabled"; 492 }; 493 494 hscif2: serial@e6560000 { 495 compatible = "renesas,hscif-r8a77980", 496 "renesas,rcar-gen3-hscif", 497 "renesas,hscif"; 498 reg = <0 0xe6560000 0 0x60>; 499 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cpg CPG_MOD 518>, 501 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 502 <&scif_clk>; 503 clock-names = "fck", "brg_int", "scif_clk"; 504 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 505 <&dmac2 0x35>, <&dmac2 0x34>; 506 dma-names = "tx", "rx", "tx", "rx"; 507 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 508 resets = <&cpg 518>; 509 status = "disabled"; 510 }; 511 512 hscif3: serial@e66a0000 { 513 compatible = "renesas,hscif-r8a77980", 514 "renesas,rcar-gen3-hscif", 515 "renesas,hscif"; 516 reg = <0 0xe66a0000 0 0x60>; 517 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cpg CPG_MOD 517>, 519 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 520 <&scif_clk>; 521 clock-names = "fck", "brg_int", "scif_clk"; 522 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 523 <&dmac2 0x37>, <&dmac2 0x36>; 524 dma-names = "tx", "rx", "tx", "rx"; 525 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 526 resets = <&cpg 517>; 527 status = "disabled"; 528 }; 529 530 pcie_phy: pcie-phy@e65d0000 { 531 compatible = "renesas,r8a77980-pcie-phy"; 532 reg = <0 0xe65d0000 0 0x8000>; 533 #phy-cells = <0>; 534 clocks = <&cpg CPG_MOD 319>; 535 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 536 resets = <&cpg 319>; 537 status = "disabled"; 538 }; 539 540 canfd: can@e66c0000 { 541 compatible = "renesas,r8a77980-canfd", 542 "renesas,rcar-gen3-canfd"; 543 reg = <0 0xe66c0000 0 0x8000>; 544 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&cpg CPG_MOD 914>, 547 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 548 <&can_clk>; 549 clock-names = "fck", "canfd", "can_clk"; 550 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 551 assigned-clock-rates = <40000000>; 552 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 553 resets = <&cpg 914>; 554 status = "disabled"; 555 556 channel0 { 557 status = "disabled"; 558 }; 559 560 channel1 { 561 status = "disabled"; 562 }; 563 }; 564 565 avb: ethernet@e6800000 { 566 compatible = "renesas,etheravb-r8a77980", 567 "renesas,etheravb-rcar-gen3"; 568 reg = <0 0xe6800000 0 0x800>; 569 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-names = "ch0", "ch1", "ch2", "ch3", 595 "ch4", "ch5", "ch6", "ch7", 596 "ch8", "ch9", "ch10", "ch11", 597 "ch12", "ch13", "ch14", "ch15", 598 "ch16", "ch17", "ch18", "ch19", 599 "ch20", "ch21", "ch22", "ch23", 600 "ch24"; 601 clocks = <&cpg CPG_MOD 812>; 602 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 603 resets = <&cpg 812>; 604 phy-mode = "rgmii"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 pwm0: pwm@e6e30000 { 611 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 612 reg = <0 0xe6e30000 0 0x10>; 613 #pwm-cells = <2>; 614 clocks = <&cpg CPG_MOD 523>; 615 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 616 resets = <&cpg 523>; 617 status = "disabled"; 618 }; 619 620 pwm1: pwm@e6e31000 { 621 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 622 reg = <0 0xe6e31000 0 0x10>; 623 #pwm-cells = <2>; 624 clocks = <&cpg CPG_MOD 523>; 625 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 626 resets = <&cpg 523>; 627 status = "disabled"; 628 }; 629 630 pwm2: pwm@e6e32000 { 631 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 632 reg = <0 0xe6e32000 0 0x10>; 633 #pwm-cells = <2>; 634 clocks = <&cpg CPG_MOD 523>; 635 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 636 resets = <&cpg 523>; 637 status = "disabled"; 638 }; 639 640 pwm3: pwm@e6e33000 { 641 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 642 reg = <0 0xe6e33000 0 0x10>; 643 #pwm-cells = <2>; 644 clocks = <&cpg CPG_MOD 523>; 645 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 646 resets = <&cpg 523>; 647 status = "disabled"; 648 }; 649 650 pwm4: pwm@e6e34000 { 651 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 652 reg = <0 0xe6e34000 0 0x10>; 653 #pwm-cells = <2>; 654 clocks = <&cpg CPG_MOD 523>; 655 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 656 resets = <&cpg 523>; 657 status = "disabled"; 658 }; 659 660 scif0: serial@e6e60000 { 661 compatible = "renesas,scif-r8a77980", 662 "renesas,rcar-gen3-scif", 663 "renesas,scif"; 664 reg = <0 0xe6e60000 0 0x40>; 665 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD 207>, 667 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 668 <&scif_clk>; 669 clock-names = "fck", "brg_int", "scif_clk"; 670 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 671 <&dmac2 0x51>, <&dmac2 0x50>; 672 dma-names = "tx", "rx", "tx", "rx"; 673 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 674 resets = <&cpg 207>; 675 status = "disabled"; 676 }; 677 678 scif1: serial@e6e68000 { 679 compatible = "renesas,scif-r8a77980", 680 "renesas,rcar-gen3-scif", 681 "renesas,scif"; 682 reg = <0 0xe6e68000 0 0x40>; 683 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 206>, 685 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 686 <&scif_clk>; 687 clock-names = "fck", "brg_int", "scif_clk"; 688 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 689 <&dmac2 0x53>, <&dmac2 0x52>; 690 dma-names = "tx", "rx", "tx", "rx"; 691 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 692 resets = <&cpg 206>; 693 status = "disabled"; 694 }; 695 696 scif3: serial@e6c50000 { 697 compatible = "renesas,scif-r8a77980", 698 "renesas,rcar-gen3-scif", 699 "renesas,scif"; 700 reg = <0 0xe6c50000 0 0x40>; 701 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cpg CPG_MOD 204>, 703 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 704 <&scif_clk>; 705 clock-names = "fck", "brg_int", "scif_clk"; 706 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 707 <&dmac2 0x57>, <&dmac2 0x56>; 708 dma-names = "tx", "rx", "tx", "rx"; 709 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 710 resets = <&cpg 204>; 711 status = "disabled"; 712 }; 713 714 scif4: serial@e6c40000 { 715 compatible = "renesas,scif-r8a77980", 716 "renesas,rcar-gen3-scif", 717 "renesas,scif"; 718 reg = <0 0xe6c40000 0 0x40>; 719 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&cpg CPG_MOD 203>, 721 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 722 <&scif_clk>; 723 clock-names = "fck", "brg_int", "scif_clk"; 724 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 725 <&dmac2 0x59>, <&dmac2 0x58>; 726 dma-names = "tx", "rx", "tx", "rx"; 727 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 728 resets = <&cpg 203>; 729 status = "disabled"; 730 }; 731 732 tpu: pwm@e6e80000 { 733 compatible = "renesas,tpu-r8a77980", "renesas,tpu"; 734 reg = <0 0xe6e80000 0 0x148>; 735 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cpg CPG_MOD 304>; 737 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 738 resets = <&cpg 304>; 739 #pwm-cells = <3>; 740 status = "disabled"; 741 }; 742 743 vin0: video@e6ef0000 { 744 compatible = "renesas,vin-r8a77980"; 745 reg = <0 0xe6ef0000 0 0x1000>; 746 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cpg CPG_MOD 811>; 748 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 749 resets = <&cpg 811>; 750 status = "disabled"; 751 752 ports { 753 #address-cells = <1>; 754 #size-cells = <0>; 755 756 port@1 { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 760 reg = <1>; 761 762 vin0csi40: endpoint@2 { 763 reg = <2>; 764 remote-endpoint = <&csi40vin0>; 765 }; 766 }; 767 }; 768 }; 769 770 vin1: video@e6ef1000 { 771 compatible = "renesas,vin-r8a77980"; 772 reg = <0 0xe6ef1000 0 0x1000>; 773 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&cpg CPG_MOD 810>; 775 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 776 status = "disabled"; 777 resets = <&cpg 810>; 778 779 ports { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 783 port@1 { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 787 reg = <1>; 788 789 vin1csi40: endpoint@2 { 790 reg = <2>; 791 remote-endpoint = <&csi40vin1>; 792 }; 793 }; 794 }; 795 }; 796 797 vin2: video@e6ef2000 { 798 compatible = "renesas,vin-r8a77980"; 799 reg = <0 0xe6ef2000 0 0x1000>; 800 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&cpg CPG_MOD 809>; 802 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 803 resets = <&cpg 809>; 804 status = "disabled"; 805 806 ports { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 810 port@1 { 811 #address-cells = <1>; 812 #size-cells = <0>; 813 814 reg = <1>; 815 816 vin2csi40: endpoint@2 { 817 reg = <2>; 818 remote-endpoint = <&csi40vin2>; 819 }; 820 }; 821 }; 822 }; 823 824 vin3: video@e6ef3000 { 825 compatible = "renesas,vin-r8a77980"; 826 reg = <0 0xe6ef3000 0 0x1000>; 827 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&cpg CPG_MOD 808>; 829 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 830 resets = <&cpg 808>; 831 status = "disabled"; 832 833 ports { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 port@1 { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 841 reg = <1>; 842 843 vin3csi40: endpoint@2 { 844 reg = <2>; 845 remote-endpoint = <&csi40vin3>; 846 }; 847 }; 848 }; 849 }; 850 851 vin4: video@e6ef4000 { 852 compatible = "renesas,vin-r8a77980"; 853 reg = <0 0xe6ef4000 0 0x1000>; 854 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 807>; 856 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 857 resets = <&cpg 807>; 858 status = "disabled"; 859 860 ports { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 864 port@1 { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 868 reg = <1>; 869 870 vin4csi41: endpoint@2 { 871 reg = <2>; 872 remote-endpoint = <&csi41vin4>; 873 }; 874 }; 875 }; 876 }; 877 878 vin5: video@e6ef5000 { 879 compatible = "renesas,vin-r8a77980"; 880 reg = <0 0xe6ef5000 0 0x1000>; 881 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&cpg CPG_MOD 806>; 883 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 884 resets = <&cpg 806>; 885 status = "disabled"; 886 887 ports { 888 #address-cells = <1>; 889 #size-cells = <0>; 890 891 port@1 { 892 #address-cells = <1>; 893 #size-cells = <0>; 894 895 reg = <1>; 896 897 vin5csi41: endpoint@2 { 898 reg = <2>; 899 remote-endpoint = <&csi41vin5>; 900 }; 901 }; 902 }; 903 }; 904 905 vin6: video@e6ef6000 { 906 compatible = "renesas,vin-r8a77980"; 907 reg = <0 0xe6ef6000 0 0x1000>; 908 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&cpg CPG_MOD 805>; 910 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 911 resets = <&cpg 805>; 912 status = "disabled"; 913 914 ports { 915 #address-cells = <1>; 916 #size-cells = <0>; 917 918 port@1 { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 reg = <1>; 923 924 vin6csi41: endpoint@2 { 925 reg = <2>; 926 remote-endpoint = <&csi41vin6>; 927 }; 928 }; 929 }; 930 }; 931 932 vin7: video@e6ef7000 { 933 compatible = "renesas,vin-r8a77980"; 934 reg = <0 0xe6ef7000 0 0x1000>; 935 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&cpg CPG_MOD 804>; 937 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 938 resets = <&cpg 804>; 939 status = "disabled"; 940 941 ports { 942 #address-cells = <1>; 943 #size-cells = <0>; 944 945 port@1 { 946 #address-cells = <1>; 947 #size-cells = <0>; 948 949 reg = <1>; 950 951 vin7csi41: endpoint@2 { 952 reg = <2>; 953 remote-endpoint = <&csi41vin7>; 954 }; 955 }; 956 }; 957 }; 958 959 vin8: video@e6ef8000 { 960 compatible = "renesas,vin-r8a77980"; 961 reg = <0 0xe6ef8000 0 0x1000>; 962 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&cpg CPG_MOD 628>; 964 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 965 resets = <&cpg 628>; 966 status = "disabled"; 967 }; 968 969 vin9: video@e6ef9000 { 970 compatible = "renesas,vin-r8a77980"; 971 reg = <0 0xe6ef9000 0 0x1000>; 972 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cpg CPG_MOD 627>; 974 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 975 resets = <&cpg 627>; 976 status = "disabled"; 977 }; 978 979 vin10: video@e6efa000 { 980 compatible = "renesas,vin-r8a77980"; 981 reg = <0 0xe6efa000 0 0x1000>; 982 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cpg CPG_MOD 625>; 984 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 985 resets = <&cpg 625>; 986 status = "disabled"; 987 }; 988 989 vin11: video@e6efb000 { 990 compatible = "renesas,vin-r8a77980"; 991 reg = <0 0xe6efb000 0 0x1000>; 992 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&cpg CPG_MOD 618>; 994 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 995 resets = <&cpg 618>; 996 status = "disabled"; 997 }; 998 999 vin12: video@e6efc000 { 1000 compatible = "renesas,vin-r8a77980"; 1001 reg = <0 0xe6efc000 0 0x1000>; 1002 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&cpg CPG_MOD 612>; 1004 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1005 resets = <&cpg 612>; 1006 status = "disabled"; 1007 }; 1008 1009 vin13: video@e6efd000 { 1010 compatible = "renesas,vin-r8a77980"; 1011 reg = <0 0xe6efd000 0 0x1000>; 1012 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&cpg CPG_MOD 608>; 1014 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1015 resets = <&cpg 608>; 1016 status = "disabled"; 1017 }; 1018 1019 vin14: video@e6efe000 { 1020 compatible = "renesas,vin-r8a77980"; 1021 reg = <0 0xe6efe000 0 0x1000>; 1022 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cpg CPG_MOD 605>; 1024 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1025 resets = <&cpg 605>; 1026 status = "disabled"; 1027 }; 1028 1029 vin15: video@e6eff000 { 1030 compatible = "renesas,vin-r8a77980"; 1031 reg = <0 0xe6eff000 0 0x1000>; 1032 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&cpg CPG_MOD 604>; 1034 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1035 resets = <&cpg 604>; 1036 status = "disabled"; 1037 }; 1038 1039 dmac1: dma-controller@e7300000 { 1040 compatible = "renesas,dmac-r8a77980", 1041 "renesas,rcar-dmac"; 1042 reg = <0 0xe7300000 0 0x10000>; 1043 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 1044 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 1045 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 1046 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 1047 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 1048 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 1049 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 1050 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 1051 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 1052 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 1053 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 1054 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 1055 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 1056 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 1057 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 1058 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 1059 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1060 interrupt-names = "error", 1061 "ch0", "ch1", "ch2", "ch3", 1062 "ch4", "ch5", "ch6", "ch7", 1063 "ch8", "ch9", "ch10", "ch11", 1064 "ch12", "ch13", "ch14", "ch15"; 1065 clocks = <&cpg CPG_MOD 218>; 1066 clock-names = "fck"; 1067 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1068 resets = <&cpg 218>; 1069 #dma-cells = <1>; 1070 dma-channels = <16>; 1071 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1072 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1073 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1074 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1075 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1076 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1077 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1078 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1079 }; 1080 1081 dmac2: dma-controller@e7310000 { 1082 compatible = "renesas,dmac-r8a77980", 1083 "renesas,rcar-dmac"; 1084 reg = <0 0xe7310000 0 0x10000>; 1085 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 1086 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 1087 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 1088 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 1089 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 1090 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 1091 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 1092 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 1093 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 1094 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 1095 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 1096 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 1097 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 1098 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 1099 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 1100 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 1101 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1102 interrupt-names = "error", 1103 "ch0", "ch1", "ch2", "ch3", 1104 "ch4", "ch5", "ch6", "ch7", 1105 "ch8", "ch9", "ch10", "ch11", 1106 "ch12", "ch13", "ch14", "ch15"; 1107 clocks = <&cpg CPG_MOD 217>; 1108 clock-names = "fck"; 1109 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1110 resets = <&cpg 217>; 1111 #dma-cells = <1>; 1112 dma-channels = <16>; 1113 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1114 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1115 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1116 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1117 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1118 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1119 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1120 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1121 }; 1122 1123 gether: ethernet@e7400000 { 1124 compatible = "renesas,gether-r8a77980"; 1125 reg = <0 0xe7400000 0 0x1000>; 1126 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cpg CPG_MOD 813>; 1128 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1129 resets = <&cpg 813>; 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 status = "disabled"; 1133 }; 1134 1135 ipmmu_ds1: mmu@e7740000 { 1136 compatible = "renesas,ipmmu-r8a77980"; 1137 reg = <0 0xe7740000 0 0x1000>; 1138 renesas,ipmmu-main = <&ipmmu_mm 0>; 1139 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1140 #iommu-cells = <1>; 1141 }; 1142 1143 ipmmu_ir: mmu@ff8b0000 { 1144 compatible = "renesas,ipmmu-r8a77980"; 1145 reg = <0 0xff8b0000 0 0x1000>; 1146 renesas,ipmmu-main = <&ipmmu_mm 3>; 1147 power-domains = <&sysc R8A77980_PD_A3IR>; 1148 #iommu-cells = <1>; 1149 }; 1150 1151 ipmmu_mm: mmu@e67b0000 { 1152 compatible = "renesas,ipmmu-r8a77980"; 1153 reg = <0 0xe67b0000 0 0x1000>; 1154 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1156 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1157 #iommu-cells = <1>; 1158 }; 1159 1160 ipmmu_rt: mmu@ffc80000 { 1161 compatible = "renesas,ipmmu-r8a77980"; 1162 reg = <0 0xffc80000 0 0x1000>; 1163 renesas,ipmmu-main = <&ipmmu_mm 10>; 1164 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1165 #iommu-cells = <1>; 1166 }; 1167 1168 ipmmu_vc0: mmu@fe6b0000 { 1169 compatible = "renesas,ipmmu-r8a77980"; 1170 reg = <0 0xfe6b0000 0 0x1000>; 1171 renesas,ipmmu-main = <&ipmmu_mm 12>; 1172 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1173 #iommu-cells = <1>; 1174 }; 1175 1176 ipmmu_vi0: mmu@febd0000 { 1177 compatible = "renesas,ipmmu-r8a77980"; 1178 reg = <0 0xfebd0000 0 0x1000>; 1179 renesas,ipmmu-main = <&ipmmu_mm 14>; 1180 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1181 #iommu-cells = <1>; 1182 }; 1183 1184 ipmmu_vip0: mmu@e7b00000 { 1185 compatible = "renesas,ipmmu-r8a77980"; 1186 reg = <0 0xe7b00000 0 0x1000>; 1187 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1188 #iommu-cells = <1>; 1189 }; 1190 1191 ipmmu_vip1: mmu@e7960000 { 1192 compatible = "renesas,ipmmu-r8a77980"; 1193 reg = <0 0xe7960000 0 0x1000>; 1194 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1195 #iommu-cells = <1>; 1196 }; 1197 1198 mmc0: mmc@ee140000 { 1199 compatible = "renesas,sdhi-r8a77980", 1200 "renesas,rcar-gen3-sdhi"; 1201 reg = <0 0xee140000 0 0x2000>; 1202 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&cpg CPG_MOD 314>; 1204 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1205 resets = <&cpg 314>; 1206 max-frequency = <200000000>; 1207 status = "disabled"; 1208 }; 1209 1210 gic: interrupt-controller@f1010000 { 1211 compatible = "arm,gic-400"; 1212 #interrupt-cells = <3>; 1213 #address-cells = <0>; 1214 interrupt-controller; 1215 reg = <0x0 0xf1010000 0 0x1000>, 1216 <0x0 0xf1020000 0 0x20000>, 1217 <0x0 0xf1040000 0 0x20000>, 1218 <0x0 0xf1060000 0 0x20000>; 1219 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 1220 IRQ_TYPE_LEVEL_HIGH)>; 1221 clocks = <&cpg CPG_MOD 408>; 1222 clock-names = "clk"; 1223 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1224 resets = <&cpg 408>; 1225 }; 1226 1227 pciec: pcie@fe000000 { 1228 compatible = "renesas,pcie-r8a77980", 1229 "renesas,pcie-rcar-gen3"; 1230 reg = <0 0xfe000000 0 0x80000>; 1231 #address-cells = <3>; 1232 #size-cells = <2>; 1233 bus-range = <0x00 0xff>; 1234 device_type = "pci"; 1235 ranges = < 1236 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000 1237 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000 1238 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000 1239 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000 1240 >; 1241 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1242 0 0x80000000>; 1243 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1246 #interrupt-cells = <1>; 1247 interrupt-map-mask = <0 0 0 0>; 1248 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 1249 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1251 clock-names = "pcie", "pcie_bus"; 1252 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1253 resets = <&cpg 319>; 1254 phys = <&pcie_phy>; 1255 phy-names = "pcie"; 1256 status = "disabled"; 1257 }; 1258 1259 vspd0: vsp@fea20000 { 1260 compatible = "renesas,vsp2"; 1261 reg = <0 0xfea20000 0 0x5000>; 1262 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&cpg CPG_MOD 623>; 1264 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1265 resets = <&cpg 623>; 1266 renesas,fcp = <&fcpvd0>; 1267 }; 1268 1269 fcpvd0: fcp@fea27000 { 1270 compatible = "renesas,fcpv"; 1271 reg = <0 0xfea27000 0 0x200>; 1272 clocks = <&cpg CPG_MOD 603>; 1273 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1274 resets = <&cpg 603>; 1275 }; 1276 1277 csi40: csi2@feaa0000 { 1278 compatible = "renesas,r8a77980-csi2"; 1279 reg = <0 0xfeaa0000 0 0x10000>; 1280 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&cpg CPG_MOD 716>; 1282 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1283 resets = <&cpg 716>; 1284 status = "disabled"; 1285 1286 ports { 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 1290 port@1 { 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 1294 reg = <1>; 1295 1296 csi40vin0: endpoint@0 { 1297 reg = <0>; 1298 remote-endpoint = <&vin0csi40>; 1299 }; 1300 csi40vin1: endpoint@1 { 1301 reg = <1>; 1302 remote-endpoint = <&vin1csi40>; 1303 }; 1304 csi40vin2: endpoint@2 { 1305 reg = <2>; 1306 remote-endpoint = <&vin2csi40>; 1307 }; 1308 csi40vin3: endpoint@3 { 1309 reg = <3>; 1310 remote-endpoint = <&vin3csi40>; 1311 }; 1312 }; 1313 }; 1314 }; 1315 1316 csi41: csi2@feab0000 { 1317 compatible = "renesas,r8a77980-csi2"; 1318 reg = <0 0xfeab0000 0 0x10000>; 1319 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1320 clocks = <&cpg CPG_MOD 715>; 1321 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1322 resets = <&cpg 715>; 1323 status = "disabled"; 1324 1325 ports { 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 1329 port@1 { 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 1333 reg = <1>; 1334 1335 csi41vin4: endpoint@0 { 1336 reg = <0>; 1337 remote-endpoint = <&vin4csi41>; 1338 }; 1339 csi41vin5: endpoint@1 { 1340 reg = <1>; 1341 remote-endpoint = <&vin5csi41>; 1342 }; 1343 csi41vin6: endpoint@2 { 1344 reg = <2>; 1345 remote-endpoint = <&vin6csi41>; 1346 }; 1347 csi41vin7: endpoint@3 { 1348 reg = <3>; 1349 remote-endpoint = <&vin7csi41>; 1350 }; 1351 }; 1352 }; 1353 }; 1354 1355 du: display@feb00000 { 1356 compatible = "renesas,du-r8a77980", 1357 "renesas,du-r8a77970"; 1358 reg = <0 0xfeb00000 0 0x80000>; 1359 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&cpg CPG_MOD 724>; 1361 clock-names = "du.0"; 1362 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1363 resets = <&cpg 724>; 1364 vsps = <&vspd0>; 1365 status = "disabled"; 1366 1367 ports { 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 1371 port@0 { 1372 reg = <0>; 1373 du_out_rgb: endpoint { 1374 }; 1375 }; 1376 1377 port@1 { 1378 reg = <1>; 1379 du_out_lvds0: endpoint { 1380 remote-endpoint = <&lvds0_in>; 1381 }; 1382 }; 1383 }; 1384 }; 1385 1386 lvds0: lvds-encoder@feb90000 { 1387 compatible = "renesas,r8a77980-lvds"; 1388 reg = <0 0xfeb90000 0 0x14>; 1389 clocks = <&cpg CPG_MOD 727>; 1390 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1391 resets = <&cpg 727>; 1392 status = "disabled"; 1393 1394 ports { 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 1398 port@0 { 1399 reg = <0>; 1400 lvds0_in: endpoint { 1401 remote-endpoint = 1402 <&du_out_lvds0>; 1403 }; 1404 }; 1405 1406 port@1 { 1407 reg = <1>; 1408 lvds0_out: endpoint { 1409 }; 1410 }; 1411 }; 1412 }; 1413 1414 prr: chipid@fff00044 { 1415 compatible = "renesas,prr"; 1416 reg = <0 0xfff00044 0 4>; 1417 }; 1418 }; 1419 1420 thermal-zones { 1421 thermal-sensor-1 { 1422 polling-delay-passive = <250>; 1423 polling-delay = <1000>; 1424 thermal-sensors = <&tsc 0>; 1425 1426 trips { 1427 sensor1-passive { 1428 temperature = <95000>; 1429 hysteresis = <1000>; 1430 type = "passive"; 1431 }; 1432 sensor1-critical { 1433 temperature = <120000>; 1434 hysteresis = <1000>; 1435 type = "critical"; 1436 }; 1437 }; 1438 }; 1439 1440 thermal-sensor-2 { 1441 polling-delay-passive = <250>; 1442 polling-delay = <1000>; 1443 thermal-sensors = <&tsc 1>; 1444 1445 trips { 1446 sensor2-passive { 1447 temperature = <95000>; 1448 hysteresis = <1000>; 1449 type = "passive"; 1450 }; 1451 sensor2-critical { 1452 temperature = <120000>; 1453 hysteresis = <1000>; 1454 type = "critical"; 1455 }; 1456 }; 1457 }; 1458 }; 1459 1460 timer { 1461 compatible = "arm,armv8-timer"; 1462 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 1463 IRQ_TYPE_LEVEL_LOW)>, 1464 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 1465 IRQ_TYPE_LEVEL_LOW)>, 1466 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 1467 IRQ_TYPE_LEVEL_LOW)>, 1468 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 1469 IRQ_TYPE_LEVEL_LOW)>; 1470 }; 1471}; 1472