1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 a53_0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 reg = <0>; 36 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 37 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 38 next-level-cache = <&L2_CA53>; 39 enable-method = "psci"; 40 }; 41 42 a53_1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <1>; 46 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 47 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 48 next-level-cache = <&L2_CA53>; 49 enable-method = "psci"; 50 }; 51 52 a53_2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53", "arm,armv8"; 55 reg = <2>; 56 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 57 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 58 next-level-cache = <&L2_CA53>; 59 enable-method = "psci"; 60 }; 61 62 a53_3: cpu@3 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 reg = <3>; 66 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 67 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 68 next-level-cache = <&L2_CA53>; 69 enable-method = "psci"; 70 }; 71 72 L2_CA53: cache-controller { 73 compatible = "cache"; 74 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 75 cache-unified; 76 cache-level = <2>; 77 }; 78 }; 79 80 /* External CAN clock - to be overridden by boards that provide it */ 81 can_clk: can { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 psci { 102 compatible = "arm,psci-1.0", "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 /* External SCIF clock - to be overridden by boards that provide it */ 107 scif_clk: scif { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <0>; 111 }; 112 113 soc { 114 compatible = "simple-bus"; 115 interrupt-parent = <&gic>; 116 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 121 gpio0: gpio@e6050000 { 122 compatible = "renesas,gpio-r8a77980", 123 "renesas,rcar-gen3-gpio"; 124 reg = <0 0xe6050000 0 0x50>; 125 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 126 #gpio-cells = <2>; 127 gpio-controller; 128 gpio-ranges = <&pfc 0 0 22>; 129 #interrupt-cells = <2>; 130 interrupt-controller; 131 clocks = <&cpg CPG_MOD 912>; 132 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 133 resets = <&cpg 912>; 134 }; 135 136 gpio1: gpio@e6051000 { 137 compatible = "renesas,gpio-r8a77980", 138 "renesas,rcar-gen3-gpio"; 139 reg = <0 0xe6051000 0 0x50>; 140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 141 #gpio-cells = <2>; 142 gpio-controller; 143 gpio-ranges = <&pfc 0 32 28>; 144 #interrupt-cells = <2>; 145 interrupt-controller; 146 clocks = <&cpg CPG_MOD 911>; 147 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 148 resets = <&cpg 911>; 149 }; 150 151 gpio2: gpio@e6052000 { 152 compatible = "renesas,gpio-r8a77980", 153 "renesas,rcar-gen3-gpio"; 154 reg = <0 0xe6052000 0 0x50>; 155 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 156 #gpio-cells = <2>; 157 gpio-controller; 158 gpio-ranges = <&pfc 0 64 30>; 159 #interrupt-cells = <2>; 160 interrupt-controller; 161 clocks = <&cpg CPG_MOD 910>; 162 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 163 resets = <&cpg 910>; 164 }; 165 166 gpio3: gpio@e6053000 { 167 compatible = "renesas,gpio-r8a77980", 168 "renesas,rcar-gen3-gpio"; 169 reg = <0 0xe6053000 0 0x50>; 170 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 171 #gpio-cells = <2>; 172 gpio-controller; 173 gpio-ranges = <&pfc 0 96 17>; 174 #interrupt-cells = <2>; 175 interrupt-controller; 176 clocks = <&cpg CPG_MOD 909>; 177 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 178 resets = <&cpg 909>; 179 }; 180 181 gpio4: gpio@e6054000 { 182 compatible = "renesas,gpio-r8a77980", 183 "renesas,rcar-gen3-gpio"; 184 reg = <0 0xe6054000 0 0x50>; 185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 186 #gpio-cells = <2>; 187 gpio-controller; 188 gpio-ranges = <&pfc 0 128 25>; 189 #interrupt-cells = <2>; 190 interrupt-controller; 191 clocks = <&cpg CPG_MOD 908>; 192 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 193 resets = <&cpg 908>; 194 }; 195 196 gpio5: gpio@e6055000 { 197 compatible = "renesas,gpio-r8a77980", 198 "renesas,rcar-gen3-gpio"; 199 reg = <0 0xe6055000 0 0x50>; 200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 201 #gpio-cells = <2>; 202 gpio-controller; 203 gpio-ranges = <&pfc 0 160 15>; 204 #interrupt-cells = <2>; 205 interrupt-controller; 206 clocks = <&cpg CPG_MOD 907>; 207 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 208 resets = <&cpg 907>; 209 }; 210 211 pfc: pin-controller@e6060000 { 212 compatible = "renesas,pfc-r8a77980"; 213 reg = <0 0xe6060000 0 0x50c>; 214 }; 215 216 cpg: clock-controller@e6150000 { 217 compatible = "renesas,r8a77980-cpg-mssr"; 218 reg = <0 0xe6150000 0 0x1000>; 219 clocks = <&extal_clk>, <&extalr_clk>; 220 clock-names = "extal", "extalr"; 221 #clock-cells = <2>; 222 #power-domain-cells = <0>; 223 #reset-cells = <1>; 224 }; 225 226 rst: reset-controller@e6160000 { 227 compatible = "renesas,r8a77980-rst"; 228 reg = <0 0xe6160000 0 0x200>; 229 }; 230 231 sysc: system-controller@e6180000 { 232 compatible = "renesas,r8a77980-sysc"; 233 reg = <0 0xe6180000 0 0x440>; 234 #power-domain-cells = <1>; 235 }; 236 237 i2c0: i2c@e6500000 { 238 compatible = "renesas,i2c-r8a77980", 239 "renesas,rcar-gen3-i2c"; 240 reg = <0 0xe6500000 0 0x40>; 241 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cpg CPG_MOD 931>; 243 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 244 resets = <&cpg 931>; 245 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 246 <&dmac2 0x91>, <&dmac2 0x90>; 247 dma-names = "tx", "rx", "tx", "rx"; 248 i2c-scl-internal-delay-ns = <6>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 i2c1: i2c@e6508000 { 255 compatible = "renesas,i2c-r8a77980", 256 "renesas,rcar-gen3-i2c"; 257 reg = <0 0xe6508000 0 0x40>; 258 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cpg CPG_MOD 930>; 260 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 261 resets = <&cpg 930>; 262 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 263 <&dmac2 0x93>, <&dmac2 0x92>; 264 dma-names = "tx", "rx", "tx", "rx"; 265 i2c-scl-internal-delay-ns = <6>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 i2c2: i2c@e6510000 { 272 compatible = "renesas,i2c-r8a77980", 273 "renesas,rcar-gen3-i2c"; 274 reg = <0 0xe6510000 0 0x40>; 275 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cpg CPG_MOD 929>; 277 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 278 resets = <&cpg 929>; 279 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 280 <&dmac2 0x95>, <&dmac2 0x94>; 281 dma-names = "tx", "rx", "tx", "rx"; 282 i2c-scl-internal-delay-ns = <6>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 status = "disabled"; 286 }; 287 288 i2c3: i2c@e66d0000 { 289 compatible = "renesas,i2c-r8a77980", 290 "renesas,rcar-gen3-i2c"; 291 reg = <0 0xe66d0000 0 0x40>; 292 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cpg CPG_MOD 928>; 294 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 295 resets = <&cpg 928>; 296 i2c-scl-internal-delay-ns = <6>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 i2c4: i2c@e66d8000 { 303 compatible = "renesas,i2c-r8a77980", 304 "renesas,rcar-gen3-i2c"; 305 reg = <0 0xe66d8000 0 0x40>; 306 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&cpg CPG_MOD 927>; 308 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 309 resets = <&cpg 927>; 310 i2c-scl-internal-delay-ns = <6>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 status = "disabled"; 314 }; 315 316 i2c5: i2c@e66e0000 { 317 compatible = "renesas,i2c-r8a77980", 318 "renesas,rcar-gen3-i2c"; 319 reg = <0 0xe66e0000 0 0x40>; 320 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cpg CPG_MOD 919>; 322 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 323 resets = <&cpg 919>; 324 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 325 <&dmac2 0x9b>, <&dmac2 0x9a>; 326 dma-names = "tx", "rx", "tx", "rx"; 327 i2c-scl-internal-delay-ns = <6>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 status = "disabled"; 331 }; 332 333 hscif0: serial@e6540000 { 334 compatible = "renesas,hscif-r8a77980", 335 "renesas,rcar-gen3-hscif", 336 "renesas,hscif"; 337 reg = <0 0xe6540000 0 0x60>; 338 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cpg CPG_MOD 520>, 340 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 341 <&scif_clk>; 342 clock-names = "fck", "brg_int", "scif_clk"; 343 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 344 <&dmac2 0x31>, <&dmac2 0x30>; 345 dma-names = "tx", "rx", "tx", "rx"; 346 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 347 resets = <&cpg 520>; 348 status = "disabled"; 349 }; 350 351 hscif1: serial@e6550000 { 352 compatible = "renesas,hscif-r8a77980", 353 "renesas,rcar-gen3-hscif", 354 "renesas,hscif"; 355 reg = <0 0xe6550000 0 0x60>; 356 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&cpg CPG_MOD 519>, 358 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 359 <&scif_clk>; 360 clock-names = "fck", "brg_int", "scif_clk"; 361 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 362 <&dmac2 0x33>, <&dmac2 0x32>; 363 dma-names = "tx", "rx", "tx", "rx"; 364 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 365 resets = <&cpg 519>; 366 status = "disabled"; 367 }; 368 369 hscif2: serial@e6560000 { 370 compatible = "renesas,hscif-r8a77980", 371 "renesas,rcar-gen3-hscif", 372 "renesas,hscif"; 373 reg = <0 0xe6560000 0 0x60>; 374 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 518>, 376 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 377 <&scif_clk>; 378 clock-names = "fck", "brg_int", "scif_clk"; 379 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 380 <&dmac2 0x35>, <&dmac2 0x34>; 381 dma-names = "tx", "rx", "tx", "rx"; 382 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 383 resets = <&cpg 518>; 384 status = "disabled"; 385 }; 386 387 hscif3: serial@e66a0000 { 388 compatible = "renesas,hscif-r8a77980", 389 "renesas,rcar-gen3-hscif", 390 "renesas,hscif"; 391 reg = <0 0xe66a0000 0 0x60>; 392 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cpg CPG_MOD 517>, 394 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 395 <&scif_clk>; 396 clock-names = "fck", "brg_int", "scif_clk"; 397 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 398 <&dmac2 0x37>, <&dmac2 0x36>; 399 dma-names = "tx", "rx", "tx", "rx"; 400 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 401 resets = <&cpg 517>; 402 status = "disabled"; 403 }; 404 405 canfd: can@e66c0000 { 406 compatible = "renesas,r8a77980-canfd", 407 "renesas,rcar-gen3-canfd"; 408 reg = <0 0xe66c0000 0 0x8000>; 409 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&cpg CPG_MOD 914>, 412 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 413 <&can_clk>; 414 clock-names = "fck", "canfd", "can_clk"; 415 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 416 assigned-clock-rates = <40000000>; 417 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 418 resets = <&cpg 914>; 419 status = "disabled"; 420 421 channel0 { 422 status = "disabled"; 423 }; 424 425 channel1 { 426 status = "disabled"; 427 }; 428 }; 429 430 ipmmu_ds1: mmu@e7740000 { 431 compatible = "renesas,ipmmu-r8a77980"; 432 reg = <0 0xe7740000 0 0x1000>; 433 renesas,ipmmu-main = <&ipmmu_mm 0>; 434 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 435 #iommu-cells = <1>; 436 }; 437 438 ipmmu_vip0: mmu@e7b00000 { 439 compatible = "renesas,ipmmu-r8a77980"; 440 reg = <0 0xe7b00000 0 0x1000>; 441 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 442 #iommu-cells = <1>; 443 }; 444 445 ipmmu_vip1: mmu@e7960000 { 446 compatible = "renesas,ipmmu-r8a77980"; 447 reg = <0 0xe7960000 0 0x1000>; 448 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 449 #iommu-cells = <1>; 450 }; 451 452 ipmmu_ir: mmu@ff8b0000 { 453 compatible = "renesas,ipmmu-r8a77980"; 454 reg = <0 0xff8b0000 0 0x1000>; 455 renesas,ipmmu-main = <&ipmmu_mm 3>; 456 power-domains = <&sysc R8A77980_PD_A3IR>; 457 #iommu-cells = <1>; 458 }; 459 460 ipmmu_mm: mmu@e67b0000 { 461 compatible = "renesas,ipmmu-r8a77980"; 462 reg = <0 0xe67b0000 0 0x1000>; 463 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 465 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 466 #iommu-cells = <1>; 467 }; 468 469 ipmmu_rt: mmu@ffc80000 { 470 compatible = "renesas,ipmmu-r8a77980"; 471 reg = <0 0xffc80000 0 0x1000>; 472 renesas,ipmmu-main = <&ipmmu_mm 10>; 473 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 474 #iommu-cells = <1>; 475 }; 476 477 ipmmu_vc0: mmu@fe6b0000 { 478 compatible = "renesas,ipmmu-r8a77980"; 479 reg = <0 0xfe6b0000 0 0x1000>; 480 renesas,ipmmu-main = <&ipmmu_mm 12>; 481 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 482 #iommu-cells = <1>; 483 }; 484 485 ipmmu_vi0: mmu@febd0000 { 486 compatible = "renesas,ipmmu-r8a77980"; 487 reg = <0 0xfebd0000 0 0x1000>; 488 renesas,ipmmu-main = <&ipmmu_mm 14>; 489 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 490 #iommu-cells = <1>; 491 }; 492 493 avb: ethernet@e6800000 { 494 compatible = "renesas,etheravb-r8a77980", 495 "renesas,etheravb-rcar-gen3"; 496 reg = <0 0xe6800000 0 0x800>; 497 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "ch0", "ch1", "ch2", "ch3", 523 "ch4", "ch5", "ch6", "ch7", 524 "ch8", "ch9", "ch10", "ch11", 525 "ch12", "ch13", "ch14", "ch15", 526 "ch16", "ch17", "ch18", "ch19", 527 "ch20", "ch21", "ch22", "ch23", 528 "ch24"; 529 clocks = <&cpg CPG_MOD 812>; 530 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 531 resets = <&cpg 812>; 532 phy-mode = "rgmii"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 status = "disabled"; 536 }; 537 538 scif0: serial@e6e60000 { 539 compatible = "renesas,scif-r8a77980", 540 "renesas,rcar-gen3-scif", 541 "renesas,scif"; 542 reg = <0 0xe6e60000 0 0x40>; 543 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cpg CPG_MOD 207>, 545 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 546 <&scif_clk>; 547 clock-names = "fck", "brg_int", "scif_clk"; 548 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 549 <&dmac2 0x51>, <&dmac2 0x50>; 550 dma-names = "tx", "rx", "tx", "rx"; 551 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 552 resets = <&cpg 207>; 553 status = "disabled"; 554 }; 555 556 scif1: serial@e6e68000 { 557 compatible = "renesas,scif-r8a77980", 558 "renesas,rcar-gen3-scif", 559 "renesas,scif"; 560 reg = <0 0xe6e68000 0 0x40>; 561 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&cpg CPG_MOD 206>, 563 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 564 <&scif_clk>; 565 clock-names = "fck", "brg_int", "scif_clk"; 566 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 567 <&dmac2 0x53>, <&dmac2 0x52>; 568 dma-names = "tx", "rx", "tx", "rx"; 569 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 570 resets = <&cpg 206>; 571 status = "disabled"; 572 }; 573 574 scif3: serial@e6c50000 { 575 compatible = "renesas,scif-r8a77980", 576 "renesas,rcar-gen3-scif", 577 "renesas,scif"; 578 reg = <0 0xe6c50000 0 0x40>; 579 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&cpg CPG_MOD 204>, 581 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 582 <&scif_clk>; 583 clock-names = "fck", "brg_int", "scif_clk"; 584 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 585 <&dmac2 0x57>, <&dmac2 0x56>; 586 dma-names = "tx", "rx", "tx", "rx"; 587 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 588 resets = <&cpg 204>; 589 status = "disabled"; 590 }; 591 592 scif4: serial@e6c40000 { 593 compatible = "renesas,scif-r8a77980", 594 "renesas,rcar-gen3-scif", 595 "renesas,scif"; 596 reg = <0 0xe6c40000 0 0x40>; 597 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cpg CPG_MOD 203>, 599 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 600 <&scif_clk>; 601 clock-names = "fck", "brg_int", "scif_clk"; 602 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 603 <&dmac2 0x59>, <&dmac2 0x58>; 604 dma-names = "tx", "rx", "tx", "rx"; 605 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 606 resets = <&cpg 203>; 607 status = "disabled"; 608 }; 609 610 dmac1: dma-controller@e7300000 { 611 compatible = "renesas,dmac-r8a77980", 612 "renesas,rcar-dmac"; 613 reg = <0 0xe7300000 0 0x10000>; 614 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 615 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 616 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 617 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 618 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 619 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 620 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 621 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 622 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 623 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 624 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 625 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 626 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 627 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 628 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 629 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 630 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-names = "error", 632 "ch0", "ch1", "ch2", "ch3", 633 "ch4", "ch5", "ch6", "ch7", 634 "ch8", "ch9", "ch10", "ch11", 635 "ch12", "ch13", "ch14", "ch15"; 636 clocks = <&cpg CPG_MOD 218>; 637 clock-names = "fck"; 638 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 639 resets = <&cpg 218>; 640 #dma-cells = <1>; 641 dma-channels = <16>; 642 }; 643 644 dmac2: dma-controller@e7310000 { 645 compatible = "renesas,dmac-r8a77980", 646 "renesas,rcar-dmac"; 647 reg = <0 0xe7310000 0 0x10000>; 648 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 649 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 650 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 651 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 652 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 653 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 654 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 655 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 656 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 657 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 658 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 659 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 660 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 661 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 662 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 663 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 664 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 665 interrupt-names = "error", 666 "ch0", "ch1", "ch2", "ch3", 667 "ch4", "ch5", "ch6", "ch7", 668 "ch8", "ch9", "ch10", "ch11", 669 "ch12", "ch13", "ch14", "ch15"; 670 clocks = <&cpg CPG_MOD 217>; 671 clock-names = "fck"; 672 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 673 resets = <&cpg 217>; 674 #dma-cells = <1>; 675 dma-channels = <16>; 676 }; 677 678 gether: ethernet@e7400000 { 679 compatible = "renesas,gether-r8a77980"; 680 reg = <0 0xe7400000 0 0x1000>; 681 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD 813>; 683 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 684 resets = <&cpg 813>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 status = "disabled"; 688 }; 689 690 mmc0: mmc@ee140000 { 691 compatible = "renesas,sdhi-r8a77980", 692 "renesas,rcar-gen3-sdhi"; 693 reg = <0 0xee140000 0 0x2000>; 694 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&cpg CPG_MOD 314>; 696 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 697 resets = <&cpg 314>; 698 max-frequency = <200000000>; 699 status = "disabled"; 700 }; 701 702 gic: interrupt-controller@f1010000 { 703 compatible = "arm,gic-400"; 704 #interrupt-cells = <3>; 705 #address-cells = <0>; 706 interrupt-controller; 707 reg = <0x0 0xf1010000 0 0x1000>, 708 <0x0 0xf1020000 0 0x20000>, 709 <0x0 0xf1040000 0 0x20000>, 710 <0x0 0xf1060000 0 0x20000>; 711 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 712 IRQ_TYPE_LEVEL_HIGH)>; 713 clocks = <&cpg CPG_MOD 408>; 714 clock-names = "clk"; 715 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 716 resets = <&cpg 408>; 717 }; 718 719 vspd0: vsp@fea20000 { 720 compatible = "renesas,vsp2"; 721 reg = <0 0xfea20000 0 0x5000>; 722 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD 623>; 724 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 725 resets = <&cpg 623>; 726 renesas,fcp = <&fcpvd0>; 727 }; 728 729 fcpvd0: fcp@fea27000 { 730 compatible = "renesas,fcpv"; 731 reg = <0 0xfea27000 0 0x200>; 732 clocks = <&cpg CPG_MOD 603>; 733 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 734 resets = <&cpg 603>; 735 }; 736 737 du: display@feb00000 { 738 compatible = "renesas,du-r8a77980", 739 "renesas,du-r8a77970"; 740 reg = <0 0xfeb00000 0 0x80000>; 741 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&cpg CPG_MOD 724>; 743 clock-names = "du.0"; 744 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 745 resets = <&cpg 724>; 746 vsps = <&vspd0>; 747 status = "disabled"; 748 749 ports { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 753 port@0 { 754 reg = <0>; 755 du_out_rgb: endpoint { 756 }; 757 }; 758 759 port@1 { 760 reg = <1>; 761 du_out_lvds0: endpoint { 762 remote-endpoint = <&lvds0_in>; 763 }; 764 }; 765 }; 766 }; 767 768 lvds0: lvds-encoder@feb90000 { 769 compatible = "renesas,r8a77980-lvds"; 770 reg = <0 0xfeb90000 0 0x14>; 771 clocks = <&cpg CPG_MOD 727>; 772 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 773 resets = <&cpg 727>; 774 status = "disabled"; 775 776 ports { 777 #address-cells = <1>; 778 #size-cells = <0>; 779 780 port@0 { 781 reg = <0>; 782 lvds0_in: endpoint { 783 remote-endpoint = 784 <&du_out_lvds0>; 785 }; 786 }; 787 788 port@1 { 789 reg = <1>; 790 lvds0_out: endpoint { 791 }; 792 }; 793 }; 794 }; 795 796 prr: chipid@fff00044 { 797 compatible = "renesas,prr"; 798 reg = <0 0xfff00044 0 4>; 799 }; 800 }; 801 802 timer { 803 compatible = "arm,armv8-timer"; 804 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 805 IRQ_TYPE_LEVEL_LOW)>, 806 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 807 IRQ_TYPE_LEVEL_LOW)>, 808 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 809 IRQ_TYPE_LEVEL_LOW)>, 810 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 811 IRQ_TYPE_LEVEL_LOW)>; 812 }; 813}; 814