1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13/ { 14 compatible = "renesas,r8a77980"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 a53_0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53", "arm,armv8"; 25 reg = <0>; 26 clocks = <&cpg CPG_CORE 0>; 27 power-domains = <&sysc 5>; 28 next-level-cache = <&L2_CA53>; 29 enable-method = "psci"; 30 }; 31 32 L2_CA53: cache-controller { 33 compatible = "cache"; 34 power-domains = <&sysc 21>; 35 cache-unified; 36 cache-level = <2>; 37 }; 38 }; 39 40 extal_clk: extal { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 /* This value must be overridden by the board */ 44 clock-frequency = <0>; 45 }; 46 47 extalr_clk: extalr { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 /* This value must be overridden by the board */ 51 clock-frequency = <0>; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2"; 56 method = "smc"; 57 }; 58 59 /* External SCIF clock - to be overridden by boards that provide it */ 60 scif_clk: scif { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <0>; 64 }; 65 66 soc { 67 compatible = "simple-bus"; 68 interrupt-parent = <&gic>; 69 70 #address-cells = <2>; 71 #size-cells = <2>; 72 ranges; 73 74 cpg: clock-controller@e6150000 { 75 compatible = "renesas,r8a77980-cpg-mssr"; 76 reg = <0 0xe6150000 0 0x1000>; 77 clocks = <&extal_clk>, <&extalr_clk>; 78 clock-names = "extal", "extalr"; 79 #clock-cells = <2>; 80 #power-domain-cells = <0>; 81 #reset-cells = <1>; 82 }; 83 84 rst: reset-controller@e6160000 { 85 compatible = "renesas,r8a77980-rst"; 86 reg = <0 0xe6160000 0 0x200>; 87 }; 88 89 sysc: system-controller@e6180000 { 90 compatible = "renesas,r8a77980-sysc"; 91 reg = <0 0xe6180000 0 0x440>; 92 #power-domain-cells = <1>; 93 }; 94 95 hscif0: serial@e6540000 { 96 compatible = "renesas,hscif-r8a77980", 97 "renesas,rcar-gen3-hscif", 98 "renesas,hscif"; 99 reg = <0 0xe6540000 0 0x60>; 100 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&cpg CPG_MOD 520>, 102 <&cpg CPG_CORE 19>, 103 <&scif_clk>; 104 clock-names = "fck", "brg_int", "scif_clk"; 105 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 106 <&dmac2 0x31>, <&dmac2 0x30>; 107 dma-names = "tx", "rx", "tx", "rx"; 108 power-domains = <&sysc 32>; 109 resets = <&cpg 520>; 110 status = "disabled"; 111 }; 112 113 hscif1: serial@e6550000 { 114 compatible = "renesas,hscif-r8a77980", 115 "renesas,rcar-gen3-hscif", 116 "renesas,hscif"; 117 reg = <0 0xe6550000 0 0x60>; 118 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&cpg CPG_MOD 519>, 120 <&cpg CPG_CORE 19>, 121 <&scif_clk>; 122 clock-names = "fck", "brg_int", "scif_clk"; 123 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 124 <&dmac2 0x33>, <&dmac2 0x32>; 125 dma-names = "tx", "rx", "tx", "rx"; 126 power-domains = <&sysc 32>; 127 resets = <&cpg 519>; 128 status = "disabled"; 129 }; 130 131 hscif2: serial@e6560000 { 132 compatible = "renesas,hscif-r8a77980", 133 "renesas,rcar-gen3-hscif", 134 "renesas,hscif"; 135 reg = <0 0xe6560000 0 0x60>; 136 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&cpg CPG_MOD 518>, 138 <&cpg CPG_CORE 19>, 139 <&scif_clk>; 140 clock-names = "fck", "brg_int", "scif_clk"; 141 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 142 <&dmac2 0x35>, <&dmac2 0x34>; 143 dma-names = "tx", "rx", "tx", "rx"; 144 power-domains = <&sysc 32>; 145 resets = <&cpg 518>; 146 status = "disabled"; 147 }; 148 149 hscif3: serial@e66a0000 { 150 compatible = "renesas,hscif-r8a77980", 151 "renesas,rcar-gen3-hscif", 152 "renesas,hscif"; 153 reg = <0 0xe66a0000 0 0x60>; 154 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&cpg CPG_MOD 517>, 156 <&cpg CPG_CORE 19>, 157 <&scif_clk>; 158 clock-names = "fck", "brg_int", "scif_clk"; 159 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 160 <&dmac2 0x37>, <&dmac2 0x36>; 161 dma-names = "tx", "rx", "tx", "rx"; 162 power-domains = <&sysc 32>; 163 resets = <&cpg 517>; 164 status = "disabled"; 165 }; 166 167 scif0: serial@e6e60000 { 168 compatible = "renesas,scif-r8a77980", 169 "renesas,rcar-gen3-scif", 170 "renesas,scif"; 171 reg = <0 0xe6e60000 0 0x40>; 172 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&cpg CPG_MOD 207>, 174 <&cpg CPG_CORE 19>, 175 <&scif_clk>; 176 clock-names = "fck", "brg_int", "scif_clk"; 177 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 178 <&dmac2 0x51>, <&dmac2 0x50>; 179 dma-names = "tx", "rx", "tx", "rx"; 180 power-domains = <&sysc 32>; 181 resets = <&cpg 207>; 182 status = "disabled"; 183 }; 184 185 scif1: serial@e6e68000 { 186 compatible = "renesas,scif-r8a77980", 187 "renesas,rcar-gen3-scif", 188 "renesas,scif"; 189 reg = <0 0xe6e68000 0 0x40>; 190 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&cpg CPG_MOD 206>, 192 <&cpg CPG_CORE 19>, 193 <&scif_clk>; 194 clock-names = "fck", "brg_int", "scif_clk"; 195 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 196 <&dmac2 0x53>, <&dmac2 0x52>; 197 dma-names = "tx", "rx", "tx", "rx"; 198 power-domains = <&sysc 32>; 199 resets = <&cpg 206>; 200 status = "disabled"; 201 }; 202 203 scif3: serial@e6c50000 { 204 compatible = "renesas,scif-r8a77980", 205 "renesas,rcar-gen3-scif", 206 "renesas,scif"; 207 reg = <0 0xe6c50000 0 0x40>; 208 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&cpg CPG_MOD 204>, 210 <&cpg CPG_CORE 19>, 211 <&scif_clk>; 212 clock-names = "fck", "brg_int", "scif_clk"; 213 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 214 <&dmac2 0x57>, <&dmac2 0x56>; 215 dma-names = "tx", "rx", "tx", "rx"; 216 power-domains = <&sysc 32>; 217 resets = <&cpg 204>; 218 status = "disabled"; 219 }; 220 221 scif4: serial@e6c40000 { 222 compatible = "renesas,scif-r8a77980", 223 "renesas,rcar-gen3-scif", 224 "renesas,scif"; 225 reg = <0 0xe6c40000 0 0x40>; 226 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cpg CPG_MOD 203>, 228 <&cpg CPG_CORE 19>, 229 <&scif_clk>; 230 clock-names = "fck", "brg_int", "scif_clk"; 231 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 232 <&dmac2 0x59>, <&dmac2 0x58>; 233 dma-names = "tx", "rx", "tx", "rx"; 234 power-domains = <&sysc 32>; 235 resets = <&cpg 203>; 236 status = "disabled"; 237 }; 238 239 dmac1: dma-controller@e7300000 { 240 compatible = "renesas,dmac-r8a77980", 241 "renesas,rcar-dmac"; 242 reg = <0 0xe7300000 0 0x10000>; 243 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 246 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 247 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 248 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 249 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 250 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 251 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 252 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 253 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 254 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 255 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 256 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 257 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 258 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 259 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-names = "error", 261 "ch0", "ch1", "ch2", "ch3", 262 "ch4", "ch5", "ch6", "ch7", 263 "ch8", "ch9", "ch10", "ch11", 264 "ch12", "ch13", "ch14", "ch15"; 265 clocks = <&cpg CPG_MOD 218>; 266 clock-names = "fck"; 267 power-domains = <&sysc 32>; 268 resets = <&cpg 218>; 269 #dma-cells = <1>; 270 dma-channels = <16>; 271 }; 272 273 dmac2: dma-controller@e7310000 { 274 compatible = "renesas,dmac-r8a77980", 275 "renesas,rcar-dmac"; 276 reg = <0 0xe7310000 0 0x10000>; 277 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 278 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 279 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 280 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 281 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 282 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 283 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 284 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 285 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 286 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 287 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 288 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 289 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 290 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 291 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 292 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 293 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 294 interrupt-names = "error", 295 "ch0", "ch1", "ch2", "ch3", 296 "ch4", "ch5", "ch6", "ch7", 297 "ch8", "ch9", "ch10", "ch11", 298 "ch12", "ch13", "ch14", "ch15"; 299 clocks = <&cpg CPG_MOD 217>; 300 clock-names = "fck"; 301 power-domains = <&sysc 32>; 302 resets = <&cpg 217>; 303 #dma-cells = <1>; 304 dma-channels = <16>; 305 }; 306 307 gic: interrupt-controller@f1010000 { 308 compatible = "arm,gic-400"; 309 #interrupt-cells = <3>; 310 #address-cells = <0>; 311 interrupt-controller; 312 reg = <0x0 0xf1010000 0 0x1000>, 313 <0x0 0xf1020000 0 0x20000>, 314 <0x0 0xf1040000 0 0x20000>, 315 <0x0 0xf1060000 0 0x20000>; 316 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 317 IRQ_TYPE_LEVEL_HIGH)>; 318 clocks = <&cpg CPG_MOD 408>; 319 clock-names = "clk"; 320 power-domains = <&sysc 32>; 321 resets = <&cpg 408>; 322 }; 323 324 prr: chipid@fff00044 { 325 compatible = "renesas,prr"; 326 reg = <0 0xfff00044 0 4>; 327 }; 328 }; 329 330 timer { 331 compatible = "arm,armv8-timer"; 332 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 333 IRQ_TYPE_LEVEL_LOW)>, 334 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 335 IRQ_TYPE_LEVEL_LOW)>, 336 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 337 IRQ_TYPE_LEVEL_LOW)>, 338 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 339 IRQ_TYPE_LEVEL_LOW)>; 340 }; 341}; 342