1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 }; 27 28 /* External CAN clock - to be overridden by boards that provide it */ 29 can_clk: can { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 a53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0>; 43 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 45 next-level-cache = <&L2_CA53>; 46 enable-method = "psci"; 47 }; 48 49 a53_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <1>; 53 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 55 next-level-cache = <&L2_CA53>; 56 enable-method = "psci"; 57 }; 58 59 a53_2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53", "arm,armv8"; 62 reg = <2>; 63 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 65 next-level-cache = <&L2_CA53>; 66 enable-method = "psci"; 67 }; 68 69 a53_3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <3>; 73 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 75 next-level-cache = <&L2_CA53>; 76 enable-method = "psci"; 77 }; 78 79 L2_CA53: cache-controller { 80 compatible = "cache"; 81 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 82 cache-unified; 83 cache-level = <2>; 84 }; 85 }; 86 87 extal_clk: extal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 }; 93 94 extalr_clk: extalr { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board */ 98 clock-frequency = <0>; 99 }; 100 101 /* External PCIe clock - can be overridden by the board */ 102 pcie_bus_clk: pcie_bus { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 pmu_a53 { 109 compatible = "arm,cortex-a53-pmu"; 110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 111 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 112 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 113 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0", "arm,psci-0.2"; 119 method = "smc"; 120 }; 121 122 /* External SCIF clock - to be overridden by boards that provide it */ 123 scif_clk: scif { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 interrupt-parent = <&gic>; 132 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 rwdt: watchdog@e6020000 { 138 compatible = "renesas,r8a77980-wdt", 139 "renesas,rcar-gen3-wdt"; 140 reg = <0 0xe6020000 0 0x0c>; 141 clocks = <&cpg CPG_MOD 402>; 142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 143 resets = <&cpg 402>; 144 status = "disabled"; 145 }; 146 147 gpio0: gpio@e6050000 { 148 compatible = "renesas,gpio-r8a77980", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6050000 0 0x50>; 151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 0 22>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 912>; 158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 159 resets = <&cpg 912>; 160 }; 161 162 gpio1: gpio@e6051000 { 163 compatible = "renesas,gpio-r8a77980", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6051000 0 0x50>; 166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 32 28>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 911>; 173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 174 resets = <&cpg 911>; 175 }; 176 177 gpio2: gpio@e6052000 { 178 compatible = "renesas,gpio-r8a77980", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6052000 0 0x50>; 181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 64 30>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 910>; 188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 189 resets = <&cpg 910>; 190 }; 191 192 gpio3: gpio@e6053000 { 193 compatible = "renesas,gpio-r8a77980", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6053000 0 0x50>; 196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 96 17>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 909>; 203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 204 resets = <&cpg 909>; 205 }; 206 207 gpio4: gpio@e6054000 { 208 compatible = "renesas,gpio-r8a77980", 209 "renesas,rcar-gen3-gpio"; 210 reg = <0 0xe6054000 0 0x50>; 211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 212 #gpio-cells = <2>; 213 gpio-controller; 214 gpio-ranges = <&pfc 0 128 25>; 215 #interrupt-cells = <2>; 216 interrupt-controller; 217 clocks = <&cpg CPG_MOD 908>; 218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 219 resets = <&cpg 908>; 220 }; 221 222 gpio5: gpio@e6055000 { 223 compatible = "renesas,gpio-r8a77980", 224 "renesas,rcar-gen3-gpio"; 225 reg = <0 0xe6055000 0 0x50>; 226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 227 #gpio-cells = <2>; 228 gpio-controller; 229 gpio-ranges = <&pfc 0 160 15>; 230 #interrupt-cells = <2>; 231 interrupt-controller; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 }; 236 237 pfc: pin-controller@e6060000 { 238 compatible = "renesas,pfc-r8a77980"; 239 reg = <0 0xe6060000 0 0x50c>; 240 }; 241 242 cmt0: timer@e60f0000 { 243 compatible = "renesas,r8a77980-cmt0", 244 "renesas,rcar-gen3-cmt0"; 245 reg = <0 0xe60f0000 0 0x1004>; 246 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cpg CPG_MOD 303>; 249 clock-names = "fck"; 250 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 251 resets = <&cpg 303>; 252 status = "disabled"; 253 }; 254 255 cmt1: timer@e6130000 { 256 compatible = "renesas,r8a77980-cmt1", 257 "renesas,rcar-gen3-cmt1"; 258 reg = <0 0xe6130000 0 0x1004>; 259 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 302>; 268 clock-names = "fck"; 269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 270 resets = <&cpg 302>; 271 status = "disabled"; 272 }; 273 274 cmt2: timer@e6140000 { 275 compatible = "renesas,r8a77980-cmt1", 276 "renesas,rcar-gen3-cmt1"; 277 reg = <0 0xe6140000 0 0x1004>; 278 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 301>; 287 clock-names = "fck"; 288 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 289 resets = <&cpg 301>; 290 status = "disabled"; 291 }; 292 293 cmt3: timer@e6148000 { 294 compatible = "renesas,r8a77980-cmt1", 295 "renesas,rcar-gen3-cmt1"; 296 reg = <0 0xe6148000 0 0x1004>; 297 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cpg CPG_MOD 300>; 306 clock-names = "fck"; 307 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 308 resets = <&cpg 300>; 309 status = "disabled"; 310 }; 311 312 cpg: clock-controller@e6150000 { 313 compatible = "renesas,r8a77980-cpg-mssr"; 314 reg = <0 0xe6150000 0 0x1000>; 315 clocks = <&extal_clk>, <&extalr_clk>; 316 clock-names = "extal", "extalr"; 317 #clock-cells = <2>; 318 #power-domain-cells = <0>; 319 #reset-cells = <1>; 320 }; 321 322 rst: reset-controller@e6160000 { 323 compatible = "renesas,r8a77980-rst"; 324 reg = <0 0xe6160000 0 0x200>; 325 }; 326 327 sysc: system-controller@e6180000 { 328 compatible = "renesas,r8a77980-sysc"; 329 reg = <0 0xe6180000 0 0x440>; 330 #power-domain-cells = <1>; 331 }; 332 333 intc_ex: interrupt-controller@e61c0000 { 334 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 335 #interrupt-cells = <2>; 336 interrupt-controller; 337 reg = <0 0xe61c0000 0 0x200>; 338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cpg CPG_MOD 407>; 345 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 346 resets = <&cpg 407>; 347 }; 348 349 i2c0: i2c@e6500000 { 350 compatible = "renesas,i2c-r8a77980", 351 "renesas,rcar-gen3-i2c"; 352 reg = <0 0xe6500000 0 0x40>; 353 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cpg CPG_MOD 931>; 355 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 356 resets = <&cpg 931>; 357 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 358 <&dmac2 0x91>, <&dmac2 0x90>; 359 dma-names = "tx", "rx", "tx", "rx"; 360 i2c-scl-internal-delay-ns = <6>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 i2c1: i2c@e6508000 { 367 compatible = "renesas,i2c-r8a77980", 368 "renesas,rcar-gen3-i2c"; 369 reg = <0 0xe6508000 0 0x40>; 370 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&cpg CPG_MOD 930>; 372 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 373 resets = <&cpg 930>; 374 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 375 <&dmac2 0x93>, <&dmac2 0x92>; 376 dma-names = "tx", "rx", "tx", "rx"; 377 i2c-scl-internal-delay-ns = <6>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 status = "disabled"; 381 }; 382 383 i2c2: i2c@e6510000 { 384 compatible = "renesas,i2c-r8a77980", 385 "renesas,rcar-gen3-i2c"; 386 reg = <0 0xe6510000 0 0x40>; 387 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&cpg CPG_MOD 929>; 389 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 390 resets = <&cpg 929>; 391 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 392 <&dmac2 0x95>, <&dmac2 0x94>; 393 dma-names = "tx", "rx", "tx", "rx"; 394 i2c-scl-internal-delay-ns = <6>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 status = "disabled"; 398 }; 399 400 i2c3: i2c@e66d0000 { 401 compatible = "renesas,i2c-r8a77980", 402 "renesas,rcar-gen3-i2c"; 403 reg = <0 0xe66d0000 0 0x40>; 404 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cpg CPG_MOD 928>; 406 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 407 resets = <&cpg 928>; 408 i2c-scl-internal-delay-ns = <6>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c4: i2c@e66d8000 { 415 compatible = "renesas,i2c-r8a77980", 416 "renesas,rcar-gen3-i2c"; 417 reg = <0 0xe66d8000 0 0x40>; 418 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cpg CPG_MOD 927>; 420 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 421 resets = <&cpg 927>; 422 i2c-scl-internal-delay-ns = <6>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c5: i2c@e66e0000 { 429 compatible = "renesas,i2c-r8a77980", 430 "renesas,rcar-gen3-i2c"; 431 reg = <0 0xe66e0000 0 0x40>; 432 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cpg CPG_MOD 919>; 434 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 435 resets = <&cpg 919>; 436 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 437 <&dmac2 0x9b>, <&dmac2 0x9a>; 438 dma-names = "tx", "rx", "tx", "rx"; 439 i2c-scl-internal-delay-ns = <6>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 hscif0: serial@e6540000 { 446 compatible = "renesas,hscif-r8a77980", 447 "renesas,rcar-gen3-hscif", 448 "renesas,hscif"; 449 reg = <0 0xe6540000 0 0x60>; 450 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cpg CPG_MOD 520>, 452 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 453 <&scif_clk>; 454 clock-names = "fck", "brg_int", "scif_clk"; 455 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 456 <&dmac2 0x31>, <&dmac2 0x30>; 457 dma-names = "tx", "rx", "tx", "rx"; 458 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 459 resets = <&cpg 520>; 460 status = "disabled"; 461 }; 462 463 hscif1: serial@e6550000 { 464 compatible = "renesas,hscif-r8a77980", 465 "renesas,rcar-gen3-hscif", 466 "renesas,hscif"; 467 reg = <0 0xe6550000 0 0x60>; 468 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cpg CPG_MOD 519>, 470 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 471 <&scif_clk>; 472 clock-names = "fck", "brg_int", "scif_clk"; 473 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 474 <&dmac2 0x33>, <&dmac2 0x32>; 475 dma-names = "tx", "rx", "tx", "rx"; 476 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 477 resets = <&cpg 519>; 478 status = "disabled"; 479 }; 480 481 hscif2: serial@e6560000 { 482 compatible = "renesas,hscif-r8a77980", 483 "renesas,rcar-gen3-hscif", 484 "renesas,hscif"; 485 reg = <0 0xe6560000 0 0x60>; 486 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 518>, 488 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 489 <&scif_clk>; 490 clock-names = "fck", "brg_int", "scif_clk"; 491 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 492 <&dmac2 0x35>, <&dmac2 0x34>; 493 dma-names = "tx", "rx", "tx", "rx"; 494 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 495 resets = <&cpg 518>; 496 status = "disabled"; 497 }; 498 499 hscif3: serial@e66a0000 { 500 compatible = "renesas,hscif-r8a77980", 501 "renesas,rcar-gen3-hscif", 502 "renesas,hscif"; 503 reg = <0 0xe66a0000 0 0x60>; 504 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 517>, 506 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 507 <&scif_clk>; 508 clock-names = "fck", "brg_int", "scif_clk"; 509 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 510 <&dmac2 0x37>, <&dmac2 0x36>; 511 dma-names = "tx", "rx", "tx", "rx"; 512 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 513 resets = <&cpg 517>; 514 status = "disabled"; 515 }; 516 517 pcie_phy: pcie-phy@e65d0000 { 518 compatible = "renesas,r8a77980-pcie-phy"; 519 reg = <0 0xe65d0000 0 0x8000>; 520 #phy-cells = <0>; 521 clocks = <&cpg CPG_MOD 319>; 522 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 523 resets = <&cpg 319>; 524 status = "disabled"; 525 }; 526 527 canfd: can@e66c0000 { 528 compatible = "renesas,r8a77980-canfd", 529 "renesas,rcar-gen3-canfd"; 530 reg = <0 0xe66c0000 0 0x8000>; 531 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cpg CPG_MOD 914>, 534 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 535 <&can_clk>; 536 clock-names = "fck", "canfd", "can_clk"; 537 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 538 assigned-clock-rates = <40000000>; 539 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 540 resets = <&cpg 914>; 541 status = "disabled"; 542 543 channel0 { 544 status = "disabled"; 545 }; 546 547 channel1 { 548 status = "disabled"; 549 }; 550 }; 551 552 avb: ethernet@e6800000 { 553 compatible = "renesas,etheravb-r8a77980", 554 "renesas,etheravb-rcar-gen3"; 555 reg = <0 0xe6800000 0 0x800>; 556 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 581 interrupt-names = "ch0", "ch1", "ch2", "ch3", 582 "ch4", "ch5", "ch6", "ch7", 583 "ch8", "ch9", "ch10", "ch11", 584 "ch12", "ch13", "ch14", "ch15", 585 "ch16", "ch17", "ch18", "ch19", 586 "ch20", "ch21", "ch22", "ch23", 587 "ch24"; 588 clocks = <&cpg CPG_MOD 812>; 589 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 590 resets = <&cpg 812>; 591 phy-mode = "rgmii"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 scif0: serial@e6e60000 { 598 compatible = "renesas,scif-r8a77980", 599 "renesas,rcar-gen3-scif", 600 "renesas,scif"; 601 reg = <0 0xe6e60000 0 0x40>; 602 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cpg CPG_MOD 207>, 604 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 605 <&scif_clk>; 606 clock-names = "fck", "brg_int", "scif_clk"; 607 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 608 <&dmac2 0x51>, <&dmac2 0x50>; 609 dma-names = "tx", "rx", "tx", "rx"; 610 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 611 resets = <&cpg 207>; 612 status = "disabled"; 613 }; 614 615 scif1: serial@e6e68000 { 616 compatible = "renesas,scif-r8a77980", 617 "renesas,rcar-gen3-scif", 618 "renesas,scif"; 619 reg = <0 0xe6e68000 0 0x40>; 620 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD 206>, 622 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 623 <&scif_clk>; 624 clock-names = "fck", "brg_int", "scif_clk"; 625 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 626 <&dmac2 0x53>, <&dmac2 0x52>; 627 dma-names = "tx", "rx", "tx", "rx"; 628 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 629 resets = <&cpg 206>; 630 status = "disabled"; 631 }; 632 633 scif3: serial@e6c50000 { 634 compatible = "renesas,scif-r8a77980", 635 "renesas,rcar-gen3-scif", 636 "renesas,scif"; 637 reg = <0 0xe6c50000 0 0x40>; 638 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cpg CPG_MOD 204>, 640 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 641 <&scif_clk>; 642 clock-names = "fck", "brg_int", "scif_clk"; 643 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 644 <&dmac2 0x57>, <&dmac2 0x56>; 645 dma-names = "tx", "rx", "tx", "rx"; 646 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 647 resets = <&cpg 204>; 648 status = "disabled"; 649 }; 650 651 scif4: serial@e6c40000 { 652 compatible = "renesas,scif-r8a77980", 653 "renesas,rcar-gen3-scif", 654 "renesas,scif"; 655 reg = <0 0xe6c40000 0 0x40>; 656 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD 203>, 658 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 659 <&scif_clk>; 660 clock-names = "fck", "brg_int", "scif_clk"; 661 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 662 <&dmac2 0x59>, <&dmac2 0x58>; 663 dma-names = "tx", "rx", "tx", "rx"; 664 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 665 resets = <&cpg 203>; 666 status = "disabled"; 667 }; 668 669 tpu: pwm@e6e80000 { 670 compatible = "renesas,tpu-r8a77980", "renesas,tpu"; 671 reg = <0 0xe6e80000 0 0x148>; 672 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cpg CPG_MOD 304>; 674 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 675 resets = <&cpg 304>; 676 #pwm-cells = <3>; 677 status = "disabled"; 678 }; 679 680 vin0: video@e6ef0000 { 681 compatible = "renesas,vin-r8a77980"; 682 reg = <0 0xe6ef0000 0 0x1000>; 683 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 811>; 685 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 686 resets = <&cpg 811>; 687 status = "disabled"; 688 689 ports { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 693 port@1 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 reg = <1>; 698 699 vin0csi40: endpoint@2 { 700 reg = <2>; 701 remote-endpoint = <&csi40vin0>; 702 }; 703 }; 704 }; 705 }; 706 707 vin1: video@e6ef1000 { 708 compatible = "renesas,vin-r8a77980"; 709 reg = <0 0xe6ef1000 0 0x1000>; 710 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cpg CPG_MOD 810>; 712 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 713 status = "disabled"; 714 resets = <&cpg 810>; 715 716 ports { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 720 port@1 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 724 reg = <1>; 725 726 vin1csi40: endpoint@2 { 727 reg = <2>; 728 remote-endpoint = <&csi40vin1>; 729 }; 730 }; 731 }; 732 }; 733 734 vin2: video@e6ef2000 { 735 compatible = "renesas,vin-r8a77980"; 736 reg = <0 0xe6ef2000 0 0x1000>; 737 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD 809>; 739 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 740 resets = <&cpg 809>; 741 status = "disabled"; 742 743 ports { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 747 port@1 { 748 #address-cells = <1>; 749 #size-cells = <0>; 750 751 reg = <1>; 752 753 vin2csi40: endpoint@2 { 754 reg = <2>; 755 remote-endpoint = <&csi40vin2>; 756 }; 757 }; 758 }; 759 }; 760 761 vin3: video@e6ef3000 { 762 compatible = "renesas,vin-r8a77980"; 763 reg = <0 0xe6ef3000 0 0x1000>; 764 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&cpg CPG_MOD 808>; 766 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 767 resets = <&cpg 808>; 768 status = "disabled"; 769 770 ports { 771 #address-cells = <1>; 772 #size-cells = <0>; 773 774 port@1 { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 778 reg = <1>; 779 780 vin3csi40: endpoint@2 { 781 reg = <2>; 782 remote-endpoint = <&csi40vin3>; 783 }; 784 }; 785 }; 786 }; 787 788 vin4: video@e6ef4000 { 789 compatible = "renesas,vin-r8a77980"; 790 reg = <0 0xe6ef4000 0 0x1000>; 791 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cpg CPG_MOD 807>; 793 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 794 resets = <&cpg 807>; 795 status = "disabled"; 796 797 ports { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 port@1 { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 805 reg = <1>; 806 807 vin4csi41: endpoint@2 { 808 reg = <2>; 809 remote-endpoint = <&csi41vin4>; 810 }; 811 }; 812 }; 813 }; 814 815 vin5: video@e6ef5000 { 816 compatible = "renesas,vin-r8a77980"; 817 reg = <0 0xe6ef5000 0 0x1000>; 818 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&cpg CPG_MOD 806>; 820 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 821 resets = <&cpg 806>; 822 status = "disabled"; 823 824 ports { 825 #address-cells = <1>; 826 #size-cells = <0>; 827 828 port@1 { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 reg = <1>; 833 834 vin5csi41: endpoint@2 { 835 reg = <2>; 836 remote-endpoint = <&csi41vin5>; 837 }; 838 }; 839 }; 840 }; 841 842 vin6: video@e6ef6000 { 843 compatible = "renesas,vin-r8a77980"; 844 reg = <0 0xe6ef6000 0 0x1000>; 845 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&cpg CPG_MOD 805>; 847 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 848 resets = <&cpg 805>; 849 status = "disabled"; 850 851 ports { 852 #address-cells = <1>; 853 #size-cells = <0>; 854 855 port@1 { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 859 reg = <1>; 860 861 vin6csi41: endpoint@2 { 862 reg = <2>; 863 remote-endpoint = <&csi41vin6>; 864 }; 865 }; 866 }; 867 }; 868 869 vin7: video@e6ef7000 { 870 compatible = "renesas,vin-r8a77980"; 871 reg = <0 0xe6ef7000 0 0x1000>; 872 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cpg CPG_MOD 804>; 874 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 875 resets = <&cpg 804>; 876 status = "disabled"; 877 878 ports { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 port@1 { 883 #address-cells = <1>; 884 #size-cells = <0>; 885 886 reg = <1>; 887 888 vin7csi41: endpoint@2 { 889 reg = <2>; 890 remote-endpoint = <&csi41vin7>; 891 }; 892 }; 893 }; 894 }; 895 896 vin8: video@e6ef8000 { 897 compatible = "renesas,vin-r8a77980"; 898 reg = <0 0xe6ef8000 0 0x1000>; 899 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&cpg CPG_MOD 628>; 901 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 902 resets = <&cpg 628>; 903 status = "disabled"; 904 }; 905 906 vin9: video@e6ef9000 { 907 compatible = "renesas,vin-r8a77980"; 908 reg = <0 0xe6ef9000 0 0x1000>; 909 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&cpg CPG_MOD 627>; 911 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 912 resets = <&cpg 627>; 913 status = "disabled"; 914 }; 915 916 vin10: video@e6efa000 { 917 compatible = "renesas,vin-r8a77980"; 918 reg = <0 0xe6efa000 0 0x1000>; 919 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&cpg CPG_MOD 625>; 921 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 922 resets = <&cpg 625>; 923 status = "disabled"; 924 }; 925 926 vin11: video@e6efb000 { 927 compatible = "renesas,vin-r8a77980"; 928 reg = <0 0xe6efb000 0 0x1000>; 929 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&cpg CPG_MOD 618>; 931 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 932 resets = <&cpg 618>; 933 status = "disabled"; 934 }; 935 936 vin12: video@e6efc000 { 937 compatible = "renesas,vin-r8a77980"; 938 reg = <0 0xe6efc000 0 0x1000>; 939 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&cpg CPG_MOD 612>; 941 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 942 resets = <&cpg 612>; 943 status = "disabled"; 944 }; 945 946 vin13: video@e6efd000 { 947 compatible = "renesas,vin-r8a77980"; 948 reg = <0 0xe6efd000 0 0x1000>; 949 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cpg CPG_MOD 608>; 951 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 952 resets = <&cpg 608>; 953 status = "disabled"; 954 }; 955 956 vin14: video@e6efe000 { 957 compatible = "renesas,vin-r8a77980"; 958 reg = <0 0xe6efe000 0 0x1000>; 959 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cpg CPG_MOD 605>; 961 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 962 resets = <&cpg 605>; 963 status = "disabled"; 964 }; 965 966 vin15: video@e6eff000 { 967 compatible = "renesas,vin-r8a77980"; 968 reg = <0 0xe6eff000 0 0x1000>; 969 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&cpg CPG_MOD 604>; 971 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 972 resets = <&cpg 604>; 973 status = "disabled"; 974 }; 975 976 dmac1: dma-controller@e7300000 { 977 compatible = "renesas,dmac-r8a77980", 978 "renesas,rcar-dmac"; 979 reg = <0 0xe7300000 0 0x10000>; 980 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 981 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 982 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 983 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 984 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 985 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 986 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 987 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 988 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 989 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 990 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 991 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 992 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 993 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 994 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 995 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 996 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-names = "error", 998 "ch0", "ch1", "ch2", "ch3", 999 "ch4", "ch5", "ch6", "ch7", 1000 "ch8", "ch9", "ch10", "ch11", 1001 "ch12", "ch13", "ch14", "ch15"; 1002 clocks = <&cpg CPG_MOD 218>; 1003 clock-names = "fck"; 1004 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1005 resets = <&cpg 218>; 1006 #dma-cells = <1>; 1007 dma-channels = <16>; 1008 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1009 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1010 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1011 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1012 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1013 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1014 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1015 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1016 }; 1017 1018 dmac2: dma-controller@e7310000 { 1019 compatible = "renesas,dmac-r8a77980", 1020 "renesas,rcar-dmac"; 1021 reg = <0 0xe7310000 0 0x10000>; 1022 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 1023 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 1024 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 1025 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 1026 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 1027 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 1028 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 1029 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 1030 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 1031 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 1032 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 1033 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 1034 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 1035 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 1036 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 1037 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 1038 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1039 interrupt-names = "error", 1040 "ch0", "ch1", "ch2", "ch3", 1041 "ch4", "ch5", "ch6", "ch7", 1042 "ch8", "ch9", "ch10", "ch11", 1043 "ch12", "ch13", "ch14", "ch15"; 1044 clocks = <&cpg CPG_MOD 217>; 1045 clock-names = "fck"; 1046 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1047 resets = <&cpg 217>; 1048 #dma-cells = <1>; 1049 dma-channels = <16>; 1050 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1051 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1052 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1053 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1054 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1055 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1056 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1057 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1058 }; 1059 1060 gether: ethernet@e7400000 { 1061 compatible = "renesas,gether-r8a77980"; 1062 reg = <0 0xe7400000 0 0x1000>; 1063 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&cpg CPG_MOD 813>; 1065 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1066 resets = <&cpg 813>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 ipmmu_ds1: mmu@e7740000 { 1073 compatible = "renesas,ipmmu-r8a77980"; 1074 reg = <0 0xe7740000 0 0x1000>; 1075 renesas,ipmmu-main = <&ipmmu_mm 0>; 1076 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1077 #iommu-cells = <1>; 1078 }; 1079 1080 ipmmu_ir: mmu@ff8b0000 { 1081 compatible = "renesas,ipmmu-r8a77980"; 1082 reg = <0 0xff8b0000 0 0x1000>; 1083 renesas,ipmmu-main = <&ipmmu_mm 3>; 1084 power-domains = <&sysc R8A77980_PD_A3IR>; 1085 #iommu-cells = <1>; 1086 }; 1087 1088 ipmmu_mm: mmu@e67b0000 { 1089 compatible = "renesas,ipmmu-r8a77980"; 1090 reg = <0 0xe67b0000 0 0x1000>; 1091 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1093 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1094 #iommu-cells = <1>; 1095 }; 1096 1097 ipmmu_rt: mmu@ffc80000 { 1098 compatible = "renesas,ipmmu-r8a77980"; 1099 reg = <0 0xffc80000 0 0x1000>; 1100 renesas,ipmmu-main = <&ipmmu_mm 10>; 1101 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1102 #iommu-cells = <1>; 1103 }; 1104 1105 ipmmu_vc0: mmu@fe6b0000 { 1106 compatible = "renesas,ipmmu-r8a77980"; 1107 reg = <0 0xfe6b0000 0 0x1000>; 1108 renesas,ipmmu-main = <&ipmmu_mm 12>; 1109 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1110 #iommu-cells = <1>; 1111 }; 1112 1113 ipmmu_vi0: mmu@febd0000 { 1114 compatible = "renesas,ipmmu-r8a77980"; 1115 reg = <0 0xfebd0000 0 0x1000>; 1116 renesas,ipmmu-main = <&ipmmu_mm 14>; 1117 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1118 #iommu-cells = <1>; 1119 }; 1120 1121 ipmmu_vip0: mmu@e7b00000 { 1122 compatible = "renesas,ipmmu-r8a77980"; 1123 reg = <0 0xe7b00000 0 0x1000>; 1124 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1125 #iommu-cells = <1>; 1126 }; 1127 1128 ipmmu_vip1: mmu@e7960000 { 1129 compatible = "renesas,ipmmu-r8a77980"; 1130 reg = <0 0xe7960000 0 0x1000>; 1131 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1132 #iommu-cells = <1>; 1133 }; 1134 1135 mmc0: mmc@ee140000 { 1136 compatible = "renesas,sdhi-r8a77980", 1137 "renesas,rcar-gen3-sdhi"; 1138 reg = <0 0xee140000 0 0x2000>; 1139 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&cpg CPG_MOD 314>; 1141 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1142 resets = <&cpg 314>; 1143 max-frequency = <200000000>; 1144 status = "disabled"; 1145 }; 1146 1147 gic: interrupt-controller@f1010000 { 1148 compatible = "arm,gic-400"; 1149 #interrupt-cells = <3>; 1150 #address-cells = <0>; 1151 interrupt-controller; 1152 reg = <0x0 0xf1010000 0 0x1000>, 1153 <0x0 0xf1020000 0 0x20000>, 1154 <0x0 0xf1040000 0 0x20000>, 1155 <0x0 0xf1060000 0 0x20000>; 1156 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 1157 IRQ_TYPE_LEVEL_HIGH)>; 1158 clocks = <&cpg CPG_MOD 408>; 1159 clock-names = "clk"; 1160 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1161 resets = <&cpg 408>; 1162 }; 1163 1164 pciec: pcie@fe000000 { 1165 compatible = "renesas,pcie-r8a77980", 1166 "renesas,pcie-rcar-gen3"; 1167 reg = <0 0xfe000000 0 0x80000>; 1168 #address-cells = <3>; 1169 #size-cells = <2>; 1170 bus-range = <0x00 0xff>; 1171 device_type = "pci"; 1172 ranges = < 1173 0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000 1174 0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000 1175 0x02000000 0 0x30000000 0 0x30000000 0 0x8000000 1176 0x42000000 0 0x38000000 0 0x38000000 0 0x8000000 1177 >; 1178 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1179 0 0x80000000>; 1180 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1183 #interrupt-cells = <1>; 1184 interrupt-map-mask = <0 0 0 0>; 1185 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 1186 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1188 clock-names = "pcie", "pcie_bus"; 1189 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1190 resets = <&cpg 319>; 1191 phys = <&pcie_phy>; 1192 phy-names = "pcie"; 1193 status = "disabled"; 1194 }; 1195 1196 vspd0: vsp@fea20000 { 1197 compatible = "renesas,vsp2"; 1198 reg = <0 0xfea20000 0 0x5000>; 1199 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&cpg CPG_MOD 623>; 1201 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1202 resets = <&cpg 623>; 1203 renesas,fcp = <&fcpvd0>; 1204 }; 1205 1206 fcpvd0: fcp@fea27000 { 1207 compatible = "renesas,fcpv"; 1208 reg = <0 0xfea27000 0 0x200>; 1209 clocks = <&cpg CPG_MOD 603>; 1210 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1211 resets = <&cpg 603>; 1212 }; 1213 1214 csi40: csi2@feaa0000 { 1215 compatible = "renesas,r8a77980-csi2"; 1216 reg = <0 0xfeaa0000 0 0x10000>; 1217 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&cpg CPG_MOD 716>; 1219 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1220 resets = <&cpg 716>; 1221 status = "disabled"; 1222 1223 ports { 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 1227 port@1 { 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 1231 reg = <1>; 1232 1233 csi40vin0: endpoint@0 { 1234 reg = <0>; 1235 remote-endpoint = <&vin0csi40>; 1236 }; 1237 csi40vin1: endpoint@1 { 1238 reg = <1>; 1239 remote-endpoint = <&vin1csi40>; 1240 }; 1241 csi40vin2: endpoint@2 { 1242 reg = <2>; 1243 remote-endpoint = <&vin2csi40>; 1244 }; 1245 csi40vin3: endpoint@3 { 1246 reg = <3>; 1247 remote-endpoint = <&vin3csi40>; 1248 }; 1249 }; 1250 }; 1251 }; 1252 1253 csi41: csi2@feab0000 { 1254 compatible = "renesas,r8a77980-csi2"; 1255 reg = <0 0xfeab0000 0 0x10000>; 1256 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cpg CPG_MOD 715>; 1258 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1259 resets = <&cpg 715>; 1260 status = "disabled"; 1261 1262 ports { 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 1266 port@1 { 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 1270 reg = <1>; 1271 1272 csi41vin4: endpoint@0 { 1273 reg = <0>; 1274 remote-endpoint = <&vin4csi41>; 1275 }; 1276 csi41vin5: endpoint@1 { 1277 reg = <1>; 1278 remote-endpoint = <&vin5csi41>; 1279 }; 1280 csi41vin6: endpoint@2 { 1281 reg = <2>; 1282 remote-endpoint = <&vin6csi41>; 1283 }; 1284 csi41vin7: endpoint@3 { 1285 reg = <3>; 1286 remote-endpoint = <&vin7csi41>; 1287 }; 1288 }; 1289 }; 1290 }; 1291 1292 du: display@feb00000 { 1293 compatible = "renesas,du-r8a77980", 1294 "renesas,du-r8a77970"; 1295 reg = <0 0xfeb00000 0 0x80000>; 1296 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1297 clocks = <&cpg CPG_MOD 724>; 1298 clock-names = "du.0"; 1299 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1300 resets = <&cpg 724>; 1301 vsps = <&vspd0>; 1302 status = "disabled"; 1303 1304 ports { 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 1308 port@0 { 1309 reg = <0>; 1310 du_out_rgb: endpoint { 1311 }; 1312 }; 1313 1314 port@1 { 1315 reg = <1>; 1316 du_out_lvds0: endpoint { 1317 remote-endpoint = <&lvds0_in>; 1318 }; 1319 }; 1320 }; 1321 }; 1322 1323 lvds0: lvds-encoder@feb90000 { 1324 compatible = "renesas,r8a77980-lvds"; 1325 reg = <0 0xfeb90000 0 0x14>; 1326 clocks = <&cpg CPG_MOD 727>; 1327 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1328 resets = <&cpg 727>; 1329 status = "disabled"; 1330 1331 ports { 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 1335 port@0 { 1336 reg = <0>; 1337 lvds0_in: endpoint { 1338 remote-endpoint = 1339 <&du_out_lvds0>; 1340 }; 1341 }; 1342 1343 port@1 { 1344 reg = <1>; 1345 lvds0_out: endpoint { 1346 }; 1347 }; 1348 }; 1349 }; 1350 1351 prr: chipid@fff00044 { 1352 compatible = "renesas,prr"; 1353 reg = <0 0xfff00044 0 4>; 1354 }; 1355 }; 1356 1357 timer { 1358 compatible = "arm,armv8-timer"; 1359 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 1360 IRQ_TYPE_LEVEL_LOW)>, 1361 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 1362 IRQ_TYPE_LEVEL_LOW)>, 1363 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 1364 IRQ_TYPE_LEVEL_LOW)>, 1365 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 1366 IRQ_TYPE_LEVEL_LOW)>; 1367 }; 1368}; 1369