1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13/ { 14 compatible = "renesas,r8a77980"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 a53_0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53", "arm,armv8"; 25 reg = <0>; 26 clocks = <&cpg CPG_CORE 0>; 27 power-domains = <&sysc 5>; 28 next-level-cache = <&L2_CA53>; 29 enable-method = "psci"; 30 }; 31 32 L2_CA53: cache-controller { 33 compatible = "cache"; 34 power-domains = <&sysc 21>; 35 cache-unified; 36 cache-level = <2>; 37 }; 38 }; 39 40 extal_clk: extal { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 /* This value must be overridden by the board */ 44 clock-frequency = <0>; 45 }; 46 47 extalr_clk: extalr { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 /* This value must be overridden by the board */ 51 clock-frequency = <0>; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0", "arm,psci-0.2"; 56 method = "smc"; 57 }; 58 59 soc { 60 compatible = "simple-bus"; 61 interrupt-parent = <&gic>; 62 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 67 cpg: clock-controller@e6150000 { 68 compatible = "renesas,r8a77980-cpg-mssr"; 69 reg = <0 0xe6150000 0 0x1000>; 70 clocks = <&extal_clk>, <&extalr_clk>; 71 clock-names = "extal", "extalr"; 72 #clock-cells = <2>; 73 #power-domain-cells = <0>; 74 #reset-cells = <1>; 75 }; 76 77 rst: reset-controller@e6160000 { 78 compatible = "renesas,r8a77980-rst"; 79 reg = <0 0xe6160000 0 0x200>; 80 }; 81 82 sysc: system-controller@e6180000 { 83 compatible = "renesas,r8a77980-sysc"; 84 reg = <0 0xe6180000 0 0x440>; 85 #power-domain-cells = <1>; 86 }; 87 88 dmac1: dma-controller@e7300000 { 89 compatible = "renesas,dmac-r8a77980", 90 "renesas,rcar-dmac"; 91 reg = <0 0xe7300000 0 0x10000>; 92 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 93 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 94 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 95 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 96 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 97 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 98 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 99 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 100 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 101 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 102 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 103 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 104 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 105 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 106 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 107 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 108 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 109 interrupt-names = "error", 110 "ch0", "ch1", "ch2", "ch3", 111 "ch4", "ch5", "ch6", "ch7", 112 "ch8", "ch9", "ch10", "ch11", 113 "ch12", "ch13", "ch14", "ch15"; 114 clocks = <&cpg CPG_MOD 218>; 115 clock-names = "fck"; 116 power-domains = <&sysc 32>; 117 resets = <&cpg 218>; 118 #dma-cells = <1>; 119 dma-channels = <16>; 120 }; 121 122 dmac2: dma-controller@e7310000 { 123 compatible = "renesas,dmac-r8a77980", 124 "renesas,rcar-dmac"; 125 reg = <0 0xe7310000 0 0x10000>; 126 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 127 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 128 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 129 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 130 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 131 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 132 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 133 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 134 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 135 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 136 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 137 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 138 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 139 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 140 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 141 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 142 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 143 interrupt-names = "error", 144 "ch0", "ch1", "ch2", "ch3", 145 "ch4", "ch5", "ch6", "ch7", 146 "ch8", "ch9", "ch10", "ch11", 147 "ch12", "ch13", "ch14", "ch15"; 148 clocks = <&cpg CPG_MOD 217>; 149 clock-names = "fck"; 150 power-domains = <&sysc 32>; 151 resets = <&cpg 217>; 152 #dma-cells = <1>; 153 dma-channels = <16>; 154 }; 155 156 gic: interrupt-controller@f1010000 { 157 compatible = "arm,gic-400"; 158 #interrupt-cells = <3>; 159 #address-cells = <0>; 160 interrupt-controller; 161 reg = <0x0 0xf1010000 0 0x1000>, 162 <0x0 0xf1020000 0 0x20000>, 163 <0x0 0xf1040000 0 0x20000>, 164 <0x0 0xf1060000 0 0x20000>; 165 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 166 IRQ_TYPE_LEVEL_HIGH)>; 167 clocks = <&cpg CPG_MOD 408>; 168 clock-names = "clk"; 169 power-domains = <&sysc 32>; 170 resets = <&cpg 408>; 171 }; 172 173 prr: chipid@fff00044 { 174 compatible = "renesas,prr"; 175 reg = <0 0xfff00044 0 4>; 176 }; 177 }; 178 179 timer { 180 compatible = "arm,armv8-timer"; 181 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 182 IRQ_TYPE_LEVEL_LOW)>, 183 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 184 IRQ_TYPE_LEVEL_LOW)>, 185 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 186 IRQ_TYPE_LEVEL_LOW)>, 187 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 188 IRQ_TYPE_LEVEL_LOW)>; 189 }; 190}; 191