1cba59c25SWolfram Sang// SPDX-License-Identifier: GPL-2.0 21a48290eSSergei Shtylyov/* 3cfd7bf66SGeert Uytterhoeven * Device Tree Source for the Eagle board with R-Car V3M 41a48290eSSergei Shtylyov * 51a48290eSSergei Shtylyov * Copyright (C) 2016-2017 Renesas Electronics Corp. 61a48290eSSergei Shtylyov * Copyright (C) 2017 Cogent Embedded, Inc. 71a48290eSSergei Shtylyov */ 81a48290eSSergei Shtylyov 91a48290eSSergei Shtylyov/dts-v1/; 101a48290eSSergei Shtylyov#include "r8a77970.dtsi" 11*732e8ee0SGeert Uytterhoeven#include <dt-bindings/gpio/gpio.h> 121a48290eSSergei Shtylyov 131a48290eSSergei Shtylyov/ { 141a48290eSSergei Shtylyov model = "Renesas Eagle board based on r8a77970"; 151a48290eSSergei Shtylyov compatible = "renesas,eagle", "renesas,r8a77970"; 161a48290eSSergei Shtylyov 171a48290eSSergei Shtylyov aliases { 181a48290eSSergei Shtylyov serial0 = &scif0; 1938525608SSergei Shtylyov ethernet0 = &avb; 201a48290eSSergei Shtylyov }; 211a48290eSSergei Shtylyov 221a48290eSSergei Shtylyov chosen { 23b31b43c9SMagnus Damm bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 241a48290eSSergei Shtylyov stdout-path = "serial0:115200n8"; 251a48290eSSergei Shtylyov }; 261a48290eSSergei Shtylyov 2783c5cf19SYoshihiro Kaneko d3p3: regulator-fixed { 2883c5cf19SYoshihiro Kaneko compatible = "regulator-fixed"; 2983c5cf19SYoshihiro Kaneko regulator-name = "fixed-3.3V"; 3083c5cf19SYoshihiro Kaneko regulator-min-microvolt = <3300000>; 3183c5cf19SYoshihiro Kaneko regulator-max-microvolt = <3300000>; 3283c5cf19SYoshihiro Kaneko regulator-boot-on; 3383c5cf19SYoshihiro Kaneko regulator-always-on; 341a48290eSSergei Shtylyov }; 353c3d1672SJacopo Mondi 363c3d1672SJacopo Mondi hdmi-out { 373c3d1672SJacopo Mondi compatible = "hdmi-connector"; 383c3d1672SJacopo Mondi type = "a"; 393c3d1672SJacopo Mondi 403c3d1672SJacopo Mondi port { 413c3d1672SJacopo Mondi hdmi_con_out: endpoint { 423c3d1672SJacopo Mondi remote-endpoint = <&adv7511_out>; 433c3d1672SJacopo Mondi }; 443c3d1672SJacopo Mondi }; 453c3d1672SJacopo Mondi }; 463c3d1672SJacopo Mondi 473c3d1672SJacopo Mondi lvds-decoder { 483c3d1672SJacopo Mondi compatible = "thine,thc63lvd1024"; 493c3d1672SJacopo Mondi 503c3d1672SJacopo Mondi vcc-supply = <&d3p3>; 513c3d1672SJacopo Mondi 523c3d1672SJacopo Mondi ports { 533c3d1672SJacopo Mondi #address-cells = <1>; 543c3d1672SJacopo Mondi #size-cells = <0>; 553c3d1672SJacopo Mondi 563c3d1672SJacopo Mondi port@0 { 573c3d1672SJacopo Mondi reg = <0>; 583c3d1672SJacopo Mondi thc63lvd1024_in: endpoint { 593c3d1672SJacopo Mondi remote-endpoint = <&lvds0_out>; 603c3d1672SJacopo Mondi }; 613c3d1672SJacopo Mondi }; 623c3d1672SJacopo Mondi 633c3d1672SJacopo Mondi port@2 { 643c3d1672SJacopo Mondi reg = <2>; 653c3d1672SJacopo Mondi thc63lvd1024_out: endpoint { 663c3d1672SJacopo Mondi remote-endpoint = <&adv7511_in>; 673c3d1672SJacopo Mondi }; 683c3d1672SJacopo Mondi }; 693c3d1672SJacopo Mondi }; 703c3d1672SJacopo Mondi }; 7183c5cf19SYoshihiro Kaneko 7283c5cf19SYoshihiro Kaneko memory@48000000 { 7383c5cf19SYoshihiro Kaneko device_type = "memory"; 7483c5cf19SYoshihiro Kaneko /* first 128MB is reserved for secure area. */ 7583c5cf19SYoshihiro Kaneko reg = <0x0 0x48000000 0x0 0x38000000>; 7683c5cf19SYoshihiro Kaneko }; 77e9550a53SValentine Barshak 78e9550a53SValentine Barshak x1_clk: x1-clock { 79e9550a53SValentine Barshak compatible = "fixed-clock"; 80e9550a53SValentine Barshak #clock-cells = <0>; 81e9550a53SValentine Barshak clock-frequency = <148500000>; 82e9550a53SValentine Barshak }; 831a48290eSSergei Shtylyov}; 841a48290eSSergei Shtylyov 85d0ff035fSGeert Uytterhoeven&avb { 861119cffeSSergei Shtylyov pinctrl-0 = <&avb_pins>; 871119cffeSSergei Shtylyov pinctrl-names = "default"; 881119cffeSSergei Shtylyov 89d0ff035fSGeert Uytterhoeven renesas,no-ether-link; 90d0ff035fSGeert Uytterhoeven phy-handle = <&phy0>; 919b810181SGeert Uytterhoeven rx-internal-delay-ps = <1800>; 929b810181SGeert Uytterhoeven tx-internal-delay-ps = <2000>; 93d0ff035fSGeert Uytterhoeven status = "okay"; 94d0ff035fSGeert Uytterhoeven 95d0ff035fSGeert Uytterhoeven phy0: ethernet-phy@0 { 96722d55f3SGeert Uytterhoeven compatible = "ethernet-phy-id0022.1622", 97722d55f3SGeert Uytterhoeven "ethernet-phy-ieee802.3-c22"; 98d0ff035fSGeert Uytterhoeven rxc-skew-ps = <1500>; 99d0ff035fSGeert Uytterhoeven reg = <0>; 10051671b26SSergei Shtylyov interrupt-parent = <&gpio1>; 10151671b26SSergei Shtylyov interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 102*732e8ee0SGeert Uytterhoeven reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 103d0ff035fSGeert Uytterhoeven }; 104d0ff035fSGeert Uytterhoeven}; 105d0ff035fSGeert Uytterhoeven 106bb8d2033SSergei Shtylyov&canfd { 107bb8d2033SSergei Shtylyov pinctrl-0 = <&canfd0_pins>; 108bb8d2033SSergei Shtylyov pinctrl-names = "default"; 109bb8d2033SSergei Shtylyov status = "okay"; 110bb8d2033SSergei Shtylyov 111bb8d2033SSergei Shtylyov channel0 { 112bb8d2033SSergei Shtylyov status = "okay"; 113bb8d2033SSergei Shtylyov }; 114bb8d2033SSergei Shtylyov}; 115bb8d2033SSergei Shtylyov 11683c5cf19SYoshihiro Kaneko&du { 117e9550a53SValentine Barshak clocks = <&cpg CPG_MOD 724>, <&x1_clk>; 118e9550a53SValentine Barshak clock-names = "du.0", "dclkin.0"; 11983c5cf19SYoshihiro Kaneko status = "okay"; 12083c5cf19SYoshihiro Kaneko}; 12183c5cf19SYoshihiro Kaneko 1221a48290eSSergei Shtylyov&extal_clk { 1231a48290eSSergei Shtylyov clock-frequency = <16666666>; 1241a48290eSSergei Shtylyov}; 1251a48290eSSergei Shtylyov 1261a48290eSSergei Shtylyov&extalr_clk { 1271a48290eSSergei Shtylyov clock-frequency = <32768>; 1281a48290eSSergei Shtylyov}; 1291a48290eSSergei Shtylyov 1307859eb31SSergei Shtylyov&i2c0 { 1317859eb31SSergei Shtylyov pinctrl-0 = <&i2c0_pins>; 1327859eb31SSergei Shtylyov pinctrl-names = "default"; 1337859eb31SSergei Shtylyov 1347859eb31SSergei Shtylyov status = "okay"; 1357859eb31SSergei Shtylyov clock-frequency = <400000>; 1367859eb31SSergei Shtylyov 1377859eb31SSergei Shtylyov io_expander: gpio@20 { 1387859eb31SSergei Shtylyov compatible = "onnn,pca9654"; 1397859eb31SSergei Shtylyov reg = <0x20>; 1407859eb31SSergei Shtylyov gpio-controller; 1417859eb31SSergei Shtylyov #gpio-cells = <2>; 1427859eb31SSergei Shtylyov }; 1433c3d1672SJacopo Mondi 1443c3d1672SJacopo Mondi hdmi@39 { 1453c3d1672SJacopo Mondi compatible = "adi,adv7511w"; 1463c3d1672SJacopo Mondi reg = <0x39>; 1473c3d1672SJacopo Mondi interrupt-parent = <&gpio1>; 1483c3d1672SJacopo Mondi interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 1493c3d1672SJacopo Mondi 1503c3d1672SJacopo Mondi adi,input-depth = <8>; 1513c3d1672SJacopo Mondi adi,input-colorspace = "rgb"; 1523c3d1672SJacopo Mondi adi,input-clock = "1x"; 1533c3d1672SJacopo Mondi 1543c3d1672SJacopo Mondi ports { 1553c3d1672SJacopo Mondi #address-cells = <1>; 1563c3d1672SJacopo Mondi #size-cells = <0>; 1573c3d1672SJacopo Mondi 1583c3d1672SJacopo Mondi port@0 { 1593c3d1672SJacopo Mondi reg = <0>; 1603c3d1672SJacopo Mondi adv7511_in: endpoint { 1613c3d1672SJacopo Mondi remote-endpoint = <&thc63lvd1024_out>; 1623c3d1672SJacopo Mondi }; 1633c3d1672SJacopo Mondi }; 1643c3d1672SJacopo Mondi 1653c3d1672SJacopo Mondi port@1 { 1663c3d1672SJacopo Mondi reg = <1>; 1673c3d1672SJacopo Mondi adv7511_out: endpoint { 1683c3d1672SJacopo Mondi remote-endpoint = <&hdmi_con_out>; 1693c3d1672SJacopo Mondi }; 1703c3d1672SJacopo Mondi }; 1713c3d1672SJacopo Mondi }; 1723c3d1672SJacopo Mondi }; 1737859eb31SSergei Shtylyov}; 1747859eb31SSergei Shtylyov 17583c5cf19SYoshihiro Kaneko&lvds0 { 17683c5cf19SYoshihiro Kaneko status = "okay"; 17783c5cf19SYoshihiro Kaneko 17883c5cf19SYoshihiro Kaneko ports { 17983c5cf19SYoshihiro Kaneko port@1 { 18083c5cf19SYoshihiro Kaneko lvds0_out: endpoint { 18183c5cf19SYoshihiro Kaneko remote-endpoint = <&thc63lvd1024_in>; 18283c5cf19SYoshihiro Kaneko }; 18383c5cf19SYoshihiro Kaneko }; 18483c5cf19SYoshihiro Kaneko }; 18583c5cf19SYoshihiro Kaneko}; 18683c5cf19SYoshihiro Kaneko 18731bded67SSergei Shtylyov&pfc { 1881119cffeSSergei Shtylyov avb_pins: avb0 { 1891119cffeSSergei Shtylyov groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; 1901119cffeSSergei Shtylyov function = "avb0"; 1911119cffeSSergei Shtylyov }; 1921119cffeSSergei Shtylyov 193bb8d2033SSergei Shtylyov canfd0_pins: canfd0 { 194bb8d2033SSergei Shtylyov groups = "canfd0_data_a"; 195bb8d2033SSergei Shtylyov function = "canfd0"; 196bb8d2033SSergei Shtylyov }; 197bb8d2033SSergei Shtylyov 1987859eb31SSergei Shtylyov i2c0_pins: i2c0 { 1997859eb31SSergei Shtylyov groups = "i2c0"; 2007859eb31SSergei Shtylyov function = "i2c0"; 2017859eb31SSergei Shtylyov }; 2027859eb31SSergei Shtylyov 203daa36ae0SSergei Shtylyov qspi0_pins: qspi0 { 204daa36ae0SSergei Shtylyov groups = "qspi0_ctrl", "qspi0_data4"; 205daa36ae0SSergei Shtylyov function = "qspi0"; 206daa36ae0SSergei Shtylyov }; 207daa36ae0SSergei Shtylyov 20831bded67SSergei Shtylyov scif0_pins: scif0 { 20931bded67SSergei Shtylyov groups = "scif0_data"; 21031bded67SSergei Shtylyov function = "scif0"; 21131bded67SSergei Shtylyov }; 21231bded67SSergei Shtylyov}; 21331bded67SSergei Shtylyov 214daa36ae0SSergei Shtylyov&rpc { 215daa36ae0SSergei Shtylyov pinctrl-0 = <&qspi0_pins>; 216daa36ae0SSergei Shtylyov pinctrl-names = "default"; 217daa36ae0SSergei Shtylyov 218daa36ae0SSergei Shtylyov status = "okay"; 219daa36ae0SSergei Shtylyov 220daa36ae0SSergei Shtylyov flash@0 { 221daa36ae0SSergei Shtylyov compatible = "spansion,s25fs512s", "jedec,spi-nor"; 222daa36ae0SSergei Shtylyov reg = <0>; 223daa36ae0SSergei Shtylyov spi-max-frequency = <50000000>; 224daa36ae0SSergei Shtylyov spi-rx-bus-width = <4>; 225daa36ae0SSergei Shtylyov 226daa36ae0SSergei Shtylyov partitions { 227daa36ae0SSergei Shtylyov compatible = "fixed-partitions"; 228daa36ae0SSergei Shtylyov #address-cells = <1>; 229daa36ae0SSergei Shtylyov #size-cells = <1>; 230daa36ae0SSergei Shtylyov 231daa36ae0SSergei Shtylyov bootparam@0 { 232daa36ae0SSergei Shtylyov reg = <0x00000000 0x040000>; 233daa36ae0SSergei Shtylyov read-only; 234daa36ae0SSergei Shtylyov }; 235daa36ae0SSergei Shtylyov cr7@40000 { 236daa36ae0SSergei Shtylyov reg = <0x00040000 0x080000>; 237daa36ae0SSergei Shtylyov read-only; 238daa36ae0SSergei Shtylyov }; 239daa36ae0SSergei Shtylyov cert_header_sa3@c0000 { 240daa36ae0SSergei Shtylyov reg = <0x000c0000 0x080000>; 241daa36ae0SSergei Shtylyov read-only; 242daa36ae0SSergei Shtylyov }; 243daa36ae0SSergei Shtylyov bl2@140000 { 244daa36ae0SSergei Shtylyov reg = <0x00140000 0x040000>; 245daa36ae0SSergei Shtylyov read-only; 246daa36ae0SSergei Shtylyov }; 247daa36ae0SSergei Shtylyov cert_header_sa6@180000 { 248daa36ae0SSergei Shtylyov reg = <0x00180000 0x040000>; 249daa36ae0SSergei Shtylyov read-only; 250daa36ae0SSergei Shtylyov }; 251daa36ae0SSergei Shtylyov bl31@1c0000 { 252daa36ae0SSergei Shtylyov reg = <0x001c0000 0x460000>; 253daa36ae0SSergei Shtylyov read-only; 254daa36ae0SSergei Shtylyov }; 255daa36ae0SSergei Shtylyov uboot@640000 { 256daa36ae0SSergei Shtylyov reg = <0x00640000 0x0c0000>; 257daa36ae0SSergei Shtylyov read-only; 258daa36ae0SSergei Shtylyov }; 259daa36ae0SSergei Shtylyov uboot-env@700000 { 260daa36ae0SSergei Shtylyov reg = <0x00700000 0x040000>; 261daa36ae0SSergei Shtylyov read-only; 262daa36ae0SSergei Shtylyov }; 263daa36ae0SSergei Shtylyov dtb@740000 { 264daa36ae0SSergei Shtylyov reg = <0x00740000 0x080000>; 265daa36ae0SSergei Shtylyov }; 266daa36ae0SSergei Shtylyov kernel@7c0000 { 267daa36ae0SSergei Shtylyov reg = <0x007c0000 0x1400000>; 268daa36ae0SSergei Shtylyov }; 269daa36ae0SSergei Shtylyov user@1bc0000 { 270daa36ae0SSergei Shtylyov reg = <0x01bc0000 0x2440000>; 271daa36ae0SSergei Shtylyov }; 272daa36ae0SSergei Shtylyov }; 273daa36ae0SSergei Shtylyov }; 274daa36ae0SSergei Shtylyov}; 275daa36ae0SSergei Shtylyov 276fd363f54SGeert Uytterhoeven&rwdt { 277fd363f54SGeert Uytterhoeven timeout-sec = <60>; 278fd363f54SGeert Uytterhoeven status = "okay"; 279fd363f54SGeert Uytterhoeven}; 280fd363f54SGeert Uytterhoeven 2811a48290eSSergei Shtylyov&scif0 { 28231bded67SSergei Shtylyov pinctrl-0 = <&scif0_pins>; 28331bded67SSergei Shtylyov pinctrl-names = "default"; 28431bded67SSergei Shtylyov 2851a48290eSSergei Shtylyov status = "okay"; 2861a48290eSSergei Shtylyov}; 287