1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77965 SoC 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Based on r8a7796.dtsi 8 * Copyright (C) 2016 Renesas Electronics Corp. 9 */ 10 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14#define CPG_AUDIO_CLK_I 10 15 16/ { 17 compatible = "renesas,r8a77965"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a57_0: cpu@0 { 31 compatible = "arm,cortex-a57", "arm,armv8"; 32 reg = <0x0>; 33 device_type = "cpu"; 34 power-domains = <&sysc 0>; 35 next-level-cache = <&L2_CA57>; 36 enable-method = "psci"; 37 }; 38 39 a57_1: cpu@1 { 40 compatible = "arm,cortex-a57","arm,armv8"; 41 reg = <0x1>; 42 device_type = "cpu"; 43 power-domains = <&sysc 1>; 44 next-level-cache = <&L2_CA57>; 45 enable-method = "psci"; 46 }; 47 48 L2_CA57: cache-controller-0 { 49 compatible = "cache"; 50 power-domains = <&sysc 12>; 51 cache-unified; 52 cache-level = <2>; 53 }; 54 }; 55 56 extal_clk: extal { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 /* This value must be overridden by the board */ 60 clock-frequency = <0>; 61 }; 62 63 extalr_clk: extalr { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 /* This value must be overridden by the board */ 67 clock-frequency = <0>; 68 }; 69 70 /* 71 * The external audio clocks are configured as 0 Hz fixed frequency 72 * clocks by default. 73 * Boards that provide audio clocks should override them. 74 */ 75 audio_clk_a: audio_clk_a { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <0>; 79 }; 80 81 audio_clk_b: audio_clk_b { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 audio_clk_c: audio_clk_c { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <0>; 91 }; 92 93 /* External CAN clock - to be overridden by boards that provide it */ 94 can_clk: can { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 98 }; 99 100 /* External SCIF clock - to be overridden by boards that provide it */ 101 scif_clk: scif { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <0>; 105 }; 106 107 /* External PCIe clock - can be overridden by the board */ 108 pcie_bus_clk: pcie_bus { 109 compatible = "fixed-clock"; 110 #clock-cells = <0>; 111 clock-frequency = <0>; 112 }; 113 114 /* External USB clocks - can be overridden by the board */ 115 usb3s0_clk: usb3s0 { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 clock-frequency = <0>; 119 }; 120 121 usb_extal_clk: usb_extal { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 }; 126 127 timer { 128 compatible = "arm,armv8-timer"; 129 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 130 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 131 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 132 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 133 }; 134 135 pmu_a57 { 136 compatible = "arm,cortex-a57-pmu"; 137 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 138 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 139 interrupt-affinity = <&a57_0>, 140 <&a57_1>; 141 }; 142 143 soc { 144 compatible = "simple-bus"; 145 interrupt-parent = <&gic>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges; 149 150 gic: interrupt-controller@f1010000 { 151 compatible = "arm,gic-400"; 152 #interrupt-cells = <3>; 153 #address-cells = <0>; 154 interrupt-controller; 155 reg = <0x0 0xf1010000 0 0x1000>, 156 <0x0 0xf1020000 0 0x20000>, 157 <0x0 0xf1040000 0 0x20000>, 158 <0x0 0xf1060000 0 0x20000>; 159 interrupts = <GIC_PPI 9 160 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 161 clocks = <&cpg CPG_MOD 408>; 162 clock-names = "clk"; 163 power-domains = <&sysc 32>; 164 resets = <&cpg 408>; 165 }; 166 167 pfc: pin-controller@e6060000 { 168 compatible = "renesas,pfc-r8a77965"; 169 reg = <0 0xe6060000 0 0x50c>; 170 }; 171 172 cpg: clock-controller@e6150000 { 173 compatible = "renesas,r8a77965-cpg-mssr"; 174 reg = <0 0xe6150000 0 0x1000>; 175 clocks = <&extal_clk>, <&extalr_clk>; 176 clock-names = "extal", "extalr"; 177 #clock-cells = <2>; 178 #power-domain-cells = <0>; 179 #reset-cells = <1>; 180 }; 181 182 rst: reset-controller@e6160000 { 183 compatible = "renesas,r8a77965-rst"; 184 reg = <0 0xe6160000 0 0x0200>; 185 }; 186 187 prr: chipid@fff00044 { 188 compatible = "renesas,prr"; 189 reg = <0 0xfff00044 0 4>; 190 }; 191 192 sysc: system-controller@e6180000 { 193 compatible = "renesas,r8a77965-sysc"; 194 reg = <0 0xe6180000 0 0x0400>; 195 #power-domain-cells = <1>; 196 }; 197 198 gpio0: gpio@e6050000 { 199 compatible = "renesas,gpio-r8a77965", 200 "renesas,rcar-gen3-gpio"; 201 reg = <0 0xe6050000 0 0x50>; 202 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 203 #gpio-cells = <2>; 204 gpio-controller; 205 gpio-ranges = <&pfc 0 0 16>; 206 #interrupt-cells = <2>; 207 interrupt-controller; 208 clocks = <&cpg CPG_MOD 912>; 209 power-domains = <&sysc 32>; 210 resets = <&cpg 912>; 211 }; 212 213 gpio1: gpio@e6051000 { 214 compatible = "renesas,gpio-r8a77965", 215 "renesas,rcar-gen3-gpio"; 216 reg = <0 0xe6051000 0 0x50>; 217 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 218 #gpio-cells = <2>; 219 gpio-controller; 220 gpio-ranges = <&pfc 0 32 29>; 221 #interrupt-cells = <2>; 222 interrupt-controller; 223 clocks = <&cpg CPG_MOD 911>; 224 power-domains = <&sysc 32>; 225 resets = <&cpg 911>; 226 }; 227 228 gpio2: gpio@e6052000 { 229 compatible = "renesas,gpio-r8a77965", 230 "renesas,rcar-gen3-gpio"; 231 reg = <0 0xe6052000 0 0x50>; 232 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 233 #gpio-cells = <2>; 234 gpio-controller; 235 gpio-ranges = <&pfc 0 64 15>; 236 #interrupt-cells = <2>; 237 interrupt-controller; 238 clocks = <&cpg CPG_MOD 910>; 239 power-domains = <&sysc 32>; 240 resets = <&cpg 910>; 241 }; 242 243 gpio3: gpio@e6053000 { 244 compatible = "renesas,gpio-r8a77965", 245 "renesas,rcar-gen3-gpio"; 246 reg = <0 0xe6053000 0 0x50>; 247 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 248 #gpio-cells = <2>; 249 gpio-controller; 250 gpio-ranges = <&pfc 0 96 16>; 251 #interrupt-cells = <2>; 252 interrupt-controller; 253 clocks = <&cpg CPG_MOD 909>; 254 power-domains = <&sysc 32>; 255 resets = <&cpg 909>; 256 }; 257 258 gpio4: gpio@e6054000 { 259 compatible = "renesas,gpio-r8a77965", 260 "renesas,rcar-gen3-gpio"; 261 reg = <0 0xe6054000 0 0x50>; 262 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 263 #gpio-cells = <2>; 264 gpio-controller; 265 gpio-ranges = <&pfc 0 128 18>; 266 #interrupt-cells = <2>; 267 interrupt-controller; 268 clocks = <&cpg CPG_MOD 908>; 269 power-domains = <&sysc 32>; 270 resets = <&cpg 908>; 271 }; 272 273 gpio5: gpio@e6055000 { 274 compatible = "renesas,gpio-r8a77965", 275 "renesas,rcar-gen3-gpio"; 276 reg = <0 0xe6055000 0 0x50>; 277 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 278 #gpio-cells = <2>; 279 gpio-controller; 280 gpio-ranges = <&pfc 0 160 26>; 281 #interrupt-cells = <2>; 282 interrupt-controller; 283 clocks = <&cpg CPG_MOD 907>; 284 power-domains = <&sysc 32>; 285 resets = <&cpg 907>; 286 }; 287 288 gpio6: gpio@e6055400 { 289 compatible = "renesas,gpio-r8a77965", 290 "renesas,rcar-gen3-gpio"; 291 reg = <0 0xe6055400 0 0x50>; 292 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 293 #gpio-cells = <2>; 294 gpio-controller; 295 gpio-ranges = <&pfc 0 192 32>; 296 #interrupt-cells = <2>; 297 interrupt-controller; 298 clocks = <&cpg CPG_MOD 906>; 299 power-domains = <&sysc 32>; 300 resets = <&cpg 906>; 301 }; 302 303 gpio7: gpio@e6055800 { 304 compatible = "renesas,gpio-r8a77965", 305 "renesas,rcar-gen3-gpio"; 306 reg = <0 0xe6055800 0 0x50>; 307 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 308 #gpio-cells = <2>; 309 gpio-controller; 310 gpio-ranges = <&pfc 0 224 4>; 311 #interrupt-cells = <2>; 312 interrupt-controller; 313 clocks = <&cpg CPG_MOD 905>; 314 power-domains = <&sysc 32>; 315 resets = <&cpg 905>; 316 }; 317 318 intc_ex: interrupt-controller@e61c0000 { 319 #interrupt-cells = <2>; 320 interrupt-controller; 321 reg = <0 0xe61c0000 0 0x200>; 322 /* placeholder */ 323 }; 324 325 dmac0: dma-controller@e6700000 { 326 compatible = "renesas,dmac-r8a77965", 327 "renesas,rcar-dmac"; 328 reg = <0 0xe6700000 0 0x10000>; 329 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 344 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 345 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 346 interrupt-names = "error", 347 "ch0", "ch1", "ch2", "ch3", 348 "ch4", "ch5", "ch6", "ch7", 349 "ch8", "ch9", "ch10", "ch11", 350 "ch12", "ch13", "ch14", "ch15"; 351 clocks = <&cpg CPG_MOD 219>; 352 clock-names = "fck"; 353 power-domains = <&sysc 32>; 354 resets = <&cpg 219>; 355 #dma-cells = <1>; 356 dma-channels = <16>; 357 }; 358 359 dmac1: dma-controller@e7300000 { 360 compatible = "renesas,dmac-r8a77965", 361 "renesas,rcar-dmac"; 362 reg = <0 0xe7300000 0 0x10000>; 363 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 376 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 377 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 378 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 379 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 380 interrupt-names = "error", 381 "ch0", "ch1", "ch2", "ch3", 382 "ch4", "ch5", "ch6", "ch7", 383 "ch8", "ch9", "ch10", "ch11", 384 "ch12", "ch13", "ch14", "ch15"; 385 clocks = <&cpg CPG_MOD 218>; 386 clock-names = "fck"; 387 power-domains = <&sysc 32>; 388 resets = <&cpg 218>; 389 #dma-cells = <1>; 390 dma-channels = <16>; 391 }; 392 393 dmac2: dma-controller@e7310000 { 394 compatible = "renesas,dmac-r8a77965", 395 "renesas,rcar-dmac"; 396 reg = <0 0xe7310000 0 0x10000>; 397 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 399 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 400 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 401 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 402 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 403 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 404 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 405 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 406 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 407 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 408 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 409 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 410 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 411 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 412 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 413 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-names = "error", 415 "ch0", "ch1", "ch2", "ch3", 416 "ch4", "ch5", "ch6", "ch7", 417 "ch8", "ch9", "ch10", "ch11", 418 "ch12", "ch13", "ch14", "ch15"; 419 clocks = <&cpg CPG_MOD 217>; 420 clock-names = "fck"; 421 power-domains = <&sysc 32>; 422 resets = <&cpg 217>; 423 #dma-cells = <1>; 424 dma-channels = <16>; 425 }; 426 427 scif0: serial@e6e60000 { 428 compatible = "renesas,scif-r8a77965", 429 "renesas,rcar-gen3-scif", "renesas,scif"; 430 reg = <0 0xe6e60000 0 64>; 431 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cpg CPG_MOD 207>, 433 <&cpg CPG_CORE 20>, 434 <&scif_clk>; 435 clock-names = "fck", "brg_int", "scif_clk"; 436 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 437 <&dmac2 0x51>, <&dmac2 0x50>; 438 dma-names = "tx", "rx", "tx", "rx"; 439 power-domains = <&sysc 32>; 440 resets = <&cpg 207>; 441 status = "disabled"; 442 }; 443 444 scif1: serial@e6e68000 { 445 compatible = "renesas,scif-r8a77965", 446 "renesas,rcar-gen3-scif", "renesas,scif"; 447 reg = <0 0xe6e68000 0 64>; 448 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cpg CPG_MOD 206>, 450 <&cpg CPG_CORE 20>, 451 <&scif_clk>; 452 clock-names = "fck", "brg_int", "scif_clk"; 453 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 454 <&dmac2 0x53>, <&dmac2 0x52>; 455 dma-names = "tx", "rx", "tx", "rx"; 456 power-domains = <&sysc 32>; 457 resets = <&cpg 206>; 458 status = "disabled"; 459 }; 460 461 scif2: serial@e6e88000 { 462 compatible = "renesas,scif-r8a77965", 463 "renesas,rcar-gen3-scif", "renesas,scif"; 464 reg = <0 0xe6e88000 0 64>; 465 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cpg CPG_MOD 310>, 467 <&cpg CPG_CORE 20>, 468 <&scif_clk>; 469 clock-names = "fck", "brg_int", "scif_clk"; 470 power-domains = <&sysc 32>; 471 resets = <&cpg 310>; 472 status = "disabled"; 473 }; 474 475 scif3: serial@e6c50000 { 476 compatible = "renesas,scif-r8a77965", 477 "renesas,rcar-gen3-scif", "renesas,scif"; 478 reg = <0 0xe6c50000 0 64>; 479 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cpg CPG_MOD 204>, 481 <&cpg CPG_CORE 20>, 482 <&scif_clk>; 483 clock-names = "fck", "brg_int", "scif_clk"; 484 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 485 dma-names = "tx", "rx"; 486 power-domains = <&sysc 32>; 487 resets = <&cpg 204>; 488 status = "disabled"; 489 }; 490 491 scif4: serial@e6c40000 { 492 compatible = "renesas,scif-r8a77965", 493 "renesas,rcar-gen3-scif", "renesas,scif"; 494 reg = <0 0xe6c40000 0 64>; 495 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&cpg CPG_MOD 203>, 497 <&cpg CPG_CORE 20>, 498 <&scif_clk>; 499 clock-names = "fck", "brg_int", "scif_clk"; 500 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 501 dma-names = "tx", "rx"; 502 power-domains = <&sysc 32>; 503 resets = <&cpg 203>; 504 status = "disabled"; 505 }; 506 507 scif5: serial@e6f30000 { 508 compatible = "renesas,scif-r8a77965", 509 "renesas,rcar-gen3-scif", "renesas,scif"; 510 reg = <0 0xe6f30000 0 64>; 511 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&cpg CPG_MOD 202>, 513 <&cpg CPG_CORE 20>, 514 <&scif_clk>; 515 clock-names = "fck", "brg_int", "scif_clk"; 516 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 517 <&dmac2 0x5b>, <&dmac2 0x5a>; 518 dma-names = "tx", "rx", "tx", "rx"; 519 power-domains = <&sysc 32>; 520 resets = <&cpg 202>; 521 status = "disabled"; 522 }; 523 524 avb: ethernet@e6800000 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 528 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 529 /* placeholder */ 530 }; 531 532 csi20: csi2@fea80000 { 533 reg = <0 0xfea80000 0 0x10000>; 534 /* placeholder */ 535 536 ports { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 }; 540 }; 541 542 csi40: csi2@feaa0000 { 543 reg = <0 0xfeaa0000 0 0x10000>; 544 /* placeholder */ 545 546 ports { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 }; 550 }; 551 552 vin0: video@e6ef0000 { 553 reg = <0 0xe6ef0000 0 0x1000>; 554 /* placeholder */ 555 }; 556 557 vin1: video@e6ef1000 { 558 reg = <0 0xe6ef1000 0 0x1000>; 559 /* placeholder */ 560 }; 561 562 vin2: video@e6ef2000 { 563 reg = <0 0xe6ef2000 0 0x1000>; 564 /* placeholder */ 565 }; 566 567 vin3: video@e6ef3000 { 568 reg = <0 0xe6ef3000 0 0x1000>; 569 /* placeholder */ 570 }; 571 572 vin4: video@e6ef4000 { 573 reg = <0 0xe6ef4000 0 0x1000>; 574 /* placeholder */ 575 }; 576 577 vin5: video@e6ef5000 { 578 reg = <0 0xe6ef5000 0 0x1000>; 579 /* placeholder */ 580 }; 581 582 vin6: video@e6ef6000 { 583 reg = <0 0xe6ef6000 0 0x1000>; 584 /* placeholder */ 585 }; 586 587 vin7: video@e6ef7000 { 588 reg = <0 0xe6ef7000 0 0x1000>; 589 /* placeholder */ 590 }; 591 592 ohci0: usb@ee080000 { 593 reg = <0 0xee080000 0 0x100>; 594 /* placeholder */ 595 }; 596 597 ehci0: usb@ee080100 { 598 reg = <0 0xee080100 0 0x100>; 599 /* placeholder */ 600 }; 601 602 usb2_phy0: usb-phy@ee080200 { 603 reg = <0 0xee080200 0 0x700>; 604 /* placeholder */ 605 }; 606 607 ohci1: usb@ee0a0000 { 608 reg = <0 0xee0a0000 0 0x100>; 609 /* placeholder */ 610 }; 611 612 ehci1: usb@ee0a0100 { 613 reg = <0 0xee0a0100 0 0x100>; 614 /* placeholder */ 615 }; 616 617 i2c0: i2c@e6500000 { 618 reg = <0 0xe6500000 0 0x40>; 619 /* placeholder */ 620 }; 621 622 i2c1: i2c@e6508000 { 623 reg = <0 0xe6508000 0 0x40>; 624 /* placeholder */ 625 }; 626 627 i2c2: i2c@e6510000 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 631 reg = <0 0xe6510000 0 0x40>; 632 /* placeholder */ 633 }; 634 635 i2c3: i2c@e66d0000 { 636 reg = <0 0xe66d0000 0 0x40>; 637 /* placeholder */ 638 }; 639 640 i2c4: i2c@e66d8000 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 644 reg = <0 0xe66d8000 0 0x40>; 645 /* placeholder */ 646 }; 647 648 i2c5: i2c@e66e0000 { 649 reg = <0 0xe66e0000 0 0x40>; 650 /* placeholder */ 651 }; 652 653 i2c6: i2c@e66e8000 { 654 reg = <0 0xe66e8000 0 0x40>; 655 /* placeholder */ 656 }; 657 658 i2c_dvfs: i2c@e60b0000 { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 662 reg = <0 0xe60b0000 0 0x425>; 663 /* placeholder */ 664 }; 665 666 pwm0: pwm@e6e30000 { 667 reg = <0 0xe6e30000 0 8>; 668 /* placeholder */ 669 }; 670 671 pwm1: pwm@e6e31000 { 672 reg = <0 0xe6e31000 0 8>; 673 #pwm-cells = <2>; 674 /* placeholder */ 675 }; 676 677 pwm2: pwm@e6e32000 { 678 reg = <0 0xe6e32000 0 8>; 679 /* placeholder */ 680 }; 681 682 pwm3: pwm@e6e33000 { 683 reg = <0 0xe6e33000 0 8>; 684 /* placeholder */ 685 }; 686 687 pwm4: pwm@e6e34000 { 688 reg = <0 0xe6e34000 0 8>; 689 /* placeholder */ 690 }; 691 692 pwm5: pwm@e6e35000 { 693 reg = <0 0xe6e35000 0 8>; 694 /* placeholder */ 695 }; 696 697 pwm6: pwm@e6e36000 { 698 reg = <0 0xe6e36000 0 8>; 699 /* placeholder */ 700 }; 701 702 du: display@feb00000 { 703 reg = <0 0xfeb00000 0 0x80000>, 704 <0 0xfeb90000 0 0x14>; 705 /* placeholder */ 706 707 ports { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 711 port@0 { 712 reg = <0>; 713 du_out_rgb: endpoint { 714 }; 715 }; 716 port@1 { 717 reg = <1>; 718 du_out_hdmi0: endpoint { 719 }; 720 }; 721 port@2 { 722 reg = <2>; 723 du_out_lvds0: endpoint { 724 }; 725 }; 726 }; 727 }; 728 729 hsusb: usb@e6590000 { 730 reg = <0 0xe6590000 0 0x100>; 731 /* placeholder */ 732 }; 733 734 pciec0: pcie@fe000000 { 735 reg = <0 0xfe000000 0 0x80000>; 736 /* placeholder */ 737 }; 738 739 pciec1: pcie@ee800000 { 740 reg = <0 0xee800000 0 0x80000>; 741 /* placeholder */ 742 }; 743 744 rcar_sound: sound@ec500000 { 745 reg = <0 0xec500000 0 0x1000>, /* SCU */ 746 <0 0xec5a0000 0 0x100>, /* ADG */ 747 <0 0xec540000 0 0x1000>, /* SSIU */ 748 <0 0xec541000 0 0x280>, /* SSI */ 749 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 750 /* placeholder */ 751 752 rcar_sound,dvc { 753 dvc0: dvc-0 { 754 }; 755 dvc1: dvc-1 { 756 }; 757 }; 758 759 rcar_sound,src { 760 src0: src-0 { 761 }; 762 src1: src-1 { 763 }; 764 }; 765 766 rcar_sound,ssi { 767 ssi0: ssi-0 { 768 }; 769 ssi1: ssi-1 { 770 }; 771 }; 772 }; 773 774 usb2_phy1: usb-phy@ee0a0200 { 775 reg = <0 0xee0a0200 0 0x700>; 776 /* placeholder */ 777 }; 778 779 sdhi0: sd@ee100000 { 780 reg = <0 0xee100000 0 0x2000>; 781 /* placeholder */ 782 }; 783 784 sdhi1: sd@ee120000 { 785 reg = <0 0xee120000 0 0x2000>; 786 /* placeholder */ 787 }; 788 789 sdhi2: sd@ee140000 { 790 reg = <0 0xee140000 0 0x2000>; 791 /* placeholder */ 792 }; 793 794 sdhi3: sd@ee160000 { 795 reg = <0 0xee160000 0 0x2000>; 796 /* placeholder */ 797 }; 798 799 usb3_phy0: usb-phy@e65ee000 { 800 reg = <0 0xe65ee000 0 0x90>; 801 #phy-cells = <0>; 802 /* placeholder */ 803 }; 804 805 usb3_peri0: usb@ee020000 { 806 reg = <0 0xee020000 0 0x400>; 807 /* placeholder */ 808 }; 809 810 xhci0: usb@ee000000 { 811 reg = <0 0xee000000 0 0xc00>; 812 /* placeholder */ 813 }; 814 815 wdt0: watchdog@e6020000 { 816 reg = <0 0xe6020000 0 0x0c>; 817 /* placeholder */ 818 }; 819 }; 820}; 821