1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77965 SoC 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Based on r8a7796.dtsi 8 * Copyright (C) 2016 Renesas Electronics Corp. 9 */ 10 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14#define CPG_AUDIO_CLK_I 10 15 16/ { 17 compatible = "renesas,r8a77965"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a57_0: cpu@0 { 31 compatible = "arm,cortex-a57", "arm,armv8"; 32 reg = <0x0>; 33 device_type = "cpu"; 34 power-domains = <&sysc 0>; 35 next-level-cache = <&L2_CA57>; 36 enable-method = "psci"; 37 }; 38 39 a57_1: cpu@1 { 40 compatible = "arm,cortex-a57","arm,armv8"; 41 reg = <0x1>; 42 device_type = "cpu"; 43 power-domains = <&sysc 1>; 44 next-level-cache = <&L2_CA57>; 45 enable-method = "psci"; 46 }; 47 48 L2_CA57: cache-controller-0 { 49 compatible = "cache"; 50 power-domains = <&sysc 12>; 51 cache-unified; 52 cache-level = <2>; 53 }; 54 }; 55 56 extal_clk: extal { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 /* This value must be overridden by the board */ 60 clock-frequency = <0>; 61 }; 62 63 extalr_clk: extalr { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 /* This value must be overridden by the board */ 67 clock-frequency = <0>; 68 }; 69 70 /* 71 * The external audio clocks are configured as 0 Hz fixed frequency 72 * clocks by default. 73 * Boards that provide audio clocks should override them. 74 */ 75 audio_clk_a: audio_clk_a { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <0>; 79 }; 80 81 audio_clk_b: audio_clk_b { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 audio_clk_c: audio_clk_c { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <0>; 91 }; 92 93 /* External CAN clock - to be overridden by boards that provide it */ 94 can_clk: can { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 98 }; 99 100 /* External SCIF clock - to be overridden by boards that provide it */ 101 scif_clk: scif { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <0>; 105 }; 106 107 /* External PCIe clock - can be overridden by the board */ 108 pcie_bus_clk: pcie_bus { 109 compatible = "fixed-clock"; 110 #clock-cells = <0>; 111 clock-frequency = <0>; 112 }; 113 114 /* External USB clocks - can be overridden by the board */ 115 usb3s0_clk: usb3s0 { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 clock-frequency = <0>; 119 }; 120 121 usb_extal_clk: usb_extal { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 }; 126 127 timer { 128 compatible = "arm,armv8-timer"; 129 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 130 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 131 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 132 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 133 }; 134 135 pmu_a57 { 136 compatible = "arm,cortex-a57-pmu"; 137 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 138 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 139 interrupt-affinity = <&a57_0>, 140 <&a57_1>; 141 }; 142 143 soc { 144 compatible = "simple-bus"; 145 interrupt-parent = <&gic>; 146 #address-cells = <2>; 147 #size-cells = <2>; 148 ranges; 149 150 gic: interrupt-controller@f1010000 { 151 compatible = "arm,gic-400"; 152 #interrupt-cells = <3>; 153 #address-cells = <0>; 154 interrupt-controller; 155 reg = <0x0 0xf1010000 0 0x1000>, 156 <0x0 0xf1020000 0 0x20000>, 157 <0x0 0xf1040000 0 0x20000>, 158 <0x0 0xf1060000 0 0x20000>; 159 interrupts = <GIC_PPI 9 160 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 161 clocks = <&cpg CPG_MOD 408>; 162 clock-names = "clk"; 163 power-domains = <&sysc 32>; 164 resets = <&cpg 408>; 165 }; 166 167 pfc: pin-controller@e6060000 { 168 compatible = "renesas,pfc-r8a77965"; 169 reg = <0 0xe6060000 0 0x50c>; 170 }; 171 172 cpg: clock-controller@e6150000 { 173 compatible = "renesas,r8a77965-cpg-mssr"; 174 reg = <0 0xe6150000 0 0x1000>; 175 clocks = <&extal_clk>, <&extalr_clk>; 176 clock-names = "extal", "extalr"; 177 #clock-cells = <2>; 178 #power-domain-cells = <0>; 179 #reset-cells = <1>; 180 }; 181 182 rst: reset-controller@e6160000 { 183 compatible = "renesas,r8a77965-rst"; 184 reg = <0 0xe6160000 0 0x0200>; 185 }; 186 187 prr: chipid@fff00044 { 188 compatible = "renesas,prr"; 189 reg = <0 0xfff00044 0 4>; 190 }; 191 192 sysc: system-controller@e6180000 { 193 compatible = "renesas,r8a77965-sysc"; 194 reg = <0 0xe6180000 0 0x0400>; 195 #power-domain-cells = <1>; 196 }; 197 198 gpio0: gpio@e6050000 { 199 compatible = "renesas,gpio-r8a77965", 200 "renesas,rcar-gen3-gpio"; 201 reg = <0 0xe6050000 0 0x50>; 202 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 203 #gpio-cells = <2>; 204 gpio-controller; 205 gpio-ranges = <&pfc 0 0 16>; 206 #interrupt-cells = <2>; 207 interrupt-controller; 208 clocks = <&cpg CPG_MOD 912>; 209 power-domains = <&sysc 32>; 210 resets = <&cpg 912>; 211 }; 212 213 gpio1: gpio@e6051000 { 214 compatible = "renesas,gpio-r8a77965", 215 "renesas,rcar-gen3-gpio"; 216 reg = <0 0xe6051000 0 0x50>; 217 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 218 #gpio-cells = <2>; 219 gpio-controller; 220 gpio-ranges = <&pfc 0 32 29>; 221 #interrupt-cells = <2>; 222 interrupt-controller; 223 clocks = <&cpg CPG_MOD 911>; 224 power-domains = <&sysc 32>; 225 resets = <&cpg 911>; 226 }; 227 228 gpio2: gpio@e6052000 { 229 compatible = "renesas,gpio-r8a77965", 230 "renesas,rcar-gen3-gpio"; 231 reg = <0 0xe6052000 0 0x50>; 232 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 233 #gpio-cells = <2>; 234 gpio-controller; 235 gpio-ranges = <&pfc 0 64 15>; 236 #interrupt-cells = <2>; 237 interrupt-controller; 238 clocks = <&cpg CPG_MOD 910>; 239 power-domains = <&sysc 32>; 240 resets = <&cpg 910>; 241 }; 242 243 gpio3: gpio@e6053000 { 244 compatible = "renesas,gpio-r8a77965", 245 "renesas,rcar-gen3-gpio"; 246 reg = <0 0xe6053000 0 0x50>; 247 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 248 #gpio-cells = <2>; 249 gpio-controller; 250 gpio-ranges = <&pfc 0 96 16>; 251 #interrupt-cells = <2>; 252 interrupt-controller; 253 clocks = <&cpg CPG_MOD 909>; 254 power-domains = <&sysc 32>; 255 resets = <&cpg 909>; 256 }; 257 258 gpio4: gpio@e6054000 { 259 compatible = "renesas,gpio-r8a77965", 260 "renesas,rcar-gen3-gpio"; 261 reg = <0 0xe6054000 0 0x50>; 262 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 263 #gpio-cells = <2>; 264 gpio-controller; 265 gpio-ranges = <&pfc 0 128 18>; 266 #interrupt-cells = <2>; 267 interrupt-controller; 268 clocks = <&cpg CPG_MOD 908>; 269 power-domains = <&sysc 32>; 270 resets = <&cpg 908>; 271 }; 272 273 gpio5: gpio@e6055000 { 274 compatible = "renesas,gpio-r8a77965", 275 "renesas,rcar-gen3-gpio"; 276 reg = <0 0xe6055000 0 0x50>; 277 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 278 #gpio-cells = <2>; 279 gpio-controller; 280 gpio-ranges = <&pfc 0 160 26>; 281 #interrupt-cells = <2>; 282 interrupt-controller; 283 clocks = <&cpg CPG_MOD 907>; 284 power-domains = <&sysc 32>; 285 resets = <&cpg 907>; 286 }; 287 288 gpio6: gpio@e6055400 { 289 compatible = "renesas,gpio-r8a77965", 290 "renesas,rcar-gen3-gpio"; 291 reg = <0 0xe6055400 0 0x50>; 292 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 293 #gpio-cells = <2>; 294 gpio-controller; 295 gpio-ranges = <&pfc 0 192 32>; 296 #interrupt-cells = <2>; 297 interrupt-controller; 298 clocks = <&cpg CPG_MOD 906>; 299 power-domains = <&sysc 32>; 300 resets = <&cpg 906>; 301 }; 302 303 gpio7: gpio@e6055800 { 304 compatible = "renesas,gpio-r8a77965", 305 "renesas,rcar-gen3-gpio"; 306 reg = <0 0xe6055800 0 0x50>; 307 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 308 #gpio-cells = <2>; 309 gpio-controller; 310 gpio-ranges = <&pfc 0 224 4>; 311 #interrupt-cells = <2>; 312 interrupt-controller; 313 clocks = <&cpg CPG_MOD 905>; 314 power-domains = <&sysc 32>; 315 resets = <&cpg 905>; 316 }; 317 318 intc_ex: interrupt-controller@e61c0000 { 319 reg = <0 0xe61c0000 0 0x200>; 320 /* placeholder */ 321 }; 322 323 dmac0: dma-controller@e6700000 { 324 compatible = "renesas,dmac-r8a77965", 325 "renesas,rcar-dmac"; 326 reg = <0 0xe6700000 0 0x10000>; 327 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "error", 345 "ch0", "ch1", "ch2", "ch3", 346 "ch4", "ch5", "ch6", "ch7", 347 "ch8", "ch9", "ch10", "ch11", 348 "ch12", "ch13", "ch14", "ch15"; 349 clocks = <&cpg CPG_MOD 219>; 350 clock-names = "fck"; 351 power-domains = <&sysc 32>; 352 resets = <&cpg 219>; 353 #dma-cells = <1>; 354 dma-channels = <16>; 355 }; 356 357 dmac1: dma-controller@e7300000 { 358 compatible = "renesas,dmac-r8a77965", 359 "renesas,rcar-dmac"; 360 reg = <0 0xe7300000 0 0x10000>; 361 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 362 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 363 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 376 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 377 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "error", 379 "ch0", "ch1", "ch2", "ch3", 380 "ch4", "ch5", "ch6", "ch7", 381 "ch8", "ch9", "ch10", "ch11", 382 "ch12", "ch13", "ch14", "ch15"; 383 clocks = <&cpg CPG_MOD 218>; 384 clock-names = "fck"; 385 power-domains = <&sysc 32>; 386 resets = <&cpg 218>; 387 #dma-cells = <1>; 388 dma-channels = <16>; 389 }; 390 391 dmac2: dma-controller@e7310000 { 392 compatible = "renesas,dmac-r8a77965", 393 "renesas,rcar-dmac"; 394 reg = <0 0xe7310000 0 0x10000>; 395 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 396 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 397 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 399 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 400 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 401 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 402 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 403 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 404 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 405 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 406 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 407 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 408 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 409 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 410 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 411 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 412 interrupt-names = "error", 413 "ch0", "ch1", "ch2", "ch3", 414 "ch4", "ch5", "ch6", "ch7", 415 "ch8", "ch9", "ch10", "ch11", 416 "ch12", "ch13", "ch14", "ch15"; 417 clocks = <&cpg CPG_MOD 217>; 418 clock-names = "fck"; 419 power-domains = <&sysc 32>; 420 resets = <&cpg 217>; 421 #dma-cells = <1>; 422 dma-channels = <16>; 423 }; 424 425 scif0: serial@e6e60000 { 426 compatible = "renesas,scif-r8a77965", 427 "renesas,rcar-gen3-scif", "renesas,scif"; 428 reg = <0 0xe6e60000 0 64>; 429 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cpg CPG_MOD 207>, 431 <&cpg CPG_CORE 20>, 432 <&scif_clk>; 433 clock-names = "fck", "brg_int", "scif_clk"; 434 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 435 <&dmac2 0x51>, <&dmac2 0x50>; 436 dma-names = "tx", "rx", "tx", "rx"; 437 power-domains = <&sysc 32>; 438 resets = <&cpg 207>; 439 status = "disabled"; 440 }; 441 442 scif1: serial@e6e68000 { 443 compatible = "renesas,scif-r8a77965", 444 "renesas,rcar-gen3-scif", "renesas,scif"; 445 reg = <0 0xe6e68000 0 64>; 446 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&cpg CPG_MOD 206>, 448 <&cpg CPG_CORE 20>, 449 <&scif_clk>; 450 clock-names = "fck", "brg_int", "scif_clk"; 451 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 452 <&dmac2 0x53>, <&dmac2 0x52>; 453 dma-names = "tx", "rx", "tx", "rx"; 454 power-domains = <&sysc 32>; 455 resets = <&cpg 206>; 456 status = "disabled"; 457 }; 458 459 scif2: serial@e6e88000 { 460 compatible = "renesas,scif-r8a77965", 461 "renesas,rcar-gen3-scif", "renesas,scif"; 462 reg = <0 0xe6e88000 0 64>; 463 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cpg CPG_MOD 310>, 465 <&cpg CPG_CORE 20>, 466 <&scif_clk>; 467 clock-names = "fck", "brg_int", "scif_clk"; 468 power-domains = <&sysc 32>; 469 resets = <&cpg 310>; 470 status = "disabled"; 471 }; 472 473 scif3: serial@e6c50000 { 474 compatible = "renesas,scif-r8a77965", 475 "renesas,rcar-gen3-scif", "renesas,scif"; 476 reg = <0 0xe6c50000 0 64>; 477 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&cpg CPG_MOD 204>, 479 <&cpg CPG_CORE 20>, 480 <&scif_clk>; 481 clock-names = "fck", "brg_int", "scif_clk"; 482 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 483 dma-names = "tx", "rx"; 484 power-domains = <&sysc 32>; 485 resets = <&cpg 204>; 486 status = "disabled"; 487 }; 488 489 scif4: serial@e6c40000 { 490 compatible = "renesas,scif-r8a77965", 491 "renesas,rcar-gen3-scif", "renesas,scif"; 492 reg = <0 0xe6c40000 0 64>; 493 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cpg CPG_MOD 203>, 495 <&cpg CPG_CORE 20>, 496 <&scif_clk>; 497 clock-names = "fck", "brg_int", "scif_clk"; 498 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 499 dma-names = "tx", "rx"; 500 power-domains = <&sysc 32>; 501 resets = <&cpg 203>; 502 status = "disabled"; 503 }; 504 505 scif5: serial@e6f30000 { 506 compatible = "renesas,scif-r8a77965", 507 "renesas,rcar-gen3-scif", "renesas,scif"; 508 reg = <0 0xe6f30000 0 64>; 509 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&cpg CPG_MOD 202>, 511 <&cpg CPG_CORE 20>, 512 <&scif_clk>; 513 clock-names = "fck", "brg_int", "scif_clk"; 514 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 515 <&dmac2 0x5b>, <&dmac2 0x5a>; 516 dma-names = "tx", "rx", "tx", "rx"; 517 power-domains = <&sysc 32>; 518 resets = <&cpg 202>; 519 status = "disabled"; 520 }; 521 522 avb: ethernet@e6800000 { 523 #address-cells = <1>; 524 #size-cells = <0>; 525 526 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 527 /* placeholder */ 528 }; 529 530 csi20: csi2@fea80000 { 531 reg = <0 0xfea80000 0 0x10000>; 532 /* placeholder */ 533 534 ports { 535 #address-cells = <1>; 536 #size-cells = <0>; 537 }; 538 }; 539 540 csi40: csi2@feaa0000 { 541 reg = <0 0xfeaa0000 0 0x10000>; 542 /* placeholder */ 543 544 ports { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 }; 548 }; 549 550 vin0: video@e6ef0000 { 551 reg = <0 0xe6ef0000 0 0x1000>; 552 /* placeholder */ 553 }; 554 555 vin1: video@e6ef1000 { 556 reg = <0 0xe6ef1000 0 0x1000>; 557 /* placeholder */ 558 }; 559 560 vin2: video@e6ef2000 { 561 reg = <0 0xe6ef2000 0 0x1000>; 562 /* placeholder */ 563 }; 564 565 vin3: video@e6ef3000 { 566 reg = <0 0xe6ef3000 0 0x1000>; 567 /* placeholder */ 568 }; 569 570 vin4: video@e6ef4000 { 571 reg = <0 0xe6ef4000 0 0x1000>; 572 /* placeholder */ 573 }; 574 575 vin5: video@e6ef5000 { 576 reg = <0 0xe6ef5000 0 0x1000>; 577 /* placeholder */ 578 }; 579 580 vin6: video@e6ef6000 { 581 reg = <0 0xe6ef6000 0 0x1000>; 582 /* placeholder */ 583 }; 584 585 vin7: video@e6ef7000 { 586 reg = <0 0xe6ef7000 0 0x1000>; 587 /* placeholder */ 588 }; 589 590 ohci0: usb@ee080000 { 591 reg = <0 0xee080000 0 0x100>; 592 /* placeholder */ 593 }; 594 595 ehci0: usb@ee080100 { 596 reg = <0 0xee080100 0 0x100>; 597 /* placeholder */ 598 }; 599 600 usb2_phy0: usb-phy@ee080200 { 601 reg = <0 0xee080200 0 0x700>; 602 /* placeholder */ 603 }; 604 605 ohci1: usb@ee0a0000 { 606 reg = <0 0xee0a0000 0 0x100>; 607 /* placeholder */ 608 }; 609 610 ehci1: usb@ee0a0100 { 611 reg = <0 0xee0a0100 0 0x100>; 612 /* placeholder */ 613 }; 614 615 i2c0: i2c@e6500000 { 616 reg = <0 0xe6500000 0 0x40>; 617 /* placeholder */ 618 }; 619 620 i2c1: i2c@e6508000 { 621 reg = <0 0xe6508000 0 0x40>; 622 /* placeholder */ 623 }; 624 625 i2c2: i2c@e6510000 { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 629 reg = <0 0xe6510000 0 0x40>; 630 /* placeholder */ 631 }; 632 633 i2c3: i2c@e66d0000 { 634 reg = <0 0xe66d0000 0 0x40>; 635 /* placeholder */ 636 }; 637 638 i2c4: i2c@e66d8000 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 reg = <0 0xe66d8000 0 0x40>; 643 /* placeholder */ 644 }; 645 646 i2c5: i2c@e66e0000 { 647 reg = <0 0xe66e0000 0 0x40>; 648 /* placeholder */ 649 }; 650 651 i2c6: i2c@e66e8000 { 652 reg = <0 0xe66e8000 0 0x40>; 653 /* placeholder */ 654 }; 655 656 i2c_dvfs: i2c@e60b0000 { 657 #address-cells = <1>; 658 #size-cells = <0>; 659 660 reg = <0 0xe60b0000 0 0x425>; 661 /* placeholder */ 662 }; 663 664 pwm0: pwm@e6e30000 { 665 reg = <0 0xe6e30000 0 8>; 666 /* placeholder */ 667 }; 668 669 pwm1: pwm@e6e31000 { 670 reg = <0 0xe6e31000 0 8>; 671 /* placeholder */ 672 }; 673 674 pwm2: pwm@e6e32000 { 675 reg = <0 0xe6e32000 0 8>; 676 /* placeholder */ 677 }; 678 679 pwm3: pwm@e6e33000 { 680 reg = <0 0xe6e33000 0 8>; 681 /* placeholder */ 682 }; 683 684 pwm4: pwm@e6e34000 { 685 reg = <0 0xe6e34000 0 8>; 686 /* placeholder */ 687 }; 688 689 pwm5: pwm@e6e35000 { 690 reg = <0 0xe6e35000 0 8>; 691 /* placeholder */ 692 }; 693 694 pwm6: pwm@e6e36000 { 695 reg = <0 0xe6e36000 0 8>; 696 /* placeholder */ 697 }; 698 699 du: display@feb00000 { 700 reg = <0 0xfeb00000 0 0x80000>, 701 <0 0xfeb90000 0 0x14>; 702 /* placeholder */ 703 704 ports { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 708 port@0 { 709 reg = <0>; 710 du_out_rgb: endpoint { 711 }; 712 }; 713 port@1 { 714 reg = <1>; 715 du_out_hdmi0: endpoint { 716 }; 717 }; 718 port@2 { 719 reg = <2>; 720 du_out_lvds0: endpoint { 721 }; 722 }; 723 }; 724 }; 725 726 hsusb: usb@e6590000 { 727 reg = <0 0xe6590000 0 0x100>; 728 /* placeholder */ 729 }; 730 731 pciec0: pcie@fe000000 { 732 reg = <0 0xfe000000 0 0x80000>; 733 /* placeholder */ 734 }; 735 736 pciec1: pcie@ee800000 { 737 reg = <0 0xee800000 0 0x80000>; 738 /* placeholder */ 739 }; 740 741 rcar_sound: sound@ec500000 { 742 reg = <0 0xec500000 0 0x1000>, /* SCU */ 743 <0 0xec5a0000 0 0x100>, /* ADG */ 744 <0 0xec540000 0 0x1000>, /* SSIU */ 745 <0 0xec541000 0 0x280>, /* SSI */ 746 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 747 /* placeholder */ 748 749 rcar_sound,dvc { 750 dvc0: dvc-0 { 751 }; 752 dvc1: dvc-1 { 753 }; 754 }; 755 756 rcar_sound,src { 757 src0: src-0 { 758 }; 759 src1: src-1 { 760 }; 761 }; 762 763 rcar_sound,ssi { 764 ssi0: ssi-0 { 765 }; 766 ssi1: ssi-1 { 767 }; 768 }; 769 }; 770 771 usb2_phy1: usb-phy@ee0a0200 { 772 reg = <0 0xee0a0200 0 0x700>; 773 /* placeholder */ 774 }; 775 776 sdhi0: sd@ee100000 { 777 reg = <0 0xee100000 0 0x2000>; 778 /* placeholder */ 779 }; 780 781 sdhi1: sd@ee120000 { 782 reg = <0 0xee120000 0 0x2000>; 783 /* placeholder */ 784 }; 785 786 sdhi2: sd@ee140000 { 787 reg = <0 0xee140000 0 0x2000>; 788 /* placeholder */ 789 }; 790 791 sdhi3: sd@ee160000 { 792 reg = <0 0xee160000 0 0x2000>; 793 /* placeholder */ 794 }; 795 796 usb3_phy0: usb-phy@e65ee000 { 797 reg = <0 0xe65ee000 0 0x90>; 798 #phy-cells = <0>; 799 /* placeholder */ 800 }; 801 802 usb3_peri0: usb@ee020000 { 803 reg = <0 0xee020000 0 0x400>; 804 /* placeholder */ 805 }; 806 807 xhci0: usb@ee000000 { 808 reg = <0 0xee000000 0 0xc00>; 809 /* placeholder */ 810 }; 811 812 wdt0: watchdog@e6020000 { 813 reg = <0 0xe6020000 0 0x0c>; 814 /* placeholder */ 815 }; 816 }; 817}; 818