1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77965 SoC 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Based on r8a7796.dtsi 8 * Copyright (C) 2016 Renesas Electronics Corp. 9 */ 10 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14#define CPG_AUDIO_CLK_I 10 15 16/ { 17 compatible = "renesas,r8a77965"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a57_0: cpu@0 { 31 compatible = "arm,cortex-a57", "arm,armv8"; 32 reg = <0x0>; 33 device_type = "cpu"; 34 power-domains = <&sysc 0>; 35 next-level-cache = <&L2_CA57>; 36 enable-method = "psci"; 37 }; 38 39 a57_1: cpu@1 { 40 compatible = "arm,cortex-a57","arm,armv8"; 41 reg = <0x1>; 42 device_type = "cpu"; 43 power-domains = <&sysc 1>; 44 next-level-cache = <&L2_CA57>; 45 enable-method = "psci"; 46 }; 47 48 L2_CA57: cache-controller-0 { 49 compatible = "cache"; 50 reg = <0>; 51 power-domains = <&sysc 12>; 52 cache-unified; 53 cache-level = <2>; 54 }; 55 }; 56 57 extal_clk: extal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 /* This value must be overridden by the board */ 61 clock-frequency = <0>; 62 }; 63 64 extalr_clk: extalr { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 /* This value must be overridden by the board */ 68 clock-frequency = <0>; 69 }; 70 71 /* 72 * The external audio clocks are configured as 0 Hz fixed frequency 73 * clocks by default. 74 * Boards that provide audio clocks should override them. 75 */ 76 audio_clk_a: audio_clk_a { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <0>; 80 }; 81 82 audio_clk_b: audio_clk_b { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <0>; 86 }; 87 88 audio_clk_c: audio_clk_c { 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <0>; 92 }; 93 94 /* External CAN clock - to be overridden by boards that provide it */ 95 can_clk: can { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <0>; 99 }; 100 101 /* External SCIF clock - to be overridden by boards that provide it */ 102 scif_clk: scif { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 /* External PCIe clock - can be overridden by the board */ 109 pcie_bus_clk: pcie_bus { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <0>; 113 }; 114 115 /* External USB clocks - can be overridden by the board */ 116 usb3s0_clk: usb3s0 { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <0>; 120 }; 121 122 usb_extal_clk: usb_extal { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <0>; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 131 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 132 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 133 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 134 }; 135 136 pmu_a57 { 137 compatible = "arm,cortex-a57-pmu"; 138 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 139 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 140 interrupt-affinity = <&a57_0>, 141 <&a57_1>; 142 }; 143 144 soc { 145 compatible = "simple-bus"; 146 interrupt-parent = <&gic>; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 gic: interrupt-controller@f1010000 { 152 compatible = "arm,gic-400"; 153 #interrupt-cells = <3>; 154 #address-cells = <0>; 155 interrupt-controller; 156 reg = <0x0 0xf1010000 0 0x1000>, 157 <0x0 0xf1020000 0 0x20000>, 158 <0x0 0xf1040000 0 0x20000>, 159 <0x0 0xf1060000 0 0x20000>; 160 interrupts = <GIC_PPI 9 161 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 162 clocks = <&cpg CPG_MOD 408>; 163 clock-names = "clk"; 164 power-domains = <&sysc 32>; 165 resets = <&cpg 408>; 166 }; 167 168 pfc: pin-controller@e6060000 { 169 compatible = "renesas,pfc-r8a77965"; 170 reg = <0 0xe6060000 0 0x50c>; 171 }; 172 173 cpg: clock-controller@e6150000 { 174 compatible = "renesas,r8a77965-cpg-mssr"; 175 reg = <0 0xe6150000 0 0x1000>; 176 clocks = <&extal_clk>, <&extalr_clk>; 177 clock-names = "extal", "extalr"; 178 #clock-cells = <2>; 179 #power-domain-cells = <0>; 180 #reset-cells = <1>; 181 }; 182 183 rst: reset-controller@e6160000 { 184 compatible = "renesas,r8a77965-rst"; 185 reg = <0 0xe6160000 0 0x0200>; 186 }; 187 188 prr: chipid@fff00044 { 189 compatible = "renesas,prr"; 190 reg = <0 0xfff00044 0 4>; 191 }; 192 193 sysc: system-controller@e6180000 { 194 compatible = "renesas,r8a77965-sysc"; 195 reg = <0 0xe6180000 0 0x0400>; 196 #power-domain-cells = <1>; 197 }; 198 199 gpio0: gpio@e6050000 { 200 /* placeholder */ 201 }; 202 203 gpio1: gpio@e6051000 { 204 /* placeholder */ 205 }; 206 207 gpio2: gpio@e6052000 { 208 /* placeholder */ 209 }; 210 211 gpio3: gpio@e6053000 { 212 /* placeholder */ 213 }; 214 215 gpio4: gpio@e6054000 { 216 /* placeholder */ 217 }; 218 219 gpio5: gpio@e6055000 { 220 /* placeholder */ 221 }; 222 223 gpio6: gpio@e6055400 { 224 /* placeholder */ 225 }; 226 227 gpio7: gpio@e6055800 { 228 /* placeholder */ 229 }; 230 231 intc_ex: interrupt-controller@e61c0000 { 232 /* placeholder */ 233 }; 234 235 dmac0: dma-controller@e6700000 { 236 compatible = "renesas,dmac-r8a77965", 237 "renesas,rcar-dmac"; 238 reg = <0 0xe6700000 0 0x10000>; 239 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 240 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 241 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 242 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 243 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 246 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 247 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 248 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 249 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 250 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 251 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 252 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 253 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 254 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 255 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-names = "error", 257 "ch0", "ch1", "ch2", "ch3", 258 "ch4", "ch5", "ch6", "ch7", 259 "ch8", "ch9", "ch10", "ch11", 260 "ch12", "ch13", "ch14", "ch15"; 261 clocks = <&cpg CPG_MOD 219>; 262 clock-names = "fck"; 263 power-domains = <&sysc 32>; 264 resets = <&cpg 219>; 265 #dma-cells = <1>; 266 dma-channels = <16>; 267 }; 268 269 dmac1: dma-controller@e7300000 { 270 compatible = "renesas,dmac-r8a77965", 271 "renesas,rcar-dmac"; 272 reg = <0 0xe7300000 0 0x10000>; 273 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 274 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 275 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 276 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 277 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 278 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 279 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 280 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 281 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 282 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 283 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 284 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 285 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 286 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 287 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 288 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 289 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "error", 291 "ch0", "ch1", "ch2", "ch3", 292 "ch4", "ch5", "ch6", "ch7", 293 "ch8", "ch9", "ch10", "ch11", 294 "ch12", "ch13", "ch14", "ch15"; 295 clocks = <&cpg CPG_MOD 218>; 296 clock-names = "fck"; 297 power-domains = <&sysc 32>; 298 resets = <&cpg 218>; 299 #dma-cells = <1>; 300 dma-channels = <16>; 301 }; 302 303 dmac2: dma-controller@e7310000 { 304 compatible = "renesas,dmac-r8a77965", 305 "renesas,rcar-dmac"; 306 reg = <0 0xe7310000 0 0x10000>; 307 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 311 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 312 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 313 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 314 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 315 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 317 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 318 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 319 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 320 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 321 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 322 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 323 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "error", 325 "ch0", "ch1", "ch2", "ch3", 326 "ch4", "ch5", "ch6", "ch7", 327 "ch8", "ch9", "ch10", "ch11", 328 "ch12", "ch13", "ch14", "ch15"; 329 clocks = <&cpg CPG_MOD 217>; 330 clock-names = "fck"; 331 power-domains = <&sysc 32>; 332 resets = <&cpg 217>; 333 #dma-cells = <1>; 334 dma-channels = <16>; 335 }; 336 337 scif0: serial@e6e60000 { 338 /* placeholder */ 339 }; 340 341 scif1: serial@e6e68000 { 342 /* placeholder */ 343 }; 344 345 scif2: serial@e6e88000 { 346 /* placeholder */ 347 }; 348 349 scif3: serial@e6c50000 { 350 /* placeholder */ 351 }; 352 353 scif4: serial@e6c40000 { 354 /* placeholder */ 355 }; 356 357 scif5: serial@e6f30000 { 358 /* placeholder */ 359 }; 360 361 avb: ethernet@e6800000 { 362 /* placeholder */ 363 }; 364 365 csi20: csi2@fea80000 { 366 /* placeholder */ 367 }; 368 369 csi40: csi2@feaa0000 { 370 /* placeholder */ 371 }; 372 373 vin0: video@e6ef0000 { 374 /* placeholder */ 375 }; 376 377 vin1: video@e6ef1000 { 378 /* placeholder */ 379 }; 380 381 vin2: video@e6ef2000 { 382 /* placeholder */ 383 }; 384 385 vin3: video@e6ef3000 { 386 /* placeholder */ 387 }; 388 389 vin4: video@e6ef4000 { 390 /* placeholder */ 391 }; 392 393 vin5: video@e6ef5000 { 394 /* placeholder */ 395 }; 396 397 vin6: video@e6ef6000 { 398 /* placeholder */ 399 }; 400 401 vin7: video@e6ef7000 { 402 /* placeholder */ 403 }; 404 405 ohci0: usb@ee080000 { 406 /* placeholder */ 407 }; 408 409 ehci0: usb@ee080100 { 410 /* placeholder */ 411 }; 412 413 usb2_phy0: usb-phy@ee080200 { 414 /* placeholder */ 415 }; 416 417 ohci1: usb@ee0a0000 { 418 /* placeholder */ 419 }; 420 421 ehci1: usb@ee0a0100 { 422 /* placeholder */ 423 }; 424 425 i2c0: i2c@e6500000 { 426 /* placeholder */ 427 }; 428 429 i2c1: i2c@e6508000 { 430 /* placeholder */ 431 }; 432 433 i2c2: i2c@e6510000 { 434 /* placeholder */ 435 }; 436 437 i2c3: i2c@e66d0000 { 438 /* placeholder */ 439 }; 440 441 i2c4: i2c@e66d8000 { 442 /* placeholder */ 443 }; 444 445 i2c5: i2c@e66e0000 { 446 /* placeholder */ 447 }; 448 449 i2c6: i2c@e66e8000 { 450 /* placeholder */ 451 }; 452 453 i2c_dvfs: i2c@e60b0000 { 454 /* placeholder */ 455 }; 456 457 pwm0: pwm@e6e30000 { 458 /* placeholder */ 459 }; 460 461 pwm1: pwm@e6e31000 { 462 /* placeholder */ 463 }; 464 465 pwm2: pwm@e6e32000 { 466 /* placeholder */ 467 }; 468 469 pwm3: pwm@e6e33000 { 470 /* placeholder */ 471 }; 472 473 pwm4: pwm@e6e34000 { 474 /* placeholder */ 475 }; 476 477 pwm5: pwm@e6e35000 { 478 /* placeholder */ 479 }; 480 481 pwm6: pwm@e6e36000 { 482 /* placeholder */ 483 }; 484 485 du: display@feb00000 { 486 /* placeholder */ 487 488 ports { 489 port@0 { 490 reg = <0>; 491 du_out_rgb: endpoint { 492 }; 493 }; 494 port@1 { 495 reg = <1>; 496 du_out_hdmi0: endpoint { 497 }; 498 }; 499 port@2 { 500 reg = <2>; 501 du_out_lvds0: endpoint { 502 }; 503 }; 504 }; 505 }; 506 507 hsusb: usb@e6590000 { 508 /* placeholder */ 509 }; 510 511 pciec0: pcie@fe000000 { 512 /* placeholder */ 513 }; 514 515 pciec1: pcie@ee800000 { 516 /* placeholder */ 517 }; 518 519 rcar_sound: sound@ec500000 { 520 /* placeholder */ 521 522 rcar_sound,dvc { 523 dvc0: dvc-0 { 524 }; 525 dvc1: dvc-1 { 526 }; 527 }; 528 529 rcar_sound,src { 530 src0: src-0 { 531 }; 532 src1: src-1 { 533 }; 534 }; 535 536 rcar_sound,ssi { 537 ssi0: ssi-0 { 538 }; 539 ssi1: ssi-1 { 540 }; 541 }; 542 }; 543 544 usb2_phy1: usb-phy@ee0a0200 { 545 /* placeholder */ 546 }; 547 548 sdhi0: sd@ee100000 { 549 /* placeholder */ 550 }; 551 552 sdhi1: sd@ee120000 { 553 /* placeholder */ 554 }; 555 556 sdhi2: sd@ee140000 { 557 /* placeholder */ 558 }; 559 560 sdhi3: sd@ee160000 { 561 /* placeholder */ 562 }; 563 564 usb3_phy0: usb-phy@e65ee000 { 565 /* placeholder */ 566 }; 567 568 usb3_peri0: usb@ee020000 { 569 /* placeholder */ 570 }; 571 572 xhci0: usb@ee000000 { 573 /* placeholder */ 574 }; 575 576 wdt0: watchdog@e6020000 { 577 /* placeholder */ 578 }; 579 }; 580}; 581