1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77965 SoC 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Based on r8a7796.dtsi 8 * Copyright (C) 2016 Renesas Electronics Corp. 9 */ 10 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14#define CPG_AUDIO_CLK_I 10 15 16/ { 17 compatible = "renesas,r8a77965"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 i2c7 = &i2c_dvfs; 23 }; 24 25 /* 26 * The external audio clocks are configured as 0 Hz fixed frequency 27 * clocks by default. 28 * Boards that provide audio clocks should override them. 29 */ 30 audio_clk_a: audio_clk_a { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_b: audio_clk_b { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 audio_clk_c: audio_clk_c { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 /* External CAN clock - to be overridden by boards that provide it */ 49 can_clk: can { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 a57_0: cpu@0 { 60 compatible = "arm,cortex-a57", "arm,armv8"; 61 reg = <0x0>; 62 device_type = "cpu"; 63 power-domains = <&sysc 0>; 64 next-level-cache = <&L2_CA57>; 65 enable-method = "psci"; 66 }; 67 68 a57_1: cpu@1 { 69 compatible = "arm,cortex-a57","arm,armv8"; 70 reg = <0x1>; 71 device_type = "cpu"; 72 power-domains = <&sysc 1>; 73 next-level-cache = <&L2_CA57>; 74 enable-method = "psci"; 75 }; 76 77 L2_CA57: cache-controller-0 { 78 compatible = "cache"; 79 power-domains = <&sysc 12>; 80 cache-unified; 81 cache-level = <2>; 82 }; 83 }; 84 85 extal_clk: extal { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 /* This value must be overridden by the board */ 89 clock-frequency = <0>; 90 }; 91 92 extalr_clk: extalr { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 /* This value must be overridden by the board */ 96 clock-frequency = <0>; 97 }; 98 99 /* External PCIe clock - can be overridden by the board */ 100 pcie_bus_clk: pcie_bus { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <0>; 104 }; 105 106 pmu_a57 { 107 compatible = "arm,cortex-a57-pmu"; 108 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 109 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 110 interrupt-affinity = <&a57_0>, 111 <&a57_1>; 112 }; 113 114 psci { 115 compatible = "arm,psci-1.0", "arm,psci-0.2"; 116 method = "smc"; 117 }; 118 119 /* External SCIF clock - to be overridden by boards that provide it */ 120 scif_clk: scif { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <0>; 124 }; 125 126 soc { 127 compatible = "simple-bus"; 128 interrupt-parent = <&gic>; 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 wdt0: watchdog@e6020000 { 134 reg = <0 0xe6020000 0 0x0c>; 135 /* placeholder */ 136 }; 137 138 gpio0: gpio@e6050000 { 139 compatible = "renesas,gpio-r8a77965", 140 "renesas,rcar-gen3-gpio"; 141 reg = <0 0xe6050000 0 0x50>; 142 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 143 #gpio-cells = <2>; 144 gpio-controller; 145 gpio-ranges = <&pfc 0 0 16>; 146 #interrupt-cells = <2>; 147 interrupt-controller; 148 clocks = <&cpg CPG_MOD 912>; 149 power-domains = <&sysc 32>; 150 resets = <&cpg 912>; 151 }; 152 153 gpio1: gpio@e6051000 { 154 compatible = "renesas,gpio-r8a77965", 155 "renesas,rcar-gen3-gpio"; 156 reg = <0 0xe6051000 0 0x50>; 157 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 158 #gpio-cells = <2>; 159 gpio-controller; 160 gpio-ranges = <&pfc 0 32 29>; 161 #interrupt-cells = <2>; 162 interrupt-controller; 163 clocks = <&cpg CPG_MOD 911>; 164 power-domains = <&sysc 32>; 165 resets = <&cpg 911>; 166 }; 167 168 gpio2: gpio@e6052000 { 169 compatible = "renesas,gpio-r8a77965", 170 "renesas,rcar-gen3-gpio"; 171 reg = <0 0xe6052000 0 0x50>; 172 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 173 #gpio-cells = <2>; 174 gpio-controller; 175 gpio-ranges = <&pfc 0 64 15>; 176 #interrupt-cells = <2>; 177 interrupt-controller; 178 clocks = <&cpg CPG_MOD 910>; 179 power-domains = <&sysc 32>; 180 resets = <&cpg 910>; 181 }; 182 183 gpio3: gpio@e6053000 { 184 compatible = "renesas,gpio-r8a77965", 185 "renesas,rcar-gen3-gpio"; 186 reg = <0 0xe6053000 0 0x50>; 187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 188 #gpio-cells = <2>; 189 gpio-controller; 190 gpio-ranges = <&pfc 0 96 16>; 191 #interrupt-cells = <2>; 192 interrupt-controller; 193 clocks = <&cpg CPG_MOD 909>; 194 power-domains = <&sysc 32>; 195 resets = <&cpg 909>; 196 }; 197 198 gpio4: gpio@e6054000 { 199 compatible = "renesas,gpio-r8a77965", 200 "renesas,rcar-gen3-gpio"; 201 reg = <0 0xe6054000 0 0x50>; 202 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 203 #gpio-cells = <2>; 204 gpio-controller; 205 gpio-ranges = <&pfc 0 128 18>; 206 #interrupt-cells = <2>; 207 interrupt-controller; 208 clocks = <&cpg CPG_MOD 908>; 209 power-domains = <&sysc 32>; 210 resets = <&cpg 908>; 211 }; 212 213 gpio5: gpio@e6055000 { 214 compatible = "renesas,gpio-r8a77965", 215 "renesas,rcar-gen3-gpio"; 216 reg = <0 0xe6055000 0 0x50>; 217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 218 #gpio-cells = <2>; 219 gpio-controller; 220 gpio-ranges = <&pfc 0 160 26>; 221 #interrupt-cells = <2>; 222 interrupt-controller; 223 clocks = <&cpg CPG_MOD 907>; 224 power-domains = <&sysc 32>; 225 resets = <&cpg 907>; 226 }; 227 228 gpio6: gpio@e6055400 { 229 compatible = "renesas,gpio-r8a77965", 230 "renesas,rcar-gen3-gpio"; 231 reg = <0 0xe6055400 0 0x50>; 232 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 233 #gpio-cells = <2>; 234 gpio-controller; 235 gpio-ranges = <&pfc 0 192 32>; 236 #interrupt-cells = <2>; 237 interrupt-controller; 238 clocks = <&cpg CPG_MOD 906>; 239 power-domains = <&sysc 32>; 240 resets = <&cpg 906>; 241 }; 242 243 gpio7: gpio@e6055800 { 244 compatible = "renesas,gpio-r8a77965", 245 "renesas,rcar-gen3-gpio"; 246 reg = <0 0xe6055800 0 0x50>; 247 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 248 #gpio-cells = <2>; 249 gpio-controller; 250 gpio-ranges = <&pfc 0 224 4>; 251 #interrupt-cells = <2>; 252 interrupt-controller; 253 clocks = <&cpg CPG_MOD 905>; 254 power-domains = <&sysc 32>; 255 resets = <&cpg 905>; 256 }; 257 258 pfc: pin-controller@e6060000 { 259 compatible = "renesas,pfc-r8a77965"; 260 reg = <0 0xe6060000 0 0x50c>; 261 }; 262 263 cpg: clock-controller@e6150000 { 264 compatible = "renesas,r8a77965-cpg-mssr"; 265 reg = <0 0xe6150000 0 0x1000>; 266 clocks = <&extal_clk>, <&extalr_clk>; 267 clock-names = "extal", "extalr"; 268 #clock-cells = <2>; 269 #power-domain-cells = <0>; 270 #reset-cells = <1>; 271 }; 272 273 rst: reset-controller@e6160000 { 274 compatible = "renesas,r8a77965-rst"; 275 reg = <0 0xe6160000 0 0x0200>; 276 }; 277 278 sysc: system-controller@e6180000 { 279 compatible = "renesas,r8a77965-sysc"; 280 reg = <0 0xe6180000 0 0x0400>; 281 #power-domain-cells = <1>; 282 }; 283 284 intc_ex: interrupt-controller@e61c0000 { 285 compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; 286 #interrupt-cells = <2>; 287 interrupt-controller; 288 reg = <0 0xe61c0000 0 0x200>; 289 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 290 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 291 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 292 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 293 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 294 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&cpg CPG_MOD 407>; 296 power-domains = <&sysc 32>; 297 resets = <&cpg 407>; 298 }; 299 300 i2c0: i2c@e6500000 { 301 reg = <0 0xe6500000 0 0x40>; 302 /* placeholder */ 303 }; 304 305 i2c1: i2c@e6508000 { 306 reg = <0 0xe6508000 0 0x40>; 307 /* placeholder */ 308 }; 309 310 i2c2: i2c@e6510000 { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 314 reg = <0 0xe6510000 0 0x40>; 315 /* placeholder */ 316 }; 317 318 i2c3: i2c@e66d0000 { 319 reg = <0 0xe66d0000 0 0x40>; 320 /* placeholder */ 321 }; 322 323 i2c4: i2c@e66d8000 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 reg = <0 0xe66d8000 0 0x40>; 328 /* placeholder */ 329 }; 330 331 i2c5: i2c@e66e0000 { 332 reg = <0 0xe66e0000 0 0x40>; 333 /* placeholder */ 334 }; 335 336 i2c6: i2c@e66e8000 { 337 reg = <0 0xe66e8000 0 0x40>; 338 /* placeholder */ 339 }; 340 341 i2c_dvfs: i2c@e60b0000 { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 compatible = "renesas,iic-r8a77965", 345 "renesas,rcar-gen3-iic", 346 "renesas,rmobile-iic"; 347 reg = <0 0xe60b0000 0 0x425>; 348 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cpg CPG_MOD 926>; 350 power-domains = <&sysc 32>; 351 resets = <&cpg 926>; 352 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 353 dma-names = "tx", "rx"; 354 status = "disabled"; 355 }; 356 357 hsusb: usb@e6590000 { 358 compatible = "renesas,usbhs-r8a7796", 359 "renesas,rcar-gen3-usbhs"; 360 reg = <0 0xe6590000 0 0x100>; 361 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cpg CPG_MOD 704>; 363 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 364 <&usb_dmac1 0>, <&usb_dmac1 1>; 365 dma-names = "ch0", "ch1", "ch2", "ch3"; 366 renesas,buswait = <11>; 367 phys = <&usb2_phy0>; 368 phy-names = "usb"; 369 power-domains = <&sysc 32>; 370 resets = <&cpg 704>; 371 status = "disabled"; 372 }; 373 374 usb_dmac0: dma-controller@e65a0000 { 375 compatible = "renesas,r8a77965-usb-dmac", 376 "renesas,usb-dmac"; 377 reg = <0 0xe65a0000 0 0x100>; 378 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 379 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 380 interrupt-names = "ch0", "ch1"; 381 clocks = <&cpg CPG_MOD 330>; 382 power-domains = <&sysc 32>; 383 resets = <&cpg 330>; 384 #dma-cells = <1>; 385 dma-channels = <2>; 386 }; 387 388 usb_dmac1: dma-controller@e65b0000 { 389 compatible = "renesas,r8a77965-usb-dmac", 390 "renesas,usb-dmac"; 391 reg = <0 0xe65b0000 0 0x100>; 392 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 393 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 394 interrupt-names = "ch0", "ch1"; 395 clocks = <&cpg CPG_MOD 331>; 396 power-domains = <&sysc 32>; 397 resets = <&cpg 331>; 398 #dma-cells = <1>; 399 dma-channels = <2>; 400 }; 401 402 usb3_phy0: usb-phy@e65ee000 { 403 compatible = "renesas,r8a77965-usb3-phy", 404 "renesas,rcar-gen3-usb3-phy"; 405 reg = <0 0xe65ee000 0 0x90>; 406 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 407 <&usb_extal_clk>; 408 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 409 power-domains = <&sysc 32>; 410 resets = <&cpg 328>; 411 #phy-cells = <0>; 412 status = "disabled"; 413 }; 414 415 dmac0: dma-controller@e6700000 { 416 compatible = "renesas,dmac-r8a77965", 417 "renesas,rcar-dmac"; 418 reg = <0 0xe6700000 0 0x10000>; 419 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 420 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 421 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 422 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 423 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 424 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 425 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 426 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 427 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 428 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 429 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 430 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 431 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 432 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 433 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 434 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 435 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 436 interrupt-names = "error", 437 "ch0", "ch1", "ch2", "ch3", 438 "ch4", "ch5", "ch6", "ch7", 439 "ch8", "ch9", "ch10", "ch11", 440 "ch12", "ch13", "ch14", "ch15"; 441 clocks = <&cpg CPG_MOD 219>; 442 clock-names = "fck"; 443 power-domains = <&sysc 32>; 444 resets = <&cpg 219>; 445 #dma-cells = <1>; 446 dma-channels = <16>; 447 }; 448 449 dmac1: dma-controller@e7300000 { 450 compatible = "renesas,dmac-r8a77965", 451 "renesas,rcar-dmac"; 452 reg = <0 0xe7300000 0 0x10000>; 453 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 454 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 455 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 456 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 457 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 458 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 459 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 460 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 461 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 462 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 463 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 464 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 465 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 466 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 467 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 468 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 469 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "error", 471 "ch0", "ch1", "ch2", "ch3", 472 "ch4", "ch5", "ch6", "ch7", 473 "ch8", "ch9", "ch10", "ch11", 474 "ch12", "ch13", "ch14", "ch15"; 475 clocks = <&cpg CPG_MOD 218>; 476 clock-names = "fck"; 477 power-domains = <&sysc 32>; 478 resets = <&cpg 218>; 479 #dma-cells = <1>; 480 dma-channels = <16>; 481 }; 482 483 dmac2: dma-controller@e7310000 { 484 compatible = "renesas,dmac-r8a77965", 485 "renesas,rcar-dmac"; 486 reg = <0 0xe7310000 0 0x10000>; 487 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 488 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 489 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 490 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 491 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 492 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 493 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 494 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 495 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 496 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 497 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 498 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 499 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 500 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 501 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 502 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 503 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "error", 505 "ch0", "ch1", "ch2", "ch3", 506 "ch4", "ch5", "ch6", "ch7", 507 "ch8", "ch9", "ch10", "ch11", 508 "ch12", "ch13", "ch14", "ch15"; 509 clocks = <&cpg CPG_MOD 217>; 510 clock-names = "fck"; 511 power-domains = <&sysc 32>; 512 resets = <&cpg 217>; 513 #dma-cells = <1>; 514 dma-channels = <16>; 515 }; 516 517 avb: ethernet@e6800000 { 518 compatible = "renesas,etheravb-r8a77965", 519 "renesas,etheravb-rcar-gen3"; 520 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 521 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 546 interrupt-names = "ch0", "ch1", "ch2", "ch3", 547 "ch4", "ch5", "ch6", "ch7", 548 "ch8", "ch9", "ch10", "ch11", 549 "ch12", "ch13", "ch14", "ch15", 550 "ch16", "ch17", "ch18", "ch19", 551 "ch20", "ch21", "ch22", "ch23", 552 "ch24"; 553 clocks = <&cpg CPG_MOD 812>; 554 power-domains = <&sysc 32>; 555 resets = <&cpg 812>; 556 phy-mode = "rgmii"; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 status = "disabled"; 560 }; 561 562 pwm0: pwm@e6e30000 { 563 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 564 reg = <0 0xe6e30000 0 8>; 565 #pwm-cells = <2>; 566 clocks = <&cpg CPG_MOD 523>; 567 resets = <&cpg 523>; 568 power-domains = <&sysc 32>; 569 status = "disabled"; 570 }; 571 572 pwm1: pwm@e6e31000 { 573 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 574 reg = <0 0xe6e31000 0 8>; 575 #pwm-cells = <2>; 576 clocks = <&cpg CPG_MOD 523>; 577 resets = <&cpg 523>; 578 power-domains = <&sysc 32>; 579 status = "disabled"; 580 }; 581 582 pwm2: pwm@e6e32000 { 583 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 584 reg = <0 0xe6e32000 0 8>; 585 #pwm-cells = <2>; 586 clocks = <&cpg CPG_MOD 523>; 587 resets = <&cpg 523>; 588 power-domains = <&sysc 32>; 589 status = "disabled"; 590 }; 591 592 pwm3: pwm@e6e33000 { 593 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 594 reg = <0 0xe6e33000 0 8>; 595 #pwm-cells = <2>; 596 clocks = <&cpg CPG_MOD 523>; 597 resets = <&cpg 523>; 598 power-domains = <&sysc 32>; 599 status = "disabled"; 600 }; 601 602 pwm4: pwm@e6e34000 { 603 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 604 reg = <0 0xe6e34000 0 8>; 605 #pwm-cells = <2>; 606 clocks = <&cpg CPG_MOD 523>; 607 resets = <&cpg 523>; 608 power-domains = <&sysc 32>; 609 status = "disabled"; 610 }; 611 612 pwm5: pwm@e6e35000 { 613 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 614 reg = <0 0xe6e35000 0 8>; 615 #pwm-cells = <2>; 616 clocks = <&cpg CPG_MOD 523>; 617 resets = <&cpg 523>; 618 power-domains = <&sysc 32>; 619 status = "disabled"; 620 }; 621 622 pwm6: pwm@e6e36000 { 623 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; 624 reg = <0 0xe6e36000 0 8>; 625 #pwm-cells = <2>; 626 clocks = <&cpg CPG_MOD 523>; 627 resets = <&cpg 523>; 628 power-domains = <&sysc 32>; 629 status = "disabled"; 630 }; 631 632 scif0: serial@e6e60000 { 633 compatible = "renesas,scif-r8a77965", 634 "renesas,rcar-gen3-scif", "renesas,scif"; 635 reg = <0 0xe6e60000 0 64>; 636 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cpg CPG_MOD 207>, 638 <&cpg CPG_CORE 20>, 639 <&scif_clk>; 640 clock-names = "fck", "brg_int", "scif_clk"; 641 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 642 <&dmac2 0x51>, <&dmac2 0x50>; 643 dma-names = "tx", "rx", "tx", "rx"; 644 power-domains = <&sysc 32>; 645 resets = <&cpg 207>; 646 status = "disabled"; 647 }; 648 649 scif1: serial@e6e68000 { 650 compatible = "renesas,scif-r8a77965", 651 "renesas,rcar-gen3-scif", "renesas,scif"; 652 reg = <0 0xe6e68000 0 64>; 653 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&cpg CPG_MOD 206>, 655 <&cpg CPG_CORE 20>, 656 <&scif_clk>; 657 clock-names = "fck", "brg_int", "scif_clk"; 658 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 659 <&dmac2 0x53>, <&dmac2 0x52>; 660 dma-names = "tx", "rx", "tx", "rx"; 661 power-domains = <&sysc 32>; 662 resets = <&cpg 206>; 663 status = "disabled"; 664 }; 665 666 scif2: serial@e6e88000 { 667 compatible = "renesas,scif-r8a77965", 668 "renesas,rcar-gen3-scif", "renesas,scif"; 669 reg = <0 0xe6e88000 0 64>; 670 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 310>, 672 <&cpg CPG_CORE 20>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 power-domains = <&sysc 32>; 676 resets = <&cpg 310>; 677 status = "disabled"; 678 }; 679 680 scif3: serial@e6c50000 { 681 compatible = "renesas,scif-r8a77965", 682 "renesas,rcar-gen3-scif", "renesas,scif"; 683 reg = <0 0xe6c50000 0 64>; 684 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cpg CPG_MOD 204>, 686 <&cpg CPG_CORE 20>, 687 <&scif_clk>; 688 clock-names = "fck", "brg_int", "scif_clk"; 689 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 690 dma-names = "tx", "rx"; 691 power-domains = <&sysc 32>; 692 resets = <&cpg 204>; 693 status = "disabled"; 694 }; 695 696 scif4: serial@e6c40000 { 697 compatible = "renesas,scif-r8a77965", 698 "renesas,rcar-gen3-scif", "renesas,scif"; 699 reg = <0 0xe6c40000 0 64>; 700 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 203>, 702 <&cpg CPG_CORE 20>, 703 <&scif_clk>; 704 clock-names = "fck", "brg_int", "scif_clk"; 705 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 706 dma-names = "tx", "rx"; 707 power-domains = <&sysc 32>; 708 resets = <&cpg 203>; 709 status = "disabled"; 710 }; 711 712 scif5: serial@e6f30000 { 713 compatible = "renesas,scif-r8a77965", 714 "renesas,rcar-gen3-scif", "renesas,scif"; 715 reg = <0 0xe6f30000 0 64>; 716 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cpg CPG_MOD 202>, 718 <&cpg CPG_CORE 20>, 719 <&scif_clk>; 720 clock-names = "fck", "brg_int", "scif_clk"; 721 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 722 <&dmac2 0x5b>, <&dmac2 0x5a>; 723 dma-names = "tx", "rx", "tx", "rx"; 724 power-domains = <&sysc 32>; 725 resets = <&cpg 202>; 726 status = "disabled"; 727 }; 728 729 msiof0: spi@e6e90000 { 730 compatible = "renesas,msiof-r8a77965", 731 "renesas,rcar-gen3-msiof"; 732 reg = <0 0xe6e90000 0 0x0064>; 733 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cpg CPG_MOD 211>; 735 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 736 <&dmac2 0x41>, <&dmac2 0x40>; 737 dma-names = "tx", "rx", "tx", "rx"; 738 power-domains = <&sysc 32>; 739 resets = <&cpg 211>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 status = "disabled"; 743 }; 744 745 msiof1: spi@e6ea0000 { 746 compatible = "renesas,msiof-r8a77965", 747 "renesas,rcar-gen3-msiof"; 748 reg = <0 0xe6ea0000 0 0x0064>; 749 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&cpg CPG_MOD 210>; 751 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 752 <&dmac2 0x43>, <&dmac2 0x42>; 753 dma-names = "tx", "rx", "tx", "rx"; 754 power-domains = <&sysc 32>; 755 resets = <&cpg 210>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 msiof2: spi@e6c00000 { 762 compatible = "renesas,msiof-r8a77965", 763 "renesas,rcar-gen3-msiof"; 764 reg = <0 0xe6c00000 0 0x0064>; 765 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cpg CPG_MOD 209>; 767 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 768 dma-names = "tx", "rx"; 769 power-domains = <&sysc 32>; 770 resets = <&cpg 209>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 msiof3: spi@e6c10000 { 777 compatible = "renesas,msiof-r8a77965", 778 "renesas,rcar-gen3-msiof"; 779 reg = <0 0xe6c10000 0 0x0064>; 780 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD 208>; 782 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 783 dma-names = "tx", "rx"; 784 power-domains = <&sysc 32>; 785 resets = <&cpg 208>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 status = "disabled"; 789 }; 790 791 vin0: video@e6ef0000 { 792 reg = <0 0xe6ef0000 0 0x1000>; 793 /* placeholder */ 794 }; 795 796 vin1: video@e6ef1000 { 797 reg = <0 0xe6ef1000 0 0x1000>; 798 /* placeholder */ 799 }; 800 801 vin2: video@e6ef2000 { 802 reg = <0 0xe6ef2000 0 0x1000>; 803 /* placeholder */ 804 }; 805 806 vin3: video@e6ef3000 { 807 reg = <0 0xe6ef3000 0 0x1000>; 808 /* placeholder */ 809 }; 810 811 vin4: video@e6ef4000 { 812 reg = <0 0xe6ef4000 0 0x1000>; 813 /* placeholder */ 814 }; 815 816 vin5: video@e6ef5000 { 817 reg = <0 0xe6ef5000 0 0x1000>; 818 /* placeholder */ 819 }; 820 821 vin6: video@e6ef6000 { 822 reg = <0 0xe6ef6000 0 0x1000>; 823 /* placeholder */ 824 }; 825 826 vin7: video@e6ef7000 { 827 reg = <0 0xe6ef7000 0 0x1000>; 828 /* placeholder */ 829 }; 830 831 rcar_sound: sound@ec500000 { 832 reg = <0 0xec500000 0 0x1000>, /* SCU */ 833 <0 0xec5a0000 0 0x100>, /* ADG */ 834 <0 0xec540000 0 0x1000>, /* SSIU */ 835 <0 0xec541000 0 0x280>, /* SSI */ 836 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 837 /* placeholder */ 838 839 rcar_sound,dvc { 840 dvc0: dvc-0 { 841 }; 842 dvc1: dvc-1 { 843 }; 844 }; 845 846 rcar_sound,src { 847 src0: src-0 { 848 }; 849 src1: src-1 { 850 }; 851 }; 852 853 rcar_sound,ssi { 854 ssi0: ssi-0 { 855 }; 856 ssi1: ssi-1 { 857 }; 858 }; 859 }; 860 861 xhci0: usb@ee000000 { 862 compatible = "renesas,xhci-r8a77965", 863 "renesas,rcar-gen3-xhci"; 864 reg = <0 0xee000000 0 0xc00>; 865 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&cpg CPG_MOD 328>; 867 power-domains = <&sysc 32>; 868 resets = <&cpg 328>; 869 status = "disabled"; 870 }; 871 872 usb3_peri0: usb@ee020000 { 873 compatible = "renesas,r8a77965-usb3-peri", 874 "renesas,rcar-gen3-usb3-peri"; 875 reg = <0 0xee020000 0 0x400>; 876 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&cpg CPG_MOD 328>; 878 power-domains = <&sysc 32>; 879 resets = <&cpg 328>; 880 status = "disabled"; 881 }; 882 883 ohci0: usb@ee080000 { 884 compatible = "generic-ohci"; 885 reg = <0 0xee080000 0 0x100>; 886 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cpg CPG_MOD 703>; 888 phys = <&usb2_phy0>; 889 phy-names = "usb"; 890 power-domains = <&sysc 32>; 891 resets = <&cpg 703>; 892 status = "disabled"; 893 }; 894 895 ohci1: usb@ee0a0000 { 896 compatible = "generic-ohci"; 897 reg = <0 0xee0a0000 0 0x100>; 898 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&cpg CPG_MOD 702>; 900 phys = <&usb2_phy1>; 901 phy-names = "usb"; 902 power-domains = <&sysc 32>; 903 resets = <&cpg 702>; 904 status = "disabled"; 905 }; 906 907 ehci0: usb@ee080100 { 908 compatible = "generic-ehci"; 909 reg = <0 0xee080100 0 0x100>; 910 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&cpg CPG_MOD 703>; 912 phys = <&usb2_phy0>; 913 phy-names = "usb"; 914 companion = <&ohci0>; 915 power-domains = <&sysc 32>; 916 resets = <&cpg 703>; 917 status = "disabled"; 918 }; 919 920 ehci1: usb@ee0a0100 { 921 compatible = "generic-ehci"; 922 reg = <0 0xee0a0100 0 0x100>; 923 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&cpg CPG_MOD 702>; 925 phys = <&usb2_phy1>; 926 phy-names = "usb"; 927 companion = <&ohci1>; 928 power-domains = <&sysc 32>; 929 resets = <&cpg 702>; 930 status = "disabled"; 931 }; 932 933 usb2_phy0: usb-phy@ee080200 { 934 compatible = "renesas,usb2-phy-r8a77965", 935 "renesas,rcar-gen3-usb2-phy"; 936 reg = <0 0xee080200 0 0x700>; 937 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&cpg CPG_MOD 703>; 939 power-domains = <&sysc 32>; 940 resets = <&cpg 703>; 941 #phy-cells = <0>; 942 status = "disabled"; 943 }; 944 945 usb2_phy1: usb-phy@ee0a0200 { 946 compatible = "renesas,usb2-phy-r8a77965", 947 "renesas,rcar-gen3-usb2-phy"; 948 reg = <0 0xee0a0200 0 0x700>; 949 clocks = <&cpg CPG_MOD 703>; 950 power-domains = <&sysc 32>; 951 resets = <&cpg 703>; 952 #phy-cells = <0>; 953 status = "disabled"; 954 }; 955 956 sdhi0: sd@ee100000 { 957 reg = <0 0xee100000 0 0x2000>; 958 /* placeholder */ 959 }; 960 961 sdhi1: sd@ee120000 { 962 reg = <0 0xee120000 0 0x2000>; 963 /* placeholder */ 964 }; 965 966 sdhi2: sd@ee140000 { 967 reg = <0 0xee140000 0 0x2000>; 968 /* placeholder */ 969 }; 970 971 sdhi3: sd@ee160000 { 972 reg = <0 0xee160000 0 0x2000>; 973 /* placeholder */ 974 }; 975 976 gic: interrupt-controller@f1010000 { 977 compatible = "arm,gic-400"; 978 #interrupt-cells = <3>; 979 #address-cells = <0>; 980 interrupt-controller; 981 reg = <0x0 0xf1010000 0 0x1000>, 982 <0x0 0xf1020000 0 0x20000>, 983 <0x0 0xf1040000 0 0x20000>, 984 <0x0 0xf1060000 0 0x20000>; 985 interrupts = <GIC_PPI 9 986 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 987 clocks = <&cpg CPG_MOD 408>; 988 clock-names = "clk"; 989 power-domains = <&sysc 32>; 990 resets = <&cpg 408>; 991 }; 992 993 pciec0: pcie@fe000000 { 994 reg = <0 0xfe000000 0 0x80000>; 995 /* placeholder */ 996 }; 997 998 pciec1: pcie@ee800000 { 999 reg = <0 0xee800000 0 0x80000>; 1000 /* placeholder */ 1001 }; 1002 1003 csi20: csi2@fea80000 { 1004 reg = <0 0xfea80000 0 0x10000>; 1005 /* placeholder */ 1006 1007 ports { 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 }; 1011 }; 1012 1013 csi40: csi2@feaa0000 { 1014 reg = <0 0xfeaa0000 0 0x10000>; 1015 /* placeholder */ 1016 1017 ports { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 }; 1021 }; 1022 1023 du: display@feb00000 { 1024 reg = <0 0xfeb00000 0 0x80000>, 1025 <0 0xfeb90000 0 0x14>; 1026 /* placeholder */ 1027 1028 ports { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 1032 port@0 { 1033 reg = <0>; 1034 du_out_rgb: endpoint { 1035 }; 1036 }; 1037 port@1 { 1038 reg = <1>; 1039 du_out_hdmi0: endpoint { 1040 }; 1041 }; 1042 port@2 { 1043 reg = <2>; 1044 du_out_lvds0: endpoint { 1045 }; 1046 }; 1047 }; 1048 }; 1049 1050 prr: chipid@fff00044 { 1051 compatible = "renesas,prr"; 1052 reg = <0 0xfff00044 0 4>; 1053 }; 1054 }; 1055 1056 timer { 1057 compatible = "arm,armv8-timer"; 1058 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1059 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1060 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1061 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1062 }; 1063 1064 /* External USB clocks - can be overridden by the board */ 1065 usb3s0_clk: usb3s0 { 1066 compatible = "fixed-clock"; 1067 #clock-cells = <0>; 1068 clock-frequency = <0>; 1069 }; 1070 1071 usb_extal_clk: usb_extal { 1072 compatible = "fixed-clock"; 1073 #clock-cells = <0>; 1074 clock-frequency = <0>; 1075 }; 1076}; 1077