1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77965 SoC 4 * 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 6 * 7 * Based on r8a7796.dtsi 8 * Copyright (C) 2016 Renesas Electronics Corp. 9 */ 10 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14#define CPG_AUDIO_CLK_I 10 15 16/ { 17 compatible = "renesas,r8a77965"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-1.0", "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 a57_0: cpu@0 { 31 compatible = "arm,cortex-a57", "arm,armv8"; 32 reg = <0x0>; 33 device_type = "cpu"; 34 power-domains = <&sysc 0>; 35 next-level-cache = <&L2_CA57>; 36 enable-method = "psci"; 37 }; 38 39 a57_1: cpu@1 { 40 compatible = "arm,cortex-a57","arm,armv8"; 41 reg = <0x1>; 42 device_type = "cpu"; 43 power-domains = <&sysc 1>; 44 next-level-cache = <&L2_CA57>; 45 enable-method = "psci"; 46 }; 47 48 L2_CA57: cache-controller-0 { 49 compatible = "cache"; 50 reg = <0>; 51 power-domains = <&sysc 12>; 52 cache-unified; 53 cache-level = <2>; 54 }; 55 }; 56 57 extal_clk: extal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 /* This value must be overridden by the board */ 61 clock-frequency = <0>; 62 }; 63 64 extalr_clk: extalr { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 /* This value must be overridden by the board */ 68 clock-frequency = <0>; 69 }; 70 71 /* 72 * The external audio clocks are configured as 0 Hz fixed frequency 73 * clocks by default. 74 * Boards that provide audio clocks should override them. 75 */ 76 audio_clk_a: audio_clk_a { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <0>; 80 }; 81 82 audio_clk_b: audio_clk_b { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <0>; 86 }; 87 88 audio_clk_c: audio_clk_c { 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <0>; 92 }; 93 94 /* External CAN clock - to be overridden by boards that provide it */ 95 can_clk: can { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <0>; 99 }; 100 101 /* External SCIF clock - to be overridden by boards that provide it */ 102 scif_clk: scif { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 }; 107 108 /* External PCIe clock - can be overridden by the board */ 109 pcie_bus_clk: pcie_bus { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <0>; 113 }; 114 115 /* External USB clocks - can be overridden by the board */ 116 usb3s0_clk: usb3s0 { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <0>; 120 }; 121 122 usb_extal_clk: usb_extal { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <0>; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 131 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 132 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 133 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 134 }; 135 136 pmu_a57 { 137 compatible = "arm,cortex-a57-pmu"; 138 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 139 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 140 interrupt-affinity = <&a57_0>, 141 <&a57_1>; 142 }; 143 144 soc { 145 compatible = "simple-bus"; 146 interrupt-parent = <&gic>; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 gic: interrupt-controller@f1010000 { 152 compatible = "arm,gic-400"; 153 #interrupt-cells = <3>; 154 #address-cells = <0>; 155 interrupt-controller; 156 reg = <0x0 0xf1010000 0 0x1000>, 157 <0x0 0xf1020000 0 0x20000>, 158 <0x0 0xf1040000 0 0x20000>, 159 <0x0 0xf1060000 0 0x20000>; 160 interrupts = <GIC_PPI 9 161 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 162 clocks = <&cpg CPG_MOD 408>; 163 clock-names = "clk"; 164 power-domains = <&sysc 32>; 165 resets = <&cpg 408>; 166 }; 167 168 pfc: pin-controller@e6060000 { 169 compatible = "renesas,pfc-r8a77965"; 170 reg = <0 0xe6060000 0 0x50c>; 171 }; 172 173 cpg: clock-controller@e6150000 { 174 compatible = "renesas,r8a77965-cpg-mssr"; 175 reg = <0 0xe6150000 0 0x1000>; 176 clocks = <&extal_clk>, <&extalr_clk>; 177 clock-names = "extal", "extalr"; 178 #clock-cells = <2>; 179 #power-domain-cells = <0>; 180 #reset-cells = <1>; 181 }; 182 183 rst: reset-controller@e6160000 { 184 compatible = "renesas,r8a77965-rst"; 185 reg = <0 0xe6160000 0 0x0200>; 186 }; 187 188 prr: chipid@fff00044 { 189 compatible = "renesas,prr"; 190 reg = <0 0xfff00044 0 4>; 191 }; 192 193 sysc: system-controller@e6180000 { 194 compatible = "renesas,r8a77965-sysc"; 195 reg = <0 0xe6180000 0 0x0400>; 196 #power-domain-cells = <1>; 197 }; 198 199 gpio0: gpio@e6050000 { 200 /* placeholder */ 201 }; 202 203 gpio1: gpio@e6051000 { 204 /* placeholder */ 205 }; 206 207 gpio2: gpio@e6052000 { 208 /* placeholder */ 209 }; 210 211 gpio3: gpio@e6053000 { 212 /* placeholder */ 213 }; 214 215 gpio4: gpio@e6054000 { 216 /* placeholder */ 217 }; 218 219 gpio5: gpio@e6055000 { 220 /* placeholder */ 221 }; 222 223 gpio6: gpio@e6055400 { 224 /* placeholder */ 225 }; 226 227 gpio7: gpio@e6055800 { 228 /* placeholder */ 229 }; 230 231 intc_ex: interrupt-controller@e61c0000 { 232 /* placeholder */ 233 }; 234 235 dmac0: dma-controller@e6700000 { 236 compatible = "renesas,dmac-r8a77965", 237 "renesas,rcar-dmac"; 238 reg = <0 0xe6700000 0 0x10000>; 239 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 240 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 241 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 242 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 243 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 246 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 247 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 248 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 249 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 250 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 251 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 252 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 253 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 254 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 255 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-names = "error", 257 "ch0", "ch1", "ch2", "ch3", 258 "ch4", "ch5", "ch6", "ch7", 259 "ch8", "ch9", "ch10", "ch11", 260 "ch12", "ch13", "ch14", "ch15"; 261 clocks = <&cpg CPG_MOD 219>; 262 clock-names = "fck"; 263 power-domains = <&sysc 32>; 264 resets = <&cpg 219>; 265 #dma-cells = <1>; 266 dma-channels = <16>; 267 }; 268 269 dmac1: dma-controller@e7300000 { 270 compatible = "renesas,dmac-r8a77965", 271 "renesas,rcar-dmac"; 272 reg = <0 0xe7300000 0 0x10000>; 273 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 274 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 275 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 276 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 277 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 278 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 279 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 280 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 281 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 282 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 283 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 284 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 285 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 286 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 287 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 288 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 289 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "error", 291 "ch0", "ch1", "ch2", "ch3", 292 "ch4", "ch5", "ch6", "ch7", 293 "ch8", "ch9", "ch10", "ch11", 294 "ch12", "ch13", "ch14", "ch15"; 295 clocks = <&cpg CPG_MOD 218>; 296 clock-names = "fck"; 297 power-domains = <&sysc 32>; 298 resets = <&cpg 218>; 299 #dma-cells = <1>; 300 dma-channels = <16>; 301 }; 302 303 dmac2: dma-controller@e7310000 { 304 compatible = "renesas,dmac-r8a77965", 305 "renesas,rcar-dmac"; 306 reg = <0 0xe7310000 0 0x10000>; 307 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 311 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 312 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 313 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 314 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 315 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 317 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 318 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 319 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 320 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 321 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 322 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 323 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "error", 325 "ch0", "ch1", "ch2", "ch3", 326 "ch4", "ch5", "ch6", "ch7", 327 "ch8", "ch9", "ch10", "ch11", 328 "ch12", "ch13", "ch14", "ch15"; 329 clocks = <&cpg CPG_MOD 217>; 330 clock-names = "fck"; 331 power-domains = <&sysc 32>; 332 resets = <&cpg 217>; 333 #dma-cells = <1>; 334 dma-channels = <16>; 335 }; 336 337 scif0: serial@e6e60000 { 338 compatible = "renesas,scif-r8a77965", 339 "renesas,rcar-gen3-scif", "renesas,scif"; 340 reg = <0 0xe6e60000 0 64>; 341 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cpg CPG_MOD 207>, 343 <&cpg CPG_CORE 20>, 344 <&scif_clk>; 345 clock-names = "fck", "brg_int", "scif_clk"; 346 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 347 <&dmac2 0x51>, <&dmac2 0x50>; 348 dma-names = "tx", "rx", "tx", "rx"; 349 power-domains = <&sysc 32>; 350 resets = <&cpg 207>; 351 status = "disabled"; 352 }; 353 354 scif1: serial@e6e68000 { 355 compatible = "renesas,scif-r8a77965", 356 "renesas,rcar-gen3-scif", "renesas,scif"; 357 reg = <0 0xe6e68000 0 64>; 358 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&cpg CPG_MOD 206>, 360 <&cpg CPG_CORE 20>, 361 <&scif_clk>; 362 clock-names = "fck", "brg_int", "scif_clk"; 363 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 364 <&dmac2 0x53>, <&dmac2 0x52>; 365 dma-names = "tx", "rx", "tx", "rx"; 366 power-domains = <&sysc 32>; 367 resets = <&cpg 206>; 368 status = "disabled"; 369 }; 370 371 scif2: serial@e6e88000 { 372 compatible = "renesas,scif-r8a77965", 373 "renesas,rcar-gen3-scif", "renesas,scif"; 374 reg = <0 0xe6e88000 0 64>; 375 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cpg CPG_MOD 310>, 377 <&cpg CPG_CORE 20>, 378 <&scif_clk>; 379 clock-names = "fck", "brg_int", "scif_clk"; 380 power-domains = <&sysc 32>; 381 resets = <&cpg 310>; 382 status = "disabled"; 383 }; 384 385 scif3: serial@e6c50000 { 386 compatible = "renesas,scif-r8a77965", 387 "renesas,rcar-gen3-scif", "renesas,scif"; 388 reg = <0 0xe6c50000 0 64>; 389 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 204>, 391 <&cpg CPG_CORE 20>, 392 <&scif_clk>; 393 clock-names = "fck", "brg_int", "scif_clk"; 394 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 395 dma-names = "tx", "rx"; 396 power-domains = <&sysc 32>; 397 resets = <&cpg 204>; 398 status = "disabled"; 399 }; 400 401 scif4: serial@e6c40000 { 402 compatible = "renesas,scif-r8a77965", 403 "renesas,rcar-gen3-scif", "renesas,scif"; 404 reg = <0 0xe6c40000 0 64>; 405 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cpg CPG_MOD 203>, 407 <&cpg CPG_CORE 20>, 408 <&scif_clk>; 409 clock-names = "fck", "brg_int", "scif_clk"; 410 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 411 dma-names = "tx", "rx"; 412 power-domains = <&sysc 32>; 413 resets = <&cpg 203>; 414 status = "disabled"; 415 }; 416 417 scif5: serial@e6f30000 { 418 compatible = "renesas,scif-r8a77965", 419 "renesas,rcar-gen3-scif", "renesas,scif"; 420 reg = <0 0xe6f30000 0 64>; 421 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&cpg CPG_MOD 202>, 423 <&cpg CPG_CORE 20>, 424 <&scif_clk>; 425 clock-names = "fck", "brg_int", "scif_clk"; 426 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 427 <&dmac2 0x5b>, <&dmac2 0x5a>; 428 dma-names = "tx", "rx", "tx", "rx"; 429 power-domains = <&sysc 32>; 430 resets = <&cpg 202>; 431 status = "disabled"; 432 }; 433 434 avb: ethernet@e6800000 { 435 /* placeholder */ 436 }; 437 438 csi20: csi2@fea80000 { 439 /* placeholder */ 440 }; 441 442 csi40: csi2@feaa0000 { 443 /* placeholder */ 444 }; 445 446 vin0: video@e6ef0000 { 447 /* placeholder */ 448 }; 449 450 vin1: video@e6ef1000 { 451 /* placeholder */ 452 }; 453 454 vin2: video@e6ef2000 { 455 /* placeholder */ 456 }; 457 458 vin3: video@e6ef3000 { 459 /* placeholder */ 460 }; 461 462 vin4: video@e6ef4000 { 463 /* placeholder */ 464 }; 465 466 vin5: video@e6ef5000 { 467 /* placeholder */ 468 }; 469 470 vin6: video@e6ef6000 { 471 /* placeholder */ 472 }; 473 474 vin7: video@e6ef7000 { 475 /* placeholder */ 476 }; 477 478 ohci0: usb@ee080000 { 479 /* placeholder */ 480 }; 481 482 ehci0: usb@ee080100 { 483 /* placeholder */ 484 }; 485 486 usb2_phy0: usb-phy@ee080200 { 487 /* placeholder */ 488 }; 489 490 ohci1: usb@ee0a0000 { 491 /* placeholder */ 492 }; 493 494 ehci1: usb@ee0a0100 { 495 /* placeholder */ 496 }; 497 498 i2c0: i2c@e6500000 { 499 /* placeholder */ 500 }; 501 502 i2c1: i2c@e6508000 { 503 /* placeholder */ 504 }; 505 506 i2c2: i2c@e6510000 { 507 /* placeholder */ 508 }; 509 510 i2c3: i2c@e66d0000 { 511 /* placeholder */ 512 }; 513 514 i2c4: i2c@e66d8000 { 515 /* placeholder */ 516 }; 517 518 i2c5: i2c@e66e0000 { 519 /* placeholder */ 520 }; 521 522 i2c6: i2c@e66e8000 { 523 /* placeholder */ 524 }; 525 526 i2c_dvfs: i2c@e60b0000 { 527 /* placeholder */ 528 }; 529 530 pwm0: pwm@e6e30000 { 531 /* placeholder */ 532 }; 533 534 pwm1: pwm@e6e31000 { 535 /* placeholder */ 536 }; 537 538 pwm2: pwm@e6e32000 { 539 /* placeholder */ 540 }; 541 542 pwm3: pwm@e6e33000 { 543 /* placeholder */ 544 }; 545 546 pwm4: pwm@e6e34000 { 547 /* placeholder */ 548 }; 549 550 pwm5: pwm@e6e35000 { 551 /* placeholder */ 552 }; 553 554 pwm6: pwm@e6e36000 { 555 /* placeholder */ 556 }; 557 558 du: display@feb00000 { 559 /* placeholder */ 560 561 ports { 562 port@0 { 563 reg = <0>; 564 du_out_rgb: endpoint { 565 }; 566 }; 567 port@1 { 568 reg = <1>; 569 du_out_hdmi0: endpoint { 570 }; 571 }; 572 port@2 { 573 reg = <2>; 574 du_out_lvds0: endpoint { 575 }; 576 }; 577 }; 578 }; 579 580 hsusb: usb@e6590000 { 581 /* placeholder */ 582 }; 583 584 pciec0: pcie@fe000000 { 585 /* placeholder */ 586 }; 587 588 pciec1: pcie@ee800000 { 589 /* placeholder */ 590 }; 591 592 rcar_sound: sound@ec500000 { 593 /* placeholder */ 594 595 rcar_sound,dvc { 596 dvc0: dvc-0 { 597 }; 598 dvc1: dvc-1 { 599 }; 600 }; 601 602 rcar_sound,src { 603 src0: src-0 { 604 }; 605 src1: src-1 { 606 }; 607 }; 608 609 rcar_sound,ssi { 610 ssi0: ssi-0 { 611 }; 612 ssi1: ssi-1 { 613 }; 614 }; 615 }; 616 617 usb2_phy1: usb-phy@ee0a0200 { 618 /* placeholder */ 619 }; 620 621 sdhi0: sd@ee100000 { 622 /* placeholder */ 623 }; 624 625 sdhi1: sd@ee120000 { 626 /* placeholder */ 627 }; 628 629 sdhi2: sd@ee140000 { 630 /* placeholder */ 631 }; 632 633 sdhi3: sd@ee160000 { 634 /* placeholder */ 635 }; 636 637 usb3_phy0: usb-phy@e65ee000 { 638 /* placeholder */ 639 }; 640 641 usb3_peri0: usb@ee020000 { 642 /* placeholder */ 643 }; 644 645 xhci0: usb@ee000000 { 646 /* placeholder */ 647 }; 648 649 wdt0: watchdog@e6020000 { 650 /* placeholder */ 651 }; 652 }; 653}; 654