1d828266bSBiju Das// SPDX-License-Identifier: GPL-2.0 2d828266bSBiju Das/* 3d828266bSBiju Das * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) 4d828266bSBiju Das * 5d828266bSBiju Das * Copyright (C) 2019 Renesas Electronics Corp. 6d828266bSBiju Das */ 7d828266bSBiju Das 8d828266bSBiju Das/dts-v1/; 9d828266bSBiju Das#include "r8a774c0.dtsi" 10a102b93eSBiju Das#include <dt-bindings/gpio/gpio.h> 11d828266bSBiju Das 12d828266bSBiju Das/ { 13d828266bSBiju Das model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; 14d828266bSBiju Das compatible = "si-linux,cat874", "renesas,r8a774c0"; 15d828266bSBiju Das 16d828266bSBiju Das aliases { 17d828266bSBiju Das serial0 = &scif2; 18d828266bSBiju Das }; 19d828266bSBiju Das 20d828266bSBiju Das chosen { 21d828266bSBiju Das bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; 22d828266bSBiju Das stdout-path = "serial0:115200n8"; 23d828266bSBiju Das }; 24d828266bSBiju Das 25d828266bSBiju Das memory@48000000 { 26d828266bSBiju Das device_type = "memory"; 27d828266bSBiju Das /* first 128MB is reserved for secure area. */ 28d828266bSBiju Das reg = <0x0 0x48000000 0x0 0x78000000>; 29d828266bSBiju Das }; 30a102b93eSBiju Das 31a102b93eSBiju Das vcc_sdhi0: regulator-vcc-sdhi0 { 32a102b93eSBiju Das compatible = "regulator-fixed"; 33a102b93eSBiju Das 34a102b93eSBiju Das regulator-name = "SDHI0 Vcc"; 35a102b93eSBiju Das regulator-min-microvolt = <3300000>; 36a102b93eSBiju Das regulator-max-microvolt = <3300000>; 37a102b93eSBiju Das regulator-always-on; 38a102b93eSBiju Das regulator-boot-on; 39a102b93eSBiju Das }; 40a102b93eSBiju Das 41a102b93eSBiju Das vccq_sdhi0: regulator-vccq-sdhi0 { 42a102b93eSBiju Das compatible = "regulator-gpio"; 43a102b93eSBiju Das 44a102b93eSBiju Das regulator-name = "SDHI0 VccQ"; 45a102b93eSBiju Das regulator-min-microvolt = <1800000>; 46a102b93eSBiju Das regulator-max-microvolt = <3300000>; 47a102b93eSBiju Das 48a102b93eSBiju Das gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 49a102b93eSBiju Das gpios-states = <1>; 50a102b93eSBiju Das states = <3300000 1 51a102b93eSBiju Das 1800000 0>; 52a102b93eSBiju Das }; 53d828266bSBiju Das}; 54d828266bSBiju Das 55d828266bSBiju Das&extal_clk { 56d828266bSBiju Das clock-frequency = <48000000>; 57d828266bSBiju Das}; 58d828266bSBiju Das 59*aaf6c75cSBiju Das&pcie_bus_clk { 60*aaf6c75cSBiju Das clock-frequency = <100000000>; 61*aaf6c75cSBiju Das}; 62*aaf6c75cSBiju Das 63*aaf6c75cSBiju Das&pciec0 { 64*aaf6c75cSBiju Das /* Map all possible DDR as inbound ranges */ 65*aaf6c75cSBiju Das dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 66*aaf6c75cSBiju Das}; 67*aaf6c75cSBiju Das 684cf1f6ceSBiju Das&pfc { 694cf1f6ceSBiju Das scif2_pins: scif2 { 704cf1f6ceSBiju Das groups = "scif2_data_a"; 714cf1f6ceSBiju Das function = "scif2"; 724cf1f6ceSBiju Das }; 73a102b93eSBiju Das 74a102b93eSBiju Das sdhi0_pins: sd0 { 75a102b93eSBiju Das groups = "sdhi0_data4", "sdhi0_ctrl"; 76a102b93eSBiju Das function = "sdhi0"; 77a102b93eSBiju Das power-source = <3300>; 78a102b93eSBiju Das }; 79a102b93eSBiju Das 80a102b93eSBiju Das sdhi0_pins_uhs: sd0_uhs { 81a102b93eSBiju Das groups = "sdhi0_data4", "sdhi0_ctrl"; 82a102b93eSBiju Das function = "sdhi0"; 83a102b93eSBiju Das power-source = <1800>; 84a102b93eSBiju Das }; 854cf1f6ceSBiju Das}; 864cf1f6ceSBiju Das 87d828266bSBiju Das&scif2 { 884cf1f6ceSBiju Das pinctrl-0 = <&scif2_pins>; 894cf1f6ceSBiju Das pinctrl-names = "default"; 904cf1f6ceSBiju Das 91d828266bSBiju Das status = "okay"; 92d828266bSBiju Das}; 93a102b93eSBiju Das 94a102b93eSBiju Das&sdhi0 { 95a102b93eSBiju Das pinctrl-0 = <&sdhi0_pins>; 96a102b93eSBiju Das pinctrl-1 = <&sdhi0_pins_uhs>; 97a102b93eSBiju Das pinctrl-names = "default", "state_uhs"; 98a102b93eSBiju Das 99a102b93eSBiju Das vmmc-supply = <&vcc_sdhi0>; 100a102b93eSBiju Das vqmmc-supply = <&vccq_sdhi0>; 101a102b93eSBiju Das cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 102a102b93eSBiju Das bus-width = <4>; 103a102b93eSBiju Das sd-uhs-sdr50; 104a102b93eSBiju Das sd-uhs-sdr104; 105a102b93eSBiju Das status = "okay"; 106a102b93eSBiju Das}; 107