xref: /linux/scripts/dtc/include-prefixes/arm64/qcom/x1-hp-omnibook-x14.dtsi (revision 4f38da1f027ea2c9f01bb71daa7a299c191b6940)
1*72b50c2fSJens Glathe// SPDX-License-Identifier: BSD-3-Clause
2*72b50c2fSJens Glathe/*
3*72b50c2fSJens Glathe * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4*72b50c2fSJens Glathe * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com>
5*72b50c2fSJens Glathe */
6*72b50c2fSJens Glathe
7*72b50c2fSJens Glathe#include <dt-bindings/gpio/gpio.h>
8*72b50c2fSJens Glathe#include <dt-bindings/input/gpio-keys.h>
9*72b50c2fSJens Glathe#include <dt-bindings/input/input.h>
10*72b50c2fSJens Glathe#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11*72b50c2fSJens Glathe#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12*72b50c2fSJens Glathe
13*72b50c2fSJens Glathe/ {
14*72b50c2fSJens Glathe	aliases {
15*72b50c2fSJens Glathe		serial0 = &uart21;
16*72b50c2fSJens Glathe		serial1 = &uart14;
17*72b50c2fSJens Glathe	};
18*72b50c2fSJens Glathe
19*72b50c2fSJens Glathe	wcd938x: audio-codec {
20*72b50c2fSJens Glathe		compatible = "qcom,wcd9385-codec";
21*72b50c2fSJens Glathe
22*72b50c2fSJens Glathe		pinctrl-names = "default";
23*72b50c2fSJens Glathe		pinctrl-0 = <&wcd_default>;
24*72b50c2fSJens Glathe
25*72b50c2fSJens Glathe		qcom,micbias1-microvolt = <1800000>;
26*72b50c2fSJens Glathe		qcom,micbias2-microvolt = <1800000>;
27*72b50c2fSJens Glathe		qcom,micbias3-microvolt = <1800000>;
28*72b50c2fSJens Glathe		qcom,micbias4-microvolt = <1800000>;
29*72b50c2fSJens Glathe		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
30*72b50c2fSJens Glathe		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
31*72b50c2fSJens Glathe		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
32*72b50c2fSJens Glathe		qcom,rx-device = <&wcd_rx>;
33*72b50c2fSJens Glathe		qcom,tx-device = <&wcd_tx>;
34*72b50c2fSJens Glathe
35*72b50c2fSJens Glathe		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
36*72b50c2fSJens Glathe
37*72b50c2fSJens Glathe		vdd-buck-supply = <&vreg_l15b_1p8>;
38*72b50c2fSJens Glathe		vdd-rxtx-supply = <&vreg_l15b_1p8>;
39*72b50c2fSJens Glathe		vdd-io-supply = <&vreg_l15b_1p8>;
40*72b50c2fSJens Glathe		vdd-mic-bias-supply = <&vreg_bob1>;
41*72b50c2fSJens Glathe
42*72b50c2fSJens Glathe		#sound-dai-cells = <1>;
43*72b50c2fSJens Glathe	};
44*72b50c2fSJens Glathe
45*72b50c2fSJens Glathe	backlight: backlight {
46*72b50c2fSJens Glathe		compatible = "pwm-backlight";
47*72b50c2fSJens Glathe		pwms = <&pmk8550_pwm 0 5000000>;
48*72b50c2fSJens Glathe
49*72b50c2fSJens Glathe		brightness-levels = <0 2048 4096 8192 16384 65535>;
50*72b50c2fSJens Glathe		num-interpolated-steps = <20>;
51*72b50c2fSJens Glathe		default-brightness-level = <80>;
52*72b50c2fSJens Glathe
53*72b50c2fSJens Glathe		enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
54*72b50c2fSJens Glathe		power-supply = <&vreg_edp_bl>;
55*72b50c2fSJens Glathe
56*72b50c2fSJens Glathe		pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
57*72b50c2fSJens Glathe		pinctrl-names = "default";
58*72b50c2fSJens Glathe	};
59*72b50c2fSJens Glathe
60*72b50c2fSJens Glathe	gpio-keys {
61*72b50c2fSJens Glathe		compatible = "gpio-keys";
62*72b50c2fSJens Glathe
63*72b50c2fSJens Glathe		pinctrl-0 = <&hall_int_n_default>;
64*72b50c2fSJens Glathe		pinctrl-names = "default";
65*72b50c2fSJens Glathe
66*72b50c2fSJens Glathe		switch-lid {
67*72b50c2fSJens Glathe			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
68*72b50c2fSJens Glathe			linux,input-type = <EV_SW>;
69*72b50c2fSJens Glathe			linux,code = <SW_LID>;
70*72b50c2fSJens Glathe			wakeup-source;
71*72b50c2fSJens Glathe			wakeup-event-action = <EV_ACT_DEASSERTED>;
72*72b50c2fSJens Glathe		};
73*72b50c2fSJens Glathe	};
74*72b50c2fSJens Glathe
75*72b50c2fSJens Glathe	pmic-glink {
76*72b50c2fSJens Glathe		compatible = "qcom,x1e80100-pmic-glink",
77*72b50c2fSJens Glathe			     "qcom,sm8550-pmic-glink",
78*72b50c2fSJens Glathe			     "qcom,pmic-glink";
79*72b50c2fSJens Glathe		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
80*72b50c2fSJens Glathe				    <&tlmm 123 GPIO_ACTIVE_HIGH>;
81*72b50c2fSJens Glathe		#address-cells = <1>;
82*72b50c2fSJens Glathe		#size-cells = <0>;
83*72b50c2fSJens Glathe
84*72b50c2fSJens Glathe		/* Left-side port, closer to the screen */
85*72b50c2fSJens Glathe		connector@0 {
86*72b50c2fSJens Glathe			compatible = "usb-c-connector";
87*72b50c2fSJens Glathe			reg = <0>;
88*72b50c2fSJens Glathe			power-role = "dual";
89*72b50c2fSJens Glathe			data-role = "dual";
90*72b50c2fSJens Glathe
91*72b50c2fSJens Glathe			ports {
92*72b50c2fSJens Glathe				#address-cells = <1>;
93*72b50c2fSJens Glathe				#size-cells = <0>;
94*72b50c2fSJens Glathe
95*72b50c2fSJens Glathe				port@0 {
96*72b50c2fSJens Glathe					reg = <0>;
97*72b50c2fSJens Glathe
98*72b50c2fSJens Glathe					pmic_glink_ss0_hs_in: endpoint {
99*72b50c2fSJens Glathe						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
100*72b50c2fSJens Glathe					};
101*72b50c2fSJens Glathe				};
102*72b50c2fSJens Glathe
103*72b50c2fSJens Glathe				port@1 {
104*72b50c2fSJens Glathe					reg = <1>;
105*72b50c2fSJens Glathe
106*72b50c2fSJens Glathe					pmic_glink_ss0_ss_in: endpoint {
107*72b50c2fSJens Glathe						remote-endpoint = <&retimer_ss0_ss_out>;
108*72b50c2fSJens Glathe					};
109*72b50c2fSJens Glathe				};
110*72b50c2fSJens Glathe
111*72b50c2fSJens Glathe				port@2 {
112*72b50c2fSJens Glathe					reg = <2>;
113*72b50c2fSJens Glathe
114*72b50c2fSJens Glathe					pmic_glink_ss0_con_sbu_in: endpoint {
115*72b50c2fSJens Glathe						remote-endpoint = <&retimer_ss0_con_sbu_out>;
116*72b50c2fSJens Glathe					};
117*72b50c2fSJens Glathe				};
118*72b50c2fSJens Glathe			};
119*72b50c2fSJens Glathe		};
120*72b50c2fSJens Glathe
121*72b50c2fSJens Glathe		/* Left-side port, farther from the screen */
122*72b50c2fSJens Glathe		connector@1 {
123*72b50c2fSJens Glathe			compatible = "usb-c-connector";
124*72b50c2fSJens Glathe			reg = <1>;
125*72b50c2fSJens Glathe			power-role = "dual";
126*72b50c2fSJens Glathe			data-role = "dual";
127*72b50c2fSJens Glathe
128*72b50c2fSJens Glathe			ports {
129*72b50c2fSJens Glathe				#address-cells = <1>;
130*72b50c2fSJens Glathe				#size-cells = <0>;
131*72b50c2fSJens Glathe
132*72b50c2fSJens Glathe				port@0 {
133*72b50c2fSJens Glathe					reg = <0>;
134*72b50c2fSJens Glathe
135*72b50c2fSJens Glathe					pmic_glink_ss1_hs_in: endpoint {
136*72b50c2fSJens Glathe						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
137*72b50c2fSJens Glathe					};
138*72b50c2fSJens Glathe				};
139*72b50c2fSJens Glathe
140*72b50c2fSJens Glathe				port@1 {
141*72b50c2fSJens Glathe					reg = <1>;
142*72b50c2fSJens Glathe
143*72b50c2fSJens Glathe					pmic_glink_ss1_ss_in: endpoint {
144*72b50c2fSJens Glathe						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
145*72b50c2fSJens Glathe					};
146*72b50c2fSJens Glathe				};
147*72b50c2fSJens Glathe
148*72b50c2fSJens Glathe				port@2 {
149*72b50c2fSJens Glathe					reg = <2>;
150*72b50c2fSJens Glathe
151*72b50c2fSJens Glathe					pmic_glink_ss1_sbu: endpoint {
152*72b50c2fSJens Glathe						remote-endpoint = <&usb_1_ss1_sbu_mux>;
153*72b50c2fSJens Glathe					};
154*72b50c2fSJens Glathe				};
155*72b50c2fSJens Glathe			};
156*72b50c2fSJens Glathe		};
157*72b50c2fSJens Glathe	};
158*72b50c2fSJens Glathe
159*72b50c2fSJens Glathe	reserved-memory {
160*72b50c2fSJens Glathe		linux,cma {
161*72b50c2fSJens Glathe			compatible = "shared-dma-pool";
162*72b50c2fSJens Glathe			size = <0x0 0x8000000>;
163*72b50c2fSJens Glathe			reusable;
164*72b50c2fSJens Glathe			linux,cma-default;
165*72b50c2fSJens Glathe		};
166*72b50c2fSJens Glathe	};
167*72b50c2fSJens Glathe
168*72b50c2fSJens Glathe	sound: sound {
169*72b50c2fSJens Glathe		compatible = "qcom,x1e80100-sndcard";
170*72b50c2fSJens Glathe		model = "X1E80100-HP-OMNIBOOK-X14";
171*72b50c2fSJens Glathe		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
172*72b50c2fSJens Glathe				"SpkrRight IN", "WSA WSA_SPK2 OUT",
173*72b50c2fSJens Glathe				"IN1_HPHL", "HPHL_OUT",
174*72b50c2fSJens Glathe				"IN2_HPHR", "HPHR_OUT",
175*72b50c2fSJens Glathe				"AMIC2", "MIC BIAS2",
176*72b50c2fSJens Glathe				"VA DMIC0", "MIC BIAS3",
177*72b50c2fSJens Glathe				"VA DMIC1", "MIC BIAS3",
178*72b50c2fSJens Glathe				"VA DMIC2", "MIC BIAS1",
179*72b50c2fSJens Glathe				"VA DMIC3", "MIC BIAS1",
180*72b50c2fSJens Glathe				"VA DMIC0", "VA MIC BIAS3",
181*72b50c2fSJens Glathe				"VA DMIC1", "VA MIC BIAS3",
182*72b50c2fSJens Glathe				"VA DMIC2", "VA MIC BIAS1",
183*72b50c2fSJens Glathe				"VA DMIC3", "VA MIC BIAS1",
184*72b50c2fSJens Glathe				"TX SWR_INPUT1", "ADC2_OUTPUT";
185*72b50c2fSJens Glathe
186*72b50c2fSJens Glathe		wcd-playback-dai-link {
187*72b50c2fSJens Glathe			link-name = "WCD Playback";
188*72b50c2fSJens Glathe
189*72b50c2fSJens Glathe			cpu {
190*72b50c2fSJens Glathe				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
191*72b50c2fSJens Glathe			};
192*72b50c2fSJens Glathe
193*72b50c2fSJens Glathe			codec {
194*72b50c2fSJens Glathe				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
195*72b50c2fSJens Glathe			};
196*72b50c2fSJens Glathe
197*72b50c2fSJens Glathe			platform {
198*72b50c2fSJens Glathe				sound-dai = <&q6apm>;
199*72b50c2fSJens Glathe			};
200*72b50c2fSJens Glathe		};
201*72b50c2fSJens Glathe
202*72b50c2fSJens Glathe		wcd-capture-dai-link {
203*72b50c2fSJens Glathe			link-name = "WCD Capture";
204*72b50c2fSJens Glathe
205*72b50c2fSJens Glathe			cpu {
206*72b50c2fSJens Glathe				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
207*72b50c2fSJens Glathe			};
208*72b50c2fSJens Glathe
209*72b50c2fSJens Glathe			codec {
210*72b50c2fSJens Glathe				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
211*72b50c2fSJens Glathe			};
212*72b50c2fSJens Glathe
213*72b50c2fSJens Glathe			platform {
214*72b50c2fSJens Glathe				sound-dai = <&q6apm>;
215*72b50c2fSJens Glathe			};
216*72b50c2fSJens Glathe		};
217*72b50c2fSJens Glathe
218*72b50c2fSJens Glathe		wsa-dai-link {
219*72b50c2fSJens Glathe			link-name = "WSA Playback";
220*72b50c2fSJens Glathe
221*72b50c2fSJens Glathe			cpu {
222*72b50c2fSJens Glathe				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
223*72b50c2fSJens Glathe			};
224*72b50c2fSJens Glathe
225*72b50c2fSJens Glathe			codec {
226*72b50c2fSJens Glathe				sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
227*72b50c2fSJens Glathe			};
228*72b50c2fSJens Glathe
229*72b50c2fSJens Glathe			platform {
230*72b50c2fSJens Glathe				sound-dai = <&q6apm>;
231*72b50c2fSJens Glathe			};
232*72b50c2fSJens Glathe		};
233*72b50c2fSJens Glathe
234*72b50c2fSJens Glathe		va-dai-link {
235*72b50c2fSJens Glathe			link-name = "VA Capture";
236*72b50c2fSJens Glathe
237*72b50c2fSJens Glathe			cpu {
238*72b50c2fSJens Glathe				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
239*72b50c2fSJens Glathe			};
240*72b50c2fSJens Glathe
241*72b50c2fSJens Glathe			codec {
242*72b50c2fSJens Glathe				sound-dai = <&lpass_vamacro 0>;
243*72b50c2fSJens Glathe			};
244*72b50c2fSJens Glathe
245*72b50c2fSJens Glathe			platform {
246*72b50c2fSJens Glathe				sound-dai = <&q6apm>;
247*72b50c2fSJens Glathe			};
248*72b50c2fSJens Glathe		};
249*72b50c2fSJens Glathe	};
250*72b50c2fSJens Glathe
251*72b50c2fSJens Glathe	vreg_edp_3p3: regulator-edp-3p3 {
252*72b50c2fSJens Glathe		compatible = "regulator-fixed";
253*72b50c2fSJens Glathe
254*72b50c2fSJens Glathe		regulator-name = "VREG_EDP_3P3";
255*72b50c2fSJens Glathe		regulator-min-microvolt = <3300000>;
256*72b50c2fSJens Glathe		regulator-max-microvolt = <3300000>;
257*72b50c2fSJens Glathe
258*72b50c2fSJens Glathe		gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
259*72b50c2fSJens Glathe		enable-active-high;
260*72b50c2fSJens Glathe
261*72b50c2fSJens Glathe		pinctrl-0 = <&edp_reg_en>;
262*72b50c2fSJens Glathe		pinctrl-names = "default";
263*72b50c2fSJens Glathe
264*72b50c2fSJens Glathe		regulator-boot-on;
265*72b50c2fSJens Glathe	};
266*72b50c2fSJens Glathe
267*72b50c2fSJens Glathe	vreg_edp_bl: regulator-edp-bl {
268*72b50c2fSJens Glathe		compatible = "regulator-fixed";
269*72b50c2fSJens Glathe
270*72b50c2fSJens Glathe		regulator-name = "VBL9";
271*72b50c2fSJens Glathe		regulator-min-microvolt = <3600000>;
272*72b50c2fSJens Glathe		regulator-max-microvolt = <3600000>;
273*72b50c2fSJens Glathe
274*72b50c2fSJens Glathe		gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>;
275*72b50c2fSJens Glathe		enable-active-high;
276*72b50c2fSJens Glathe
277*72b50c2fSJens Glathe		pinctrl-names = "default";
278*72b50c2fSJens Glathe		pinctrl-0 = <&edp_bl_reg_en>;
279*72b50c2fSJens Glathe
280*72b50c2fSJens Glathe		regulator-boot-on;
281*72b50c2fSJens Glathe	};
282*72b50c2fSJens Glathe
283*72b50c2fSJens Glathe	vreg_misc_3p3: regulator-misc-3p3 {
284*72b50c2fSJens Glathe		compatible = "regulator-fixed";
285*72b50c2fSJens Glathe
286*72b50c2fSJens Glathe		regulator-name = "VREG_MISC_3P3";
287*72b50c2fSJens Glathe		regulator-min-microvolt = <3300000>;
288*72b50c2fSJens Glathe		regulator-max-microvolt = <3300000>;
289*72b50c2fSJens Glathe
290*72b50c2fSJens Glathe		gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
291*72b50c2fSJens Glathe		enable-active-high;
292*72b50c2fSJens Glathe
293*72b50c2fSJens Glathe		pinctrl-names = "default";
294*72b50c2fSJens Glathe		pinctrl-0 = <&misc_3p3_reg_en>;
295*72b50c2fSJens Glathe
296*72b50c2fSJens Glathe		regulator-boot-on;
297*72b50c2fSJens Glathe		regulator-always-on;
298*72b50c2fSJens Glathe	};
299*72b50c2fSJens Glathe
300*72b50c2fSJens Glathe	vreg_nvme: regulator-nvme {
301*72b50c2fSJens Glathe		compatible = "regulator-fixed";
302*72b50c2fSJens Glathe
303*72b50c2fSJens Glathe		regulator-name = "VREG_NVME_3P3";
304*72b50c2fSJens Glathe		regulator-min-microvolt = <3300000>;
305*72b50c2fSJens Glathe		regulator-max-microvolt = <3300000>;
306*72b50c2fSJens Glathe
307*72b50c2fSJens Glathe		gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
308*72b50c2fSJens Glathe		enable-active-high;
309*72b50c2fSJens Glathe
310*72b50c2fSJens Glathe		pinctrl-0 = <&nvme_reg_en>;
311*72b50c2fSJens Glathe		pinctrl-names = "default";
312*72b50c2fSJens Glathe
313*72b50c2fSJens Glathe		regulator-boot-on;
314*72b50c2fSJens Glathe	};
315*72b50c2fSJens Glathe
316*72b50c2fSJens Glathe	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
317*72b50c2fSJens Glathe		compatible = "regulator-fixed";
318*72b50c2fSJens Glathe
319*72b50c2fSJens Glathe		regulator-name = "VREG_RTMR0_1P15";
320*72b50c2fSJens Glathe		regulator-min-microvolt = <1150000>;
321*72b50c2fSJens Glathe		regulator-max-microvolt = <1150000>;
322*72b50c2fSJens Glathe
323*72b50c2fSJens Glathe		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
324*72b50c2fSJens Glathe		enable-active-high;
325*72b50c2fSJens Glathe
326*72b50c2fSJens Glathe		pinctrl-0 = <&usb0_pwr_1p15_reg_en>;
327*72b50c2fSJens Glathe		pinctrl-names = "default";
328*72b50c2fSJens Glathe
329*72b50c2fSJens Glathe		regulator-boot-on;
330*72b50c2fSJens Glathe	};
331*72b50c2fSJens Glathe
332*72b50c2fSJens Glathe	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
333*72b50c2fSJens Glathe		compatible = "regulator-fixed";
334*72b50c2fSJens Glathe
335*72b50c2fSJens Glathe		regulator-name = "VREG_RTMR0_1P8";
336*72b50c2fSJens Glathe		regulator-min-microvolt = <1800000>;
337*72b50c2fSJens Glathe		regulator-max-microvolt = <1800000>;
338*72b50c2fSJens Glathe
339*72b50c2fSJens Glathe		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
340*72b50c2fSJens Glathe		enable-active-high;
341*72b50c2fSJens Glathe
342*72b50c2fSJens Glathe		pinctrl-0 = <&usb0_1p8_reg_en>;
343*72b50c2fSJens Glathe		pinctrl-names = "default";
344*72b50c2fSJens Glathe
345*72b50c2fSJens Glathe		regulator-boot-on;
346*72b50c2fSJens Glathe	};
347*72b50c2fSJens Glathe
348*72b50c2fSJens Glathe	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
349*72b50c2fSJens Glathe		compatible = "regulator-fixed";
350*72b50c2fSJens Glathe
351*72b50c2fSJens Glathe		regulator-name = "VREG_RTMR0_3P3";
352*72b50c2fSJens Glathe		regulator-min-microvolt = <3300000>;
353*72b50c2fSJens Glathe		regulator-max-microvolt = <3300000>;
354*72b50c2fSJens Glathe
355*72b50c2fSJens Glathe		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
356*72b50c2fSJens Glathe		enable-active-high;
357*72b50c2fSJens Glathe
358*72b50c2fSJens Glathe		pinctrl-0 = <&usb0_3p3_reg_en>;
359*72b50c2fSJens Glathe		pinctrl-names = "default";
360*72b50c2fSJens Glathe
361*72b50c2fSJens Glathe		regulator-boot-on;
362*72b50c2fSJens Glathe	};
363*72b50c2fSJens Glathe
364*72b50c2fSJens Glathe	vreg_vph_pwr: regulator-vph-pwr {
365*72b50c2fSJens Glathe		compatible = "regulator-fixed";
366*72b50c2fSJens Glathe
367*72b50c2fSJens Glathe		regulator-name = "vreg_vph_pwr";
368*72b50c2fSJens Glathe		regulator-min-microvolt = <3700000>;
369*72b50c2fSJens Glathe		regulator-max-microvolt = <3700000>;
370*72b50c2fSJens Glathe
371*72b50c2fSJens Glathe		regulator-always-on;
372*72b50c2fSJens Glathe		regulator-boot-on;
373*72b50c2fSJens Glathe	};
374*72b50c2fSJens Glathe
375*72b50c2fSJens Glathe	vreg_wcn_3p3: regulator-wcn-3p3 {
376*72b50c2fSJens Glathe		compatible = "regulator-fixed";
377*72b50c2fSJens Glathe
378*72b50c2fSJens Glathe		regulator-name = "VREG_WCN_3P3";
379*72b50c2fSJens Glathe		regulator-min-microvolt = <3300000>;
380*72b50c2fSJens Glathe		regulator-max-microvolt = <3300000>;
381*72b50c2fSJens Glathe
382*72b50c2fSJens Glathe		gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>;
383*72b50c2fSJens Glathe		enable-active-high;
384*72b50c2fSJens Glathe
385*72b50c2fSJens Glathe		pinctrl-0 = <&wcn_sw_en>;
386*72b50c2fSJens Glathe		pinctrl-names = "default";
387*72b50c2fSJens Glathe
388*72b50c2fSJens Glathe		regulator-boot-on;
389*72b50c2fSJens Glathe	};
390*72b50c2fSJens Glathe
391*72b50c2fSJens Glathe	/*
392*72b50c2fSJens Glathe	 * TODO: These two regulators are actually part of the removable M.2
393*72b50c2fSJens Glathe	 * card and not the CRD mainboard. Need to describe this differently.
394*72b50c2fSJens Glathe	 * Functionally it works correctly, because all we need to do is to
395*72b50c2fSJens Glathe	 * turn on the actual 3.3V supply above.
396*72b50c2fSJens Glathe	 */
397*72b50c2fSJens Glathe	vreg_wcn_0p95: regulator-wcn-0p95 {
398*72b50c2fSJens Glathe		compatible = "regulator-fixed";
399*72b50c2fSJens Glathe
400*72b50c2fSJens Glathe		regulator-name = "VREG_WCN_0P95";
401*72b50c2fSJens Glathe		regulator-min-microvolt = <950000>;
402*72b50c2fSJens Glathe		regulator-max-microvolt = <950000>;
403*72b50c2fSJens Glathe
404*72b50c2fSJens Glathe		vin-supply = <&vreg_wcn_3p3>;
405*72b50c2fSJens Glathe	};
406*72b50c2fSJens Glathe
407*72b50c2fSJens Glathe	vreg_wcn_1p9: regulator-wcn-1p9 {
408*72b50c2fSJens Glathe		compatible = "regulator-fixed";
409*72b50c2fSJens Glathe
410*72b50c2fSJens Glathe		regulator-name = "VREG_WCN_1P9";
411*72b50c2fSJens Glathe		regulator-min-microvolt = <1900000>;
412*72b50c2fSJens Glathe		regulator-max-microvolt = <1900000>;
413*72b50c2fSJens Glathe
414*72b50c2fSJens Glathe		vin-supply = <&vreg_wcn_3p3>;
415*72b50c2fSJens Glathe	};
416*72b50c2fSJens Glathe
417*72b50c2fSJens Glathe	wcn6855-pmu {
418*72b50c2fSJens Glathe		compatible = "qcom,wcn6855-pmu";
419*72b50c2fSJens Glathe
420*72b50c2fSJens Glathe		vddaon-supply = <&vreg_wcn_0p95>;
421*72b50c2fSJens Glathe		vddio-supply = <&vreg_wcn_1p9>;
422*72b50c2fSJens Glathe		vddpcie1p3-supply = <&vreg_wcn_1p9>;
423*72b50c2fSJens Glathe		vddpcie1p9-supply = <&vreg_wcn_1p9>;
424*72b50c2fSJens Glathe		vddpmu-supply = <&vreg_wcn_0p95>;
425*72b50c2fSJens Glathe		vddpmumx-supply = <&vreg_wcn_0p95>;
426*72b50c2fSJens Glathe		vddpmucx-supply = <&vreg_wcn_0p95>;
427*72b50c2fSJens Glathe		vddrfa0p95-supply = <&vreg_wcn_0p95>;
428*72b50c2fSJens Glathe		vddrfa1p3-supply = <&vreg_wcn_1p9>;
429*72b50c2fSJens Glathe		vddrfa1p9-supply = <&vreg_wcn_1p9>;
430*72b50c2fSJens Glathe
431*72b50c2fSJens Glathe		wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
432*72b50c2fSJens Glathe		bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
433*72b50c2fSJens Glathe
434*72b50c2fSJens Glathe		pinctrl-0 = <&wcn_wlan_bt_en>;
435*72b50c2fSJens Glathe		pinctrl-names = "default";
436*72b50c2fSJens Glathe
437*72b50c2fSJens Glathe		regulators {
438*72b50c2fSJens Glathe			vreg_pmu_rfa_cmn_0p8: ldo0 {
439*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_rfa_cmn_0p8";
440*72b50c2fSJens Glathe			};
441*72b50c2fSJens Glathe
442*72b50c2fSJens Glathe			vreg_pmu_aon_0p8: ldo1 {
443*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_aon_0p8";
444*72b50c2fSJens Glathe			};
445*72b50c2fSJens Glathe
446*72b50c2fSJens Glathe			vreg_pmu_wlcx_0p8: ldo2 {
447*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_wlcx_0p8";
448*72b50c2fSJens Glathe			};
449*72b50c2fSJens Glathe
450*72b50c2fSJens Glathe			vreg_pmu_wlmx_0p8: ldo3 {
451*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_wlmx_0p8";
452*72b50c2fSJens Glathe			};
453*72b50c2fSJens Glathe
454*72b50c2fSJens Glathe			vreg_pmu_btcmx_0p8: ldo4 {
455*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_btcmx_0p8";
456*72b50c2fSJens Glathe			};
457*72b50c2fSJens Glathe
458*72b50c2fSJens Glathe			vreg_pmu_pcie_1p8: ldo5 {
459*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_pcie_1p8";
460*72b50c2fSJens Glathe			};
461*72b50c2fSJens Glathe
462*72b50c2fSJens Glathe			vreg_pmu_pcie_0p9: ldo6 {
463*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_pcie_0p9";
464*72b50c2fSJens Glathe			};
465*72b50c2fSJens Glathe
466*72b50c2fSJens Glathe			vreg_pmu_rfa_0p8: ldo7 {
467*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_rfa_0p8";
468*72b50c2fSJens Glathe			};
469*72b50c2fSJens Glathe
470*72b50c2fSJens Glathe			vreg_pmu_rfa_1p2: ldo8 {
471*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_rfa_1p2";
472*72b50c2fSJens Glathe			};
473*72b50c2fSJens Glathe
474*72b50c2fSJens Glathe			vreg_pmu_rfa_1p7: ldo9 {
475*72b50c2fSJens Glathe				regulator-name = "vreg_pmu_rfa_1p7";
476*72b50c2fSJens Glathe			};
477*72b50c2fSJens Glathe		};
478*72b50c2fSJens Glathe	};
479*72b50c2fSJens Glathe
480*72b50c2fSJens Glathe	usb-1-ss1-sbu-mux {
481*72b50c2fSJens Glathe		compatible = "onnn,fsusb42", "gpio-sbu-mux";
482*72b50c2fSJens Glathe
483*72b50c2fSJens Glathe		enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>;
484*72b50c2fSJens Glathe		select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>;
485*72b50c2fSJens Glathe
486*72b50c2fSJens Glathe		pinctrl-0 = <&usb_1_ss1_sbu_default>;
487*72b50c2fSJens Glathe		pinctrl-names = "default";
488*72b50c2fSJens Glathe
489*72b50c2fSJens Glathe		mode-switch;
490*72b50c2fSJens Glathe		orientation-switch;
491*72b50c2fSJens Glathe
492*72b50c2fSJens Glathe		port {
493*72b50c2fSJens Glathe			usb_1_ss1_sbu_mux: endpoint {
494*72b50c2fSJens Glathe				remote-endpoint = <&pmic_glink_ss1_sbu>;
495*72b50c2fSJens Glathe			};
496*72b50c2fSJens Glathe		};
497*72b50c2fSJens Glathe	};
498*72b50c2fSJens Glathe};
499*72b50c2fSJens Glathe
500*72b50c2fSJens Glathe&apps_rsc {
501*72b50c2fSJens Glathe	regulators-0 {
502*72b50c2fSJens Glathe		compatible = "qcom,pm8550-rpmh-regulators";
503*72b50c2fSJens Glathe		qcom,pmic-id = "b";
504*72b50c2fSJens Glathe
505*72b50c2fSJens Glathe		vdd-bob1-supply = <&vreg_vph_pwr>;
506*72b50c2fSJens Glathe		vdd-bob2-supply = <&vreg_vph_pwr>;
507*72b50c2fSJens Glathe		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
508*72b50c2fSJens Glathe		vdd-l2-l13-l14-supply = <&vreg_bob1>;
509*72b50c2fSJens Glathe		vdd-l5-l16-supply = <&vreg_bob1>;
510*72b50c2fSJens Glathe		vdd-l6-l7-supply = <&vreg_bob2>;
511*72b50c2fSJens Glathe		vdd-l8-l9-supply = <&vreg_bob1>;
512*72b50c2fSJens Glathe		vdd-l12-supply = <&vreg_s5j_1p2>;
513*72b50c2fSJens Glathe		vdd-l15-supply = <&vreg_s4c_1p8>;
514*72b50c2fSJens Glathe		vdd-l17-supply = <&vreg_bob2>;
515*72b50c2fSJens Glathe
516*72b50c2fSJens Glathe		vreg_bob1: bob1 {
517*72b50c2fSJens Glathe			regulator-name = "vreg_bob1";
518*72b50c2fSJens Glathe			regulator-min-microvolt = <3008000>;
519*72b50c2fSJens Glathe			regulator-max-microvolt = <3960000>;
520*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
521*72b50c2fSJens Glathe		};
522*72b50c2fSJens Glathe
523*72b50c2fSJens Glathe		vreg_bob2: bob2 {
524*72b50c2fSJens Glathe			regulator-name = "vreg_bob2";
525*72b50c2fSJens Glathe			regulator-min-microvolt = <2504000>;
526*72b50c2fSJens Glathe			regulator-max-microvolt = <3008000>;
527*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
528*72b50c2fSJens Glathe		};
529*72b50c2fSJens Glathe
530*72b50c2fSJens Glathe		vreg_l1b_1p8: ldo1 {
531*72b50c2fSJens Glathe			regulator-name = "vreg_l1b_1p8";
532*72b50c2fSJens Glathe			regulator-min-microvolt = <1800000>;
533*72b50c2fSJens Glathe			regulator-max-microvolt = <1800000>;
534*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
535*72b50c2fSJens Glathe		};
536*72b50c2fSJens Glathe
537*72b50c2fSJens Glathe		vreg_l2b_3p0: ldo2 {
538*72b50c2fSJens Glathe			regulator-name = "vreg_l2b_3p0";
539*72b50c2fSJens Glathe			regulator-min-microvolt = <3072000>;
540*72b50c2fSJens Glathe			regulator-max-microvolt = <3100000>;
541*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
542*72b50c2fSJens Glathe		};
543*72b50c2fSJens Glathe
544*72b50c2fSJens Glathe		vreg_l4b_1p8: ldo4 {
545*72b50c2fSJens Glathe			regulator-name = "vreg_l4b_1p8";
546*72b50c2fSJens Glathe			regulator-min-microvolt = <1800000>;
547*72b50c2fSJens Glathe			regulator-max-microvolt = <1800000>;
548*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
549*72b50c2fSJens Glathe		};
550*72b50c2fSJens Glathe
551*72b50c2fSJens Glathe		vreg_l5b_3p0: ldo5 {
552*72b50c2fSJens Glathe			regulator-name = "vreg_l5b_3p0";
553*72b50c2fSJens Glathe			regulator-min-microvolt = <3000000>;
554*72b50c2fSJens Glathe			regulator-max-microvolt = <3000000>;
555*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
556*72b50c2fSJens Glathe		};
557*72b50c2fSJens Glathe
558*72b50c2fSJens Glathe		vreg_l6b_1p8: ldo6 {
559*72b50c2fSJens Glathe			regulator-name = "vreg_l6b_1p8";
560*72b50c2fSJens Glathe			regulator-min-microvolt = <1800000>;
561*72b50c2fSJens Glathe			regulator-max-microvolt = <2960000>;
562*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
563*72b50c2fSJens Glathe		};
564*72b50c2fSJens Glathe
565*72b50c2fSJens Glathe		vreg_l7b_2p8: ldo7 {
566*72b50c2fSJens Glathe			regulator-name = "vreg_l7b_2p8";
567*72b50c2fSJens Glathe			regulator-min-microvolt = <2800000>;
568*72b50c2fSJens Glathe			regulator-max-microvolt = <2800000>;
569*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
570*72b50c2fSJens Glathe		};
571*72b50c2fSJens Glathe
572*72b50c2fSJens Glathe		vreg_l8b_3p0: ldo8 {
573*72b50c2fSJens Glathe			regulator-name = "vreg_l8b_3p0";
574*72b50c2fSJens Glathe			regulator-min-microvolt = <3072000>;
575*72b50c2fSJens Glathe			regulator-max-microvolt = <3072000>;
576*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
577*72b50c2fSJens Glathe		};
578*72b50c2fSJens Glathe
579*72b50c2fSJens Glathe		vreg_l9b_2p9: ldo9 {
580*72b50c2fSJens Glathe			regulator-name = "vreg_l9b_2p9";
581*72b50c2fSJens Glathe			regulator-min-microvolt = <2960000>;
582*72b50c2fSJens Glathe			regulator-max-microvolt = <2960000>;
583*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
584*72b50c2fSJens Glathe		};
585*72b50c2fSJens Glathe
586*72b50c2fSJens Glathe		vreg_l10b_1p8: ldo10 {
587*72b50c2fSJens Glathe			regulator-name = "vreg_l10b_1p8";
588*72b50c2fSJens Glathe			regulator-min-microvolt = <1800000>;
589*72b50c2fSJens Glathe			regulator-max-microvolt = <1800000>;
590*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
591*72b50c2fSJens Glathe		};
592*72b50c2fSJens Glathe
593*72b50c2fSJens Glathe		vreg_l12b_1p2: ldo12 {
594*72b50c2fSJens Glathe			regulator-name = "vreg_l12b_1p2";
595*72b50c2fSJens Glathe			regulator-min-microvolt = <1200000>;
596*72b50c2fSJens Glathe			regulator-max-microvolt = <1200000>;
597*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
598*72b50c2fSJens Glathe			regulator-always-on;
599*72b50c2fSJens Glathe		};
600*72b50c2fSJens Glathe
601*72b50c2fSJens Glathe		vreg_l13b_3p0: ldo13 {
602*72b50c2fSJens Glathe			regulator-name = "vreg_l13b_3p0";
603*72b50c2fSJens Glathe			regulator-min-microvolt = <3072000>;
604*72b50c2fSJens Glathe			regulator-max-microvolt = <3100000>;
605*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
606*72b50c2fSJens Glathe		};
607*72b50c2fSJens Glathe
608*72b50c2fSJens Glathe		vreg_l14b_3p0: ldo14 {
609*72b50c2fSJens Glathe			regulator-name = "vreg_l14b_3p0";
610*72b50c2fSJens Glathe			regulator-min-microvolt = <3072000>;
611*72b50c2fSJens Glathe			regulator-max-microvolt = <3072000>;
612*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
613*72b50c2fSJens Glathe		};
614*72b50c2fSJens Glathe
615*72b50c2fSJens Glathe		vreg_l15b_1p8: ldo15 {
616*72b50c2fSJens Glathe			regulator-name = "vreg_l15b_1p8";
617*72b50c2fSJens Glathe			regulator-min-microvolt = <1800000>;
618*72b50c2fSJens Glathe			regulator-max-microvolt = <1800000>;
619*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
620*72b50c2fSJens Glathe			regulator-always-on;
621*72b50c2fSJens Glathe		};
622*72b50c2fSJens Glathe
623*72b50c2fSJens Glathe		vreg_l16b_2p9: ldo16 {
624*72b50c2fSJens Glathe			regulator-name = "vreg_l16b_2p9";
625*72b50c2fSJens Glathe			regulator-min-microvolt = <2912000>;
626*72b50c2fSJens Glathe			regulator-max-microvolt = <2912000>;
627*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
628*72b50c2fSJens Glathe		};
629*72b50c2fSJens Glathe
630*72b50c2fSJens Glathe		vreg_l17b_2p5: ldo17 {
631*72b50c2fSJens Glathe			regulator-name = "vreg_l17b_2p5";
632*72b50c2fSJens Glathe			regulator-min-microvolt = <2504000>;
633*72b50c2fSJens Glathe			regulator-max-microvolt = <2504000>;
634*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
635*72b50c2fSJens Glathe		};
636*72b50c2fSJens Glathe	};
637*72b50c2fSJens Glathe
638*72b50c2fSJens Glathe	regulators-1 {
639*72b50c2fSJens Glathe		compatible = "qcom,pm8550ve-rpmh-regulators";
640*72b50c2fSJens Glathe		qcom,pmic-id = "c";
641*72b50c2fSJens Glathe
642*72b50c2fSJens Glathe		vdd-l1-supply = <&vreg_s5j_1p2>;
643*72b50c2fSJens Glathe		vdd-l2-supply = <&vreg_s1f_0p7>;
644*72b50c2fSJens Glathe		vdd-l3-supply = <&vreg_s1f_0p7>;
645*72b50c2fSJens Glathe		vdd-s4-supply = <&vreg_vph_pwr>;
646*72b50c2fSJens Glathe
647*72b50c2fSJens Glathe		vreg_s4c_1p8: smps4 {
648*72b50c2fSJens Glathe			regulator-name = "vreg_s4c_1p8";
649*72b50c2fSJens Glathe			regulator-min-microvolt = <1856000>;
650*72b50c2fSJens Glathe			regulator-max-microvolt = <2000000>;
651*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
652*72b50c2fSJens Glathe		};
653*72b50c2fSJens Glathe
654*72b50c2fSJens Glathe		vreg_l1c_1p2: ldo1 {
655*72b50c2fSJens Glathe			regulator-name = "vreg_l1c_1p2";
656*72b50c2fSJens Glathe			regulator-min-microvolt = <1200000>;
657*72b50c2fSJens Glathe			regulator-max-microvolt = <1200000>;
658*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
659*72b50c2fSJens Glathe		};
660*72b50c2fSJens Glathe
661*72b50c2fSJens Glathe		vreg_l2c_0p8: ldo2 {
662*72b50c2fSJens Glathe			regulator-name = "vreg_l2c_0p8";
663*72b50c2fSJens Glathe			regulator-min-microvolt = <880000>;
664*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
665*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
666*72b50c2fSJens Glathe		};
667*72b50c2fSJens Glathe
668*72b50c2fSJens Glathe		vreg_l3c_0p8: ldo3 {
669*72b50c2fSJens Glathe			regulator-name = "vreg_l3c_0p8";
670*72b50c2fSJens Glathe			regulator-min-microvolt = <880000>;
671*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
672*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
673*72b50c2fSJens Glathe		};
674*72b50c2fSJens Glathe	};
675*72b50c2fSJens Glathe
676*72b50c2fSJens Glathe	regulators-2 {
677*72b50c2fSJens Glathe		compatible = "qcom,pmc8380-rpmh-regulators";
678*72b50c2fSJens Glathe		qcom,pmic-id = "d";
679*72b50c2fSJens Glathe
680*72b50c2fSJens Glathe		vdd-l1-supply = <&vreg_s1f_0p7>;
681*72b50c2fSJens Glathe		vdd-l2-supply = <&vreg_s1f_0p7>;
682*72b50c2fSJens Glathe		vdd-l3-supply = <&vreg_s4c_1p8>;
683*72b50c2fSJens Glathe		vdd-s1-supply = <&vreg_vph_pwr>;
684*72b50c2fSJens Glathe
685*72b50c2fSJens Glathe		vreg_l1d_0p8: ldo1 {
686*72b50c2fSJens Glathe			regulator-name = "vreg_l1d_0p8";
687*72b50c2fSJens Glathe			regulator-min-microvolt = <880000>;
688*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
689*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
690*72b50c2fSJens Glathe		};
691*72b50c2fSJens Glathe
692*72b50c2fSJens Glathe		vreg_l2d_0p9: ldo2 {
693*72b50c2fSJens Glathe			regulator-name = "vreg_l2d_0p9";
694*72b50c2fSJens Glathe			regulator-min-microvolt = <912000>;
695*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
696*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
697*72b50c2fSJens Glathe		};
698*72b50c2fSJens Glathe
699*72b50c2fSJens Glathe		vreg_l3d_1p8: ldo3 {
700*72b50c2fSJens Glathe			regulator-name = "vreg_l3d_1p8";
701*72b50c2fSJens Glathe			regulator-min-microvolt = <1800000>;
702*72b50c2fSJens Glathe			regulator-max-microvolt = <1800000>;
703*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
704*72b50c2fSJens Glathe		};
705*72b50c2fSJens Glathe	};
706*72b50c2fSJens Glathe
707*72b50c2fSJens Glathe	regulators-3 {
708*72b50c2fSJens Glathe		compatible = "qcom,pmc8380-rpmh-regulators";
709*72b50c2fSJens Glathe		qcom,pmic-id = "e";
710*72b50c2fSJens Glathe
711*72b50c2fSJens Glathe		vdd-l2-supply = <&vreg_s1f_0p7>;
712*72b50c2fSJens Glathe		vdd-l3-supply = <&vreg_s5j_1p2>;
713*72b50c2fSJens Glathe
714*72b50c2fSJens Glathe		vreg_l2e_0p8: ldo2 {
715*72b50c2fSJens Glathe			regulator-name = "vreg_l2e_0p8";
716*72b50c2fSJens Glathe			regulator-min-microvolt = <880000>;
717*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
718*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
719*72b50c2fSJens Glathe		};
720*72b50c2fSJens Glathe
721*72b50c2fSJens Glathe		vreg_l3e_1p2: ldo3 {
722*72b50c2fSJens Glathe			regulator-name = "vreg_l3e_1p2";
723*72b50c2fSJens Glathe			regulator-min-microvolt = <1200000>;
724*72b50c2fSJens Glathe			regulator-max-microvolt = <1200000>;
725*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
726*72b50c2fSJens Glathe		};
727*72b50c2fSJens Glathe	};
728*72b50c2fSJens Glathe
729*72b50c2fSJens Glathe	regulators-4 {
730*72b50c2fSJens Glathe		compatible = "qcom,pmc8380-rpmh-regulators";
731*72b50c2fSJens Glathe		qcom,pmic-id = "f";
732*72b50c2fSJens Glathe
733*72b50c2fSJens Glathe		vdd-l1-supply = <&vreg_s5j_1p2>;
734*72b50c2fSJens Glathe		vdd-l2-supply = <&vreg_s5j_1p2>;
735*72b50c2fSJens Glathe		vdd-l3-supply = <&vreg_s5j_1p2>;
736*72b50c2fSJens Glathe		vdd-s1-supply = <&vreg_vph_pwr>;
737*72b50c2fSJens Glathe
738*72b50c2fSJens Glathe		vreg_s1f_0p7: smps1 {
739*72b50c2fSJens Glathe			regulator-name = "vreg_s1f_0p7";
740*72b50c2fSJens Glathe			regulator-min-microvolt = <700000>;
741*72b50c2fSJens Glathe			regulator-max-microvolt = <1100000>;
742*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
743*72b50c2fSJens Glathe		};
744*72b50c2fSJens Glathe
745*72b50c2fSJens Glathe		vreg_l1f_1p0: ldo1 {
746*72b50c2fSJens Glathe			regulator-name = "vreg_l1f_1p0";
747*72b50c2fSJens Glathe			regulator-min-microvolt = <1024000>;
748*72b50c2fSJens Glathe			regulator-max-microvolt = <1024000>;
749*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
750*72b50c2fSJens Glathe		};
751*72b50c2fSJens Glathe
752*72b50c2fSJens Glathe		vreg_l2f_1p0: ldo2 {
753*72b50c2fSJens Glathe			regulator-name = "vreg_l2f_1p0";
754*72b50c2fSJens Glathe			regulator-min-microvolt = <1024000>;
755*72b50c2fSJens Glathe			regulator-max-microvolt = <1024000>;
756*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
757*72b50c2fSJens Glathe		};
758*72b50c2fSJens Glathe
759*72b50c2fSJens Glathe		vreg_l3f_1p0: ldo3 {
760*72b50c2fSJens Glathe			regulator-name = "vreg_l3f_1p0";
761*72b50c2fSJens Glathe			regulator-min-microvolt = <1024000>;
762*72b50c2fSJens Glathe			regulator-max-microvolt = <1024000>;
763*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
764*72b50c2fSJens Glathe		};
765*72b50c2fSJens Glathe	};
766*72b50c2fSJens Glathe
767*72b50c2fSJens Glathe	regulators-6 {
768*72b50c2fSJens Glathe		compatible = "qcom,pm8550ve-rpmh-regulators";
769*72b50c2fSJens Glathe		qcom,pmic-id = "i";
770*72b50c2fSJens Glathe
771*72b50c2fSJens Glathe		vdd-l1-supply = <&vreg_s4c_1p8>;
772*72b50c2fSJens Glathe		vdd-l2-supply = <&vreg_s5j_1p2>;
773*72b50c2fSJens Glathe		vdd-l3-supply = <&vreg_s1f_0p7>;
774*72b50c2fSJens Glathe		vdd-s1-supply = <&vreg_vph_pwr>;
775*72b50c2fSJens Glathe		vdd-s2-supply = <&vreg_vph_pwr>;
776*72b50c2fSJens Glathe
777*72b50c2fSJens Glathe		vreg_s1i_0p9: smps1 {
778*72b50c2fSJens Glathe			regulator-name = "vreg_s1i_0p9";
779*72b50c2fSJens Glathe			regulator-min-microvolt = <900000>;
780*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
781*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
782*72b50c2fSJens Glathe		};
783*72b50c2fSJens Glathe
784*72b50c2fSJens Glathe		vreg_s2i_1p0: smps2 {
785*72b50c2fSJens Glathe			regulator-name = "vreg_s2i_1p0";
786*72b50c2fSJens Glathe			regulator-min-microvolt = <1000000>;
787*72b50c2fSJens Glathe			regulator-max-microvolt = <1100000>;
788*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
789*72b50c2fSJens Glathe		};
790*72b50c2fSJens Glathe
791*72b50c2fSJens Glathe		vreg_l1i_1p8: ldo1 {
792*72b50c2fSJens Glathe			regulator-name = "vreg_l1i_1p8";
793*72b50c2fSJens Glathe			regulator-min-microvolt = <1800000>;
794*72b50c2fSJens Glathe			regulator-max-microvolt = <1800000>;
795*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
796*72b50c2fSJens Glathe		};
797*72b50c2fSJens Glathe
798*72b50c2fSJens Glathe		vreg_l2i_1p2: ldo2 {
799*72b50c2fSJens Glathe			regulator-name = "vreg_l2i_1p2";
800*72b50c2fSJens Glathe			regulator-min-microvolt = <1200000>;
801*72b50c2fSJens Glathe			regulator-max-microvolt = <1200000>;
802*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
803*72b50c2fSJens Glathe		};
804*72b50c2fSJens Glathe
805*72b50c2fSJens Glathe		vreg_l3i_0p8: ldo3 {
806*72b50c2fSJens Glathe			regulator-name = "vreg_l3i_0p8";
807*72b50c2fSJens Glathe			regulator-min-microvolt = <880000>;
808*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
809*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
810*72b50c2fSJens Glathe		};
811*72b50c2fSJens Glathe	};
812*72b50c2fSJens Glathe
813*72b50c2fSJens Glathe	regulators-7 {
814*72b50c2fSJens Glathe		compatible = "qcom,pm8550ve-rpmh-regulators";
815*72b50c2fSJens Glathe		qcom,pmic-id = "j";
816*72b50c2fSJens Glathe
817*72b50c2fSJens Glathe		vdd-l1-supply = <&vreg_s1f_0p7>;
818*72b50c2fSJens Glathe		vdd-l2-supply = <&vreg_s5j_1p2>;
819*72b50c2fSJens Glathe		vdd-l3-supply = <&vreg_s1f_0p7>;
820*72b50c2fSJens Glathe		vdd-s5-supply = <&vreg_vph_pwr>;
821*72b50c2fSJens Glathe
822*72b50c2fSJens Glathe		vreg_s5j_1p2: smps5 {
823*72b50c2fSJens Glathe			regulator-name = "vreg_s5j_1p2";
824*72b50c2fSJens Glathe			regulator-min-microvolt = <1256000>;
825*72b50c2fSJens Glathe			regulator-max-microvolt = <1304000>;
826*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
827*72b50c2fSJens Glathe		};
828*72b50c2fSJens Glathe
829*72b50c2fSJens Glathe		vreg_l1j_0p8: ldo1 {
830*72b50c2fSJens Glathe			regulator-name = "vreg_l1j_0p8";
831*72b50c2fSJens Glathe			regulator-min-microvolt = <880000>;
832*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
833*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
834*72b50c2fSJens Glathe		};
835*72b50c2fSJens Glathe
836*72b50c2fSJens Glathe		vreg_l2j_1p2: ldo2 {
837*72b50c2fSJens Glathe			regulator-name = "vreg_l2j_1p2";
838*72b50c2fSJens Glathe			regulator-min-microvolt = <1256000>;
839*72b50c2fSJens Glathe			regulator-max-microvolt = <1256000>;
840*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
841*72b50c2fSJens Glathe		};
842*72b50c2fSJens Glathe
843*72b50c2fSJens Glathe		vreg_l3j_0p8: ldo3 {
844*72b50c2fSJens Glathe			regulator-name = "vreg_l3j_0p8";
845*72b50c2fSJens Glathe			regulator-min-microvolt = <880000>;
846*72b50c2fSJens Glathe			regulator-max-microvolt = <920000>;
847*72b50c2fSJens Glathe			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
848*72b50c2fSJens Glathe		};
849*72b50c2fSJens Glathe	};
850*72b50c2fSJens Glathe};
851*72b50c2fSJens Glathe
852*72b50c2fSJens Glathe&gpu {
853*72b50c2fSJens Glathe	status = "okay";
854*72b50c2fSJens Glathe};
855*72b50c2fSJens Glathe
856*72b50c2fSJens Glathe&i2c0 {
857*72b50c2fSJens Glathe	clock-frequency = <400000>;
858*72b50c2fSJens Glathe
859*72b50c2fSJens Glathe	status = "okay";
860*72b50c2fSJens Glathe
861*72b50c2fSJens Glathe	keyboard@3a {
862*72b50c2fSJens Glathe		compatible = "hid-over-i2c";
863*72b50c2fSJens Glathe		reg = <0x3a>;
864*72b50c2fSJens Glathe
865*72b50c2fSJens Glathe		hid-descr-addr = <0x1>;
866*72b50c2fSJens Glathe		interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
867*72b50c2fSJens Glathe
868*72b50c2fSJens Glathe		vdd-supply = <&vreg_misc_3p3>;
869*72b50c2fSJens Glathe		vddl-supply = <&vreg_l12b_1p2>;
870*72b50c2fSJens Glathe
871*72b50c2fSJens Glathe		pinctrl-0 = <&kybd_default>;
872*72b50c2fSJens Glathe		pinctrl-names = "default";
873*72b50c2fSJens Glathe
874*72b50c2fSJens Glathe		wakeup-source;
875*72b50c2fSJens Glathe	};
876*72b50c2fSJens Glathe
877*72b50c2fSJens Glathe	touchpad@15 {
878*72b50c2fSJens Glathe		compatible = "hid-over-i2c";
879*72b50c2fSJens Glathe		reg = <0x15>;
880*72b50c2fSJens Glathe
881*72b50c2fSJens Glathe		hid-descr-addr = <0x1>;
882*72b50c2fSJens Glathe		interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
883*72b50c2fSJens Glathe
884*72b50c2fSJens Glathe		vdd-supply = <&vreg_misc_3p3>;
885*72b50c2fSJens Glathe		vddl-supply = <&vreg_l12b_1p2>;
886*72b50c2fSJens Glathe
887*72b50c2fSJens Glathe		pinctrl-0 = <&tpad_default>;
888*72b50c2fSJens Glathe		pinctrl-names = "default";
889*72b50c2fSJens Glathe
890*72b50c2fSJens Glathe		wakeup-source;
891*72b50c2fSJens Glathe	};
892*72b50c2fSJens Glathe};
893*72b50c2fSJens Glathe
894*72b50c2fSJens Glathe&i2c3 {
895*72b50c2fSJens Glathe	clock-frequency = <400000>;
896*72b50c2fSJens Glathe
897*72b50c2fSJens Glathe	status = "okay";
898*72b50c2fSJens Glathe
899*72b50c2fSJens Glathe	typec-mux@8 {
900*72b50c2fSJens Glathe		compatible = "parade,ps8830";
901*72b50c2fSJens Glathe		reg = <0x08>;
902*72b50c2fSJens Glathe
903*72b50c2fSJens Glathe		clocks = <&rpmhcc RPMH_RF_CLK3>;
904*72b50c2fSJens Glathe
905*72b50c2fSJens Glathe		vdd-supply = <&vreg_rtmr0_1p15>;
906*72b50c2fSJens Glathe		vdd33-supply = <&vreg_rtmr0_3p3>;
907*72b50c2fSJens Glathe		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
908*72b50c2fSJens Glathe		vddar-supply = <&vreg_rtmr0_1p15>;
909*72b50c2fSJens Glathe		vddat-supply = <&vreg_rtmr0_1p15>;
910*72b50c2fSJens Glathe		vddio-supply = <&vreg_rtmr0_1p8>;
911*72b50c2fSJens Glathe
912*72b50c2fSJens Glathe		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
913*72b50c2fSJens Glathe
914*72b50c2fSJens Glathe		pinctrl-0 = <&rtmr0_default>;
915*72b50c2fSJens Glathe		pinctrl-names = "default";
916*72b50c2fSJens Glathe
917*72b50c2fSJens Glathe		orientation-switch;
918*72b50c2fSJens Glathe		retimer-switch;
919*72b50c2fSJens Glathe
920*72b50c2fSJens Glathe		ports {
921*72b50c2fSJens Glathe			#address-cells = <1>;
922*72b50c2fSJens Glathe			#size-cells = <0>;
923*72b50c2fSJens Glathe
924*72b50c2fSJens Glathe			port@0 {
925*72b50c2fSJens Glathe				reg = <0>;
926*72b50c2fSJens Glathe
927*72b50c2fSJens Glathe				retimer_ss0_ss_out: endpoint {
928*72b50c2fSJens Glathe					remote-endpoint = <&pmic_glink_ss0_ss_in>;
929*72b50c2fSJens Glathe				};
930*72b50c2fSJens Glathe			};
931*72b50c2fSJens Glathe
932*72b50c2fSJens Glathe			port@1 {
933*72b50c2fSJens Glathe				reg = <1>;
934*72b50c2fSJens Glathe
935*72b50c2fSJens Glathe				retimer_ss0_ss_in: endpoint {
936*72b50c2fSJens Glathe					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
937*72b50c2fSJens Glathe				};
938*72b50c2fSJens Glathe			};
939*72b50c2fSJens Glathe
940*72b50c2fSJens Glathe			port@2 {
941*72b50c2fSJens Glathe				reg = <2>;
942*72b50c2fSJens Glathe
943*72b50c2fSJens Glathe				retimer_ss0_con_sbu_out: endpoint {
944*72b50c2fSJens Glathe					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
945*72b50c2fSJens Glathe				};
946*72b50c2fSJens Glathe			};
947*72b50c2fSJens Glathe		};
948*72b50c2fSJens Glathe	};
949*72b50c2fSJens Glathe};
950*72b50c2fSJens Glathe
951*72b50c2fSJens Glathe&i2c5 {
952*72b50c2fSJens Glathe	clock-frequency = <400000>;
953*72b50c2fSJens Glathe	status = "okay";
954*72b50c2fSJens Glathe
955*72b50c2fSJens Glathe	eusb3_repeater: redriver@47 {
956*72b50c2fSJens Glathe		compatible = "nxp,ptn3222";
957*72b50c2fSJens Glathe		reg = <0x47>;
958*72b50c2fSJens Glathe		#phy-cells = <0>;
959*72b50c2fSJens Glathe
960*72b50c2fSJens Glathe		vdd3v3-supply = <&vreg_l13b_3p0>;
961*72b50c2fSJens Glathe		vdd1v8-supply = <&vreg_l4b_1p8>;
962*72b50c2fSJens Glathe
963*72b50c2fSJens Glathe		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
964*72b50c2fSJens Glathe
965*72b50c2fSJens Glathe		pinctrl-0 = <&eusb3_reset_n>;
966*72b50c2fSJens Glathe		pinctrl-names = "default";
967*72b50c2fSJens Glathe
968*72b50c2fSJens Glathe	};
969*72b50c2fSJens Glathe};
970*72b50c2fSJens Glathe
971*72b50c2fSJens Glathe&i2c8 {
972*72b50c2fSJens Glathe	clock-frequency = <400000>;
973*72b50c2fSJens Glathe
974*72b50c2fSJens Glathe	status = "okay";
975*72b50c2fSJens Glathe
976*72b50c2fSJens Glathe	touchscreen@10 {
977*72b50c2fSJens Glathe		compatible = "hid-over-i2c";
978*72b50c2fSJens Glathe		reg = <0x10>;
979*72b50c2fSJens Glathe
980*72b50c2fSJens Glathe		hid-descr-addr = <0x1>;
981*72b50c2fSJens Glathe		interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
982*72b50c2fSJens Glathe
983*72b50c2fSJens Glathe		vdd-supply = <&vreg_misc_3p3>;
984*72b50c2fSJens Glathe		vddl-supply = <&vreg_l15b_1p8>;
985*72b50c2fSJens Glathe
986*72b50c2fSJens Glathe		pinctrl-0 = <&ts0_default>;
987*72b50c2fSJens Glathe		pinctrl-names = "default";
988*72b50c2fSJens Glathe	};
989*72b50c2fSJens Glathe};
990*72b50c2fSJens Glathe
991*72b50c2fSJens Glathe&lpass_tlmm {
992*72b50c2fSJens Glathe	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
993*72b50c2fSJens Glathe		pins = "gpio12";
994*72b50c2fSJens Glathe		function = "gpio";
995*72b50c2fSJens Glathe		drive-strength = <16>;
996*72b50c2fSJens Glathe		bias-disable;
997*72b50c2fSJens Glathe		output-low;
998*72b50c2fSJens Glathe	};
999*72b50c2fSJens Glathe};
1000*72b50c2fSJens Glathe
1001*72b50c2fSJens Glathe&lpass_vamacro {
1002*72b50c2fSJens Glathe	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
1003*72b50c2fSJens Glathe	pinctrl-names = "default";
1004*72b50c2fSJens Glathe
1005*72b50c2fSJens Glathe	vdd-micb-supply = <&vreg_l1b_1p8>;
1006*72b50c2fSJens Glathe	qcom,dmic-sample-rate = <4800000>;
1007*72b50c2fSJens Glathe};
1008*72b50c2fSJens Glathe
1009*72b50c2fSJens Glathe&mdss {
1010*72b50c2fSJens Glathe	status = "okay";
1011*72b50c2fSJens Glathe};
1012*72b50c2fSJens Glathe
1013*72b50c2fSJens Glathe&mdss_dp0 {
1014*72b50c2fSJens Glathe	status = "okay";
1015*72b50c2fSJens Glathe};
1016*72b50c2fSJens Glathe
1017*72b50c2fSJens Glathe&mdss_dp0_out {
1018*72b50c2fSJens Glathe	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
1019*72b50c2fSJens Glathe};
1020*72b50c2fSJens Glathe
1021*72b50c2fSJens Glathe&mdss_dp1 {
1022*72b50c2fSJens Glathe	status = "okay";
1023*72b50c2fSJens Glathe};
1024*72b50c2fSJens Glathe
1025*72b50c2fSJens Glathe&mdss_dp1_out {
1026*72b50c2fSJens Glathe	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
1027*72b50c2fSJens Glathe};
1028*72b50c2fSJens Glathe
1029*72b50c2fSJens Glathe&mdss_dp3 {
1030*72b50c2fSJens Glathe	/delete-property/ #sound-dai-cells;
1031*72b50c2fSJens Glathe
1032*72b50c2fSJens Glathe	pinctrl-0 = <&edp0_hpd_default>;
1033*72b50c2fSJens Glathe	pinctrl-names = "default";
1034*72b50c2fSJens Glathe
1035*72b50c2fSJens Glathe	status = "okay";
1036*72b50c2fSJens Glathe
1037*72b50c2fSJens Glathe	aux-bus {
1038*72b50c2fSJens Glathe		panel {
1039*72b50c2fSJens Glathe			compatible = "edp-panel";
1040*72b50c2fSJens Glathe			power-supply = <&vreg_edp_3p3>;
1041*72b50c2fSJens Glathe
1042*72b50c2fSJens Glathe			backlight = <&backlight>;
1043*72b50c2fSJens Glathe
1044*72b50c2fSJens Glathe			port {
1045*72b50c2fSJens Glathe				edp_panel_in: endpoint {
1046*72b50c2fSJens Glathe					remote-endpoint = <&mdss_dp3_out>;
1047*72b50c2fSJens Glathe				};
1048*72b50c2fSJens Glathe			};
1049*72b50c2fSJens Glathe		};
1050*72b50c2fSJens Glathe	};
1051*72b50c2fSJens Glathe};
1052*72b50c2fSJens Glathe
1053*72b50c2fSJens Glathe&mdss_dp3_out {
1054*72b50c2fSJens Glathe	data-lanes = <0 1 2 3>;
1055*72b50c2fSJens Glathe	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
1056*72b50c2fSJens Glathe
1057*72b50c2fSJens Glathe	remote-endpoint = <&edp_panel_in>;
1058*72b50c2fSJens Glathe};
1059*72b50c2fSJens Glathe
1060*72b50c2fSJens Glathe&mdss_dp3_phy {
1061*72b50c2fSJens Glathe	vdda-phy-supply = <&vreg_l3j_0p8>;
1062*72b50c2fSJens Glathe	vdda-pll-supply = <&vreg_l2j_1p2>;
1063*72b50c2fSJens Glathe
1064*72b50c2fSJens Glathe	status = "okay";
1065*72b50c2fSJens Glathe};
1066*72b50c2fSJens Glathe
1067*72b50c2fSJens Glathe&pcie4 {
1068*72b50c2fSJens Glathe	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1069*72b50c2fSJens Glathe	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1070*72b50c2fSJens Glathe
1071*72b50c2fSJens Glathe	pinctrl-0 = <&pcie4_default>;
1072*72b50c2fSJens Glathe	pinctrl-names = "default";
1073*72b50c2fSJens Glathe
1074*72b50c2fSJens Glathe	status = "okay";
1075*72b50c2fSJens Glathe};
1076*72b50c2fSJens Glathe
1077*72b50c2fSJens Glathe&pcie4_phy {
1078*72b50c2fSJens Glathe	vdda-phy-supply = <&vreg_l3i_0p8>;
1079*72b50c2fSJens Glathe	vdda-pll-supply = <&vreg_l3e_1p2>;
1080*72b50c2fSJens Glathe
1081*72b50c2fSJens Glathe	status = "okay";
1082*72b50c2fSJens Glathe};
1083*72b50c2fSJens Glathe
1084*72b50c2fSJens Glathe&pcie4_port0 {
1085*72b50c2fSJens Glathe	wifi@0 {
1086*72b50c2fSJens Glathe		compatible = "pci17cb,1107";
1087*72b50c2fSJens Glathe		reg = <0x10000 0x0 0x0 0x0 0x0>;
1088*72b50c2fSJens Glathe
1089*72b50c2fSJens Glathe		vddaon-supply = <&vreg_pmu_aon_0p8>;
1090*72b50c2fSJens Glathe		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
1091*72b50c2fSJens Glathe		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
1092*72b50c2fSJens Glathe		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
1093*72b50c2fSJens Glathe		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
1094*72b50c2fSJens Glathe		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
1095*72b50c2fSJens Glathe		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
1096*72b50c2fSJens Glathe		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
1097*72b50c2fSJens Glathe		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
1098*72b50c2fSJens Glathe	};
1099*72b50c2fSJens Glathe};
1100*72b50c2fSJens Glathe
1101*72b50c2fSJens Glathe&pcie6a {
1102*72b50c2fSJens Glathe	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1103*72b50c2fSJens Glathe	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1104*72b50c2fSJens Glathe
1105*72b50c2fSJens Glathe	vddpe-3v3-supply = <&vreg_nvme>;
1106*72b50c2fSJens Glathe
1107*72b50c2fSJens Glathe	pinctrl-0 = <&pcie6a_default>;
1108*72b50c2fSJens Glathe	pinctrl-names = "default";
1109*72b50c2fSJens Glathe
1110*72b50c2fSJens Glathe	status = "okay";
1111*72b50c2fSJens Glathe};
1112*72b50c2fSJens Glathe
1113*72b50c2fSJens Glathe&pcie6a_phy {
1114*72b50c2fSJens Glathe	vdda-phy-supply = <&vreg_l1d_0p8>;
1115*72b50c2fSJens Glathe	vdda-pll-supply = <&vreg_l2j_1p2>;
1116*72b50c2fSJens Glathe
1117*72b50c2fSJens Glathe	status = "okay";
1118*72b50c2fSJens Glathe};
1119*72b50c2fSJens Glathe
1120*72b50c2fSJens Glathe&pm8550_gpios {
1121*72b50c2fSJens Glathe	rtmr0_default: rtmr0-reset-n-active-state {
1122*72b50c2fSJens Glathe		pins = "gpio10";
1123*72b50c2fSJens Glathe		function = "normal";
1124*72b50c2fSJens Glathe		power-source = <1>; /* 1.8V */
1125*72b50c2fSJens Glathe		bias-disable;
1126*72b50c2fSJens Glathe		input-disable;
1127*72b50c2fSJens Glathe		output-enable;
1128*72b50c2fSJens Glathe	};
1129*72b50c2fSJens Glathe
1130*72b50c2fSJens Glathe	usb0_3p3_reg_en: usb0-3p3-reg-en-state {
1131*72b50c2fSJens Glathe		pins = "gpio11";
1132*72b50c2fSJens Glathe		function = "normal";
1133*72b50c2fSJens Glathe		power-source = <1>; /* 1.8V */
1134*72b50c2fSJens Glathe		bias-disable;
1135*72b50c2fSJens Glathe		input-disable;
1136*72b50c2fSJens Glathe		output-enable;
1137*72b50c2fSJens Glathe	};
1138*72b50c2fSJens Glathe};
1139*72b50c2fSJens Glathe
1140*72b50c2fSJens Glathe&pm8550ve_8_gpios {
1141*72b50c2fSJens Glathe	misc_3p3_reg_en: misc-3p3-reg-en-state {
1142*72b50c2fSJens Glathe		pins = "gpio6";
1143*72b50c2fSJens Glathe		function = "normal";
1144*72b50c2fSJens Glathe		bias-disable;
1145*72b50c2fSJens Glathe		drive-push-pull;
1146*72b50c2fSJens Glathe		input-disable;
1147*72b50c2fSJens Glathe		output-enable;
1148*72b50c2fSJens Glathe		power-source = <1>; /* 1.8 V */
1149*72b50c2fSJens Glathe		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
1150*72b50c2fSJens Glathe	};
1151*72b50c2fSJens Glathe};
1152*72b50c2fSJens Glathe
1153*72b50c2fSJens Glathe&pm8550ve_9_gpios {
1154*72b50c2fSJens Glathe	usb0_1p8_reg_en: usb0-1p8-reg-en-state {
1155*72b50c2fSJens Glathe		pins = "gpio8";
1156*72b50c2fSJens Glathe		function = "normal";
1157*72b50c2fSJens Glathe		power-source = <1>; /* 1.8V */
1158*72b50c2fSJens Glathe		bias-disable;
1159*72b50c2fSJens Glathe		input-disable;
1160*72b50c2fSJens Glathe		output-enable;
1161*72b50c2fSJens Glathe	};
1162*72b50c2fSJens Glathe};
1163*72b50c2fSJens Glathe
1164*72b50c2fSJens Glathe&pmc8380_3_gpios {
1165*72b50c2fSJens Glathe	edp_bl_en: edp-bl-en-state {
1166*72b50c2fSJens Glathe		pins = "gpio4";
1167*72b50c2fSJens Glathe		function = "normal";
1168*72b50c2fSJens Glathe		power-source = <1>; /* 1.8V */
1169*72b50c2fSJens Glathe		input-disable;
1170*72b50c2fSJens Glathe		output-enable;
1171*72b50c2fSJens Glathe	};
1172*72b50c2fSJens Glathe
1173*72b50c2fSJens Glathe	edp_bl_reg_en: edp-bl-reg-en-state {
1174*72b50c2fSJens Glathe		pins = "gpio10";
1175*72b50c2fSJens Glathe		function = "normal";
1176*72b50c2fSJens Glathe	};
1177*72b50c2fSJens Glathe
1178*72b50c2fSJens Glathe};
1179*72b50c2fSJens Glathe
1180*72b50c2fSJens Glathe&pmc8380_5_gpios {
1181*72b50c2fSJens Glathe	usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
1182*72b50c2fSJens Glathe		pins = "gpio8";
1183*72b50c2fSJens Glathe		function = "normal";
1184*72b50c2fSJens Glathe		power-source = <1>; /* 1.8V */
1185*72b50c2fSJens Glathe		bias-disable;
1186*72b50c2fSJens Glathe		input-disable;
1187*72b50c2fSJens Glathe		output-enable;
1188*72b50c2fSJens Glathe	};
1189*72b50c2fSJens Glathe};
1190*72b50c2fSJens Glathe
1191*72b50c2fSJens Glathe&pmk8550_gpios {
1192*72b50c2fSJens Glathe	edp_bl_pwm: edp-bl-pwm-state {
1193*72b50c2fSJens Glathe		pins = "gpio5";
1194*72b50c2fSJens Glathe		function = "func3";
1195*72b50c2fSJens Glathe	};
1196*72b50c2fSJens Glathe};
1197*72b50c2fSJens Glathe
1198*72b50c2fSJens Glathe&pmk8550_pwm {
1199*72b50c2fSJens Glathe	status = "okay";
1200*72b50c2fSJens Glathe};
1201*72b50c2fSJens Glathe
1202*72b50c2fSJens Glathe&qupv3_0 {
1203*72b50c2fSJens Glathe	status = "okay";
1204*72b50c2fSJens Glathe};
1205*72b50c2fSJens Glathe
1206*72b50c2fSJens Glathe&qupv3_1 {
1207*72b50c2fSJens Glathe	status = "okay";
1208*72b50c2fSJens Glathe};
1209*72b50c2fSJens Glathe
1210*72b50c2fSJens Glathe&qupv3_2 {
1211*72b50c2fSJens Glathe	status = "okay";
1212*72b50c2fSJens Glathe};
1213*72b50c2fSJens Glathe
1214*72b50c2fSJens Glathe&smb2360_0 {
1215*72b50c2fSJens Glathe	status = "okay";
1216*72b50c2fSJens Glathe};
1217*72b50c2fSJens Glathe
1218*72b50c2fSJens Glathe&smb2360_0_eusb2_repeater {
1219*72b50c2fSJens Glathe	vdd18-supply = <&vreg_l3d_1p8>;
1220*72b50c2fSJens Glathe	vdd3-supply = <&vreg_l2b_3p0>;
1221*72b50c2fSJens Glathe};
1222*72b50c2fSJens Glathe
1223*72b50c2fSJens Glathe&smb2360_1 {
1224*72b50c2fSJens Glathe	status = "okay";
1225*72b50c2fSJens Glathe};
1226*72b50c2fSJens Glathe
1227*72b50c2fSJens Glathe&smb2360_1_eusb2_repeater {
1228*72b50c2fSJens Glathe	vdd18-supply = <&vreg_l3d_1p8>;
1229*72b50c2fSJens Glathe	vdd3-supply = <&vreg_l14b_3p0>;
1230*72b50c2fSJens Glathe};
1231*72b50c2fSJens Glathe
1232*72b50c2fSJens Glathe&swr0 {
1233*72b50c2fSJens Glathe	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
1234*72b50c2fSJens Glathe	pinctrl-names = "default";
1235*72b50c2fSJens Glathe
1236*72b50c2fSJens Glathe	status = "okay";
1237*72b50c2fSJens Glathe
1238*72b50c2fSJens Glathe	/* WSA8845, Left Speaker */
1239*72b50c2fSJens Glathe	left_spkr: speaker@0,0 {
1240*72b50c2fSJens Glathe		compatible = "sdw20217020400";
1241*72b50c2fSJens Glathe		reg = <0 0>;
1242*72b50c2fSJens Glathe		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
1243*72b50c2fSJens Glathe		#sound-dai-cells = <0>;
1244*72b50c2fSJens Glathe		sound-name-prefix = "SpkrLeft";
1245*72b50c2fSJens Glathe		vdd-1p8-supply = <&vreg_l15b_1p8>;
1246*72b50c2fSJens Glathe		vdd-io-supply = <&vreg_l12b_1p2>;
1247*72b50c2fSJens Glathe		qcom,port-mapping = <1 2 3 7 10 13>;
1248*72b50c2fSJens Glathe	};
1249*72b50c2fSJens Glathe
1250*72b50c2fSJens Glathe	/* WSA8845, Right Speaker */
1251*72b50c2fSJens Glathe	right_spkr: speaker@0,1 {
1252*72b50c2fSJens Glathe		compatible = "sdw20217020400";
1253*72b50c2fSJens Glathe		reg = <0 1>;
1254*72b50c2fSJens Glathe		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
1255*72b50c2fSJens Glathe		#sound-dai-cells = <0>;
1256*72b50c2fSJens Glathe		sound-name-prefix = "SpkrRight";
1257*72b50c2fSJens Glathe		vdd-1p8-supply = <&vreg_l15b_1p8>;
1258*72b50c2fSJens Glathe		vdd-io-supply = <&vreg_l12b_1p2>;
1259*72b50c2fSJens Glathe		qcom,port-mapping = <4 5 6 7 11 13>;
1260*72b50c2fSJens Glathe	};
1261*72b50c2fSJens Glathe};
1262*72b50c2fSJens Glathe
1263*72b50c2fSJens Glathe&swr1 {
1264*72b50c2fSJens Glathe	status = "okay";
1265*72b50c2fSJens Glathe
1266*72b50c2fSJens Glathe	/* WCD9385 RX */
1267*72b50c2fSJens Glathe	wcd_rx: codec@0,4 {
1268*72b50c2fSJens Glathe		compatible = "sdw20217010d00";
1269*72b50c2fSJens Glathe		reg = <0 4>;
1270*72b50c2fSJens Glathe		qcom,rx-port-mapping = <1 2 3 4 5>;
1271*72b50c2fSJens Glathe	};
1272*72b50c2fSJens Glathe};
1273*72b50c2fSJens Glathe
1274*72b50c2fSJens Glathe&swr2 {
1275*72b50c2fSJens Glathe	status = "okay";
1276*72b50c2fSJens Glathe
1277*72b50c2fSJens Glathe	/* WCD9385 TX */
1278*72b50c2fSJens Glathe	wcd_tx: codec@0,3 {
1279*72b50c2fSJens Glathe		compatible = "sdw20217010d00";
1280*72b50c2fSJens Glathe		reg = <0 3>;
1281*72b50c2fSJens Glathe		qcom,tx-port-mapping = <2 2 3 4>;
1282*72b50c2fSJens Glathe	};
1283*72b50c2fSJens Glathe};
1284*72b50c2fSJens Glathe
1285*72b50c2fSJens Glathe&tlmm {
1286*72b50c2fSJens Glathe	gpio-reserved-ranges = <34 2>, /* Unused */
1287*72b50c2fSJens Glathe			       <44 4>, /* SPI (TPM) */
1288*72b50c2fSJens Glathe			       <72 2>, /* Secure EC I2C connection (?) */
1289*72b50c2fSJens Glathe			       <238 1>; /* UFS Reset */
1290*72b50c2fSJens Glathe
1291*72b50c2fSJens Glathe	edp_reg_en: edp-reg-en-state {
1292*72b50c2fSJens Glathe		pins = "gpio70";
1293*72b50c2fSJens Glathe		function = "gpio";
1294*72b50c2fSJens Glathe		drive-strength = <16>;
1295*72b50c2fSJens Glathe		bias-disable;
1296*72b50c2fSJens Glathe	};
1297*72b50c2fSJens Glathe
1298*72b50c2fSJens Glathe	eusb3_reset_n: eusb3-reset-n-state {
1299*72b50c2fSJens Glathe		pins = "gpio6";
1300*72b50c2fSJens Glathe		function = "gpio";
1301*72b50c2fSJens Glathe		drive-strength = <2>;
1302*72b50c2fSJens Glathe		bias-disable;
1303*72b50c2fSJens Glathe		output-low;
1304*72b50c2fSJens Glathe	};
1305*72b50c2fSJens Glathe
1306*72b50c2fSJens Glathe	hall_int_n_default: hall-int-n-state {
1307*72b50c2fSJens Glathe		pins = "gpio92";
1308*72b50c2fSJens Glathe		function = "gpio";
1309*72b50c2fSJens Glathe		bias-disable;
1310*72b50c2fSJens Glathe	};
1311*72b50c2fSJens Glathe
1312*72b50c2fSJens Glathe	kybd_default: kybd-default-state {
1313*72b50c2fSJens Glathe		pins = "gpio67";
1314*72b50c2fSJens Glathe		function = "gpio";
1315*72b50c2fSJens Glathe		bias-pull-up;
1316*72b50c2fSJens Glathe	};
1317*72b50c2fSJens Glathe
1318*72b50c2fSJens Glathe	nvme_reg_en: nvme-reg-en-state {
1319*72b50c2fSJens Glathe		pins = "gpio18";
1320*72b50c2fSJens Glathe		function = "gpio";
1321*72b50c2fSJens Glathe		drive-strength = <2>;
1322*72b50c2fSJens Glathe		bias-disable;
1323*72b50c2fSJens Glathe	};
1324*72b50c2fSJens Glathe
1325*72b50c2fSJens Glathe	pcie4_default: pcie4-default-state {
1326*72b50c2fSJens Glathe		clkreq-n-pins {
1327*72b50c2fSJens Glathe			pins = "gpio147";
1328*72b50c2fSJens Glathe			function = "pcie4_clk";
1329*72b50c2fSJens Glathe			drive-strength = <2>;
1330*72b50c2fSJens Glathe			bias-pull-up;
1331*72b50c2fSJens Glathe		};
1332*72b50c2fSJens Glathe
1333*72b50c2fSJens Glathe		perst-n-pins {
1334*72b50c2fSJens Glathe			pins = "gpio146";
1335*72b50c2fSJens Glathe			function = "gpio";
1336*72b50c2fSJens Glathe			drive-strength = <2>;
1337*72b50c2fSJens Glathe			bias-disable;
1338*72b50c2fSJens Glathe		};
1339*72b50c2fSJens Glathe
1340*72b50c2fSJens Glathe		wake-n-pins {
1341*72b50c2fSJens Glathe			pins = "gpio148";
1342*72b50c2fSJens Glathe			function = "gpio";
1343*72b50c2fSJens Glathe			drive-strength = <2>;
1344*72b50c2fSJens Glathe			bias-pull-up;
1345*72b50c2fSJens Glathe		};
1346*72b50c2fSJens Glathe	};
1347*72b50c2fSJens Glathe
1348*72b50c2fSJens Glathe	pcie6a_default: pcie6a-default-state {
1349*72b50c2fSJens Glathe		clkreq-n-pins {
1350*72b50c2fSJens Glathe			pins = "gpio153";
1351*72b50c2fSJens Glathe			function = "pcie6a_clk";
1352*72b50c2fSJens Glathe			drive-strength = <2>;
1353*72b50c2fSJens Glathe			bias-pull-up;
1354*72b50c2fSJens Glathe		};
1355*72b50c2fSJens Glathe
1356*72b50c2fSJens Glathe		perst-n-pins {
1357*72b50c2fSJens Glathe			pins = "gpio152";
1358*72b50c2fSJens Glathe			function = "gpio";
1359*72b50c2fSJens Glathe			drive-strength = <2>;
1360*72b50c2fSJens Glathe			bias-disable;
1361*72b50c2fSJens Glathe		};
1362*72b50c2fSJens Glathe
1363*72b50c2fSJens Glathe		wake-n-pins {
1364*72b50c2fSJens Glathe			pins = "gpio154";
1365*72b50c2fSJens Glathe			function = "gpio";
1366*72b50c2fSJens Glathe			drive-strength = <2>;
1367*72b50c2fSJens Glathe			bias-pull-up;
1368*72b50c2fSJens Glathe		};
1369*72b50c2fSJens Glathe	};
1370*72b50c2fSJens Glathe
1371*72b50c2fSJens Glathe	tpad_default: tpad-default-state {
1372*72b50c2fSJens Glathe		pins = "gpio3";
1373*72b50c2fSJens Glathe		function = "gpio";
1374*72b50c2fSJens Glathe		bias-pull-up;
1375*72b50c2fSJens Glathe	};
1376*72b50c2fSJens Glathe
1377*72b50c2fSJens Glathe	ts0_default: ts0-default-state {
1378*72b50c2fSJens Glathe		int-n-pins {
1379*72b50c2fSJens Glathe			pins = "gpio51";
1380*72b50c2fSJens Glathe			function = "gpio";
1381*72b50c2fSJens Glathe			bias-pull-up;
1382*72b50c2fSJens Glathe		};
1383*72b50c2fSJens Glathe
1384*72b50c2fSJens Glathe		reset-n-pins {
1385*72b50c2fSJens Glathe			pins = "gpio48";
1386*72b50c2fSJens Glathe			function = "gpio";
1387*72b50c2fSJens Glathe			output-high;
1388*72b50c2fSJens Glathe			drive-strength = <16>;
1389*72b50c2fSJens Glathe		};
1390*72b50c2fSJens Glathe	};
1391*72b50c2fSJens Glathe
1392*72b50c2fSJens Glathe	usb_1_ss1_sbu_default: usb-1-ss1-sbu-state {
1393*72b50c2fSJens Glathe		mode-pins {
1394*72b50c2fSJens Glathe			pins = "gpio177";
1395*72b50c2fSJens Glathe			function = "gpio";
1396*72b50c2fSJens Glathe			bias-disable;
1397*72b50c2fSJens Glathe			drive-strength = <2>;
1398*72b50c2fSJens Glathe			output-high;
1399*72b50c2fSJens Glathe		};
1400*72b50c2fSJens Glathe
1401*72b50c2fSJens Glathe		oe-n-pins {
1402*72b50c2fSJens Glathe			pins = "gpio179";
1403*72b50c2fSJens Glathe			function = "gpio";
1404*72b50c2fSJens Glathe			bias-disable;
1405*72b50c2fSJens Glathe			drive-strength = <2>;
1406*72b50c2fSJens Glathe		};
1407*72b50c2fSJens Glathe
1408*72b50c2fSJens Glathe		sel-pins {
1409*72b50c2fSJens Glathe			pins = "gpio178";
1410*72b50c2fSJens Glathe			function = "gpio";
1411*72b50c2fSJens Glathe			bias-disable;
1412*72b50c2fSJens Glathe			drive-strength = <2>;
1413*72b50c2fSJens Glathe		};
1414*72b50c2fSJens Glathe	};
1415*72b50c2fSJens Glathe
1416*72b50c2fSJens Glathe	wcd_default: wcd-reset-n-active-state {
1417*72b50c2fSJens Glathe		pins = "gpio191";
1418*72b50c2fSJens Glathe		function = "gpio";
1419*72b50c2fSJens Glathe		drive-strength = <16>;
1420*72b50c2fSJens Glathe		bias-disable;
1421*72b50c2fSJens Glathe		output-low;
1422*72b50c2fSJens Glathe	};
1423*72b50c2fSJens Glathe
1424*72b50c2fSJens Glathe	wcn_sw_en: wcn-sw-en-state {
1425*72b50c2fSJens Glathe		pins = "gpio214";
1426*72b50c2fSJens Glathe		function = "gpio";
1427*72b50c2fSJens Glathe		drive-strength = <2>;
1428*72b50c2fSJens Glathe		bias-disable;
1429*72b50c2fSJens Glathe	};
1430*72b50c2fSJens Glathe
1431*72b50c2fSJens Glathe	wcn_wlan_bt_en: wcn-wlan-bt-en-state {
1432*72b50c2fSJens Glathe		pins = "gpio116", "gpio117";
1433*72b50c2fSJens Glathe		function = "gpio";
1434*72b50c2fSJens Glathe		drive-strength = <2>;
1435*72b50c2fSJens Glathe		bias-disable;
1436*72b50c2fSJens Glathe	};
1437*72b50c2fSJens Glathe};
1438*72b50c2fSJens Glathe
1439*72b50c2fSJens Glathe&uart14 {
1440*72b50c2fSJens Glathe	status = "okay";
1441*72b50c2fSJens Glathe
1442*72b50c2fSJens Glathe	bluetooth {
1443*72b50c2fSJens Glathe		compatible = "qcom,wcn6855-bt";
1444*72b50c2fSJens Glathe		max-speed = <3200000>;
1445*72b50c2fSJens Glathe
1446*72b50c2fSJens Glathe		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
1447*72b50c2fSJens Glathe		vddaon-supply = <&vreg_pmu_aon_0p8>;
1448*72b50c2fSJens Glathe		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
1449*72b50c2fSJens Glathe		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
1450*72b50c2fSJens Glathe		vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
1451*72b50c2fSJens Glathe		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
1452*72b50c2fSJens Glathe		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
1453*72b50c2fSJens Glathe		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
1454*72b50c2fSJens Glathe	};
1455*72b50c2fSJens Glathe};
1456*72b50c2fSJens Glathe
1457*72b50c2fSJens Glathe&usb_1_ss0_hsphy {
1458*72b50c2fSJens Glathe	vdd-supply = <&vreg_l3j_0p8>;
1459*72b50c2fSJens Glathe	vdda12-supply = <&vreg_l2j_1p2>;
1460*72b50c2fSJens Glathe
1461*72b50c2fSJens Glathe	phys = <&smb2360_0_eusb2_repeater>;
1462*72b50c2fSJens Glathe
1463*72b50c2fSJens Glathe	status = "okay";
1464*72b50c2fSJens Glathe};
1465*72b50c2fSJens Glathe
1466*72b50c2fSJens Glathe&usb_1_ss0_qmpphy {
1467*72b50c2fSJens Glathe	vdda-phy-supply = <&vreg_l3e_1p2>;
1468*72b50c2fSJens Glathe	vdda-pll-supply = <&vreg_l1j_0p8>;
1469*72b50c2fSJens Glathe
1470*72b50c2fSJens Glathe	status = "okay";
1471*72b50c2fSJens Glathe};
1472*72b50c2fSJens Glathe
1473*72b50c2fSJens Glathe&usb_1_ss0 {
1474*72b50c2fSJens Glathe	status = "okay";
1475*72b50c2fSJens Glathe};
1476*72b50c2fSJens Glathe
1477*72b50c2fSJens Glathe&usb_1_ss0_dwc3 {
1478*72b50c2fSJens Glathe	dr_mode = "host";
1479*72b50c2fSJens Glathe};
1480*72b50c2fSJens Glathe
1481*72b50c2fSJens Glathe&usb_1_ss0_dwc3_hs {
1482*72b50c2fSJens Glathe	remote-endpoint = <&pmic_glink_ss0_hs_in>;
1483*72b50c2fSJens Glathe};
1484*72b50c2fSJens Glathe
1485*72b50c2fSJens Glathe&usb_1_ss0_qmpphy_out {
1486*72b50c2fSJens Glathe	remote-endpoint = <&retimer_ss0_ss_in>;
1487*72b50c2fSJens Glathe};
1488*72b50c2fSJens Glathe
1489*72b50c2fSJens Glathe&usb_1_ss1_hsphy {
1490*72b50c2fSJens Glathe	vdd-supply = <&vreg_l3j_0p8>;
1491*72b50c2fSJens Glathe	vdda12-supply = <&vreg_l2j_1p2>;
1492*72b50c2fSJens Glathe
1493*72b50c2fSJens Glathe	phys = <&smb2360_1_eusb2_repeater>;
1494*72b50c2fSJens Glathe
1495*72b50c2fSJens Glathe	status = "okay";
1496*72b50c2fSJens Glathe};
1497*72b50c2fSJens Glathe
1498*72b50c2fSJens Glathe&usb_1_ss1_qmpphy {
1499*72b50c2fSJens Glathe	vdda-phy-supply = <&vreg_l3e_1p2>;
1500*72b50c2fSJens Glathe	vdda-pll-supply = <&vreg_l2d_0p9>;
1501*72b50c2fSJens Glathe
1502*72b50c2fSJens Glathe	status = "okay";
1503*72b50c2fSJens Glathe};
1504*72b50c2fSJens Glathe
1505*72b50c2fSJens Glathe&usb_1_ss1 {
1506*72b50c2fSJens Glathe	status = "okay";
1507*72b50c2fSJens Glathe};
1508*72b50c2fSJens Glathe
1509*72b50c2fSJens Glathe&usb_1_ss1_dwc3 {
1510*72b50c2fSJens Glathe	dr_mode = "host";
1511*72b50c2fSJens Glathe};
1512*72b50c2fSJens Glathe
1513*72b50c2fSJens Glathe&usb_1_ss1_dwc3_hs {
1514*72b50c2fSJens Glathe	remote-endpoint = <&pmic_glink_ss1_hs_in>;
1515*72b50c2fSJens Glathe};
1516*72b50c2fSJens Glathe
1517*72b50c2fSJens Glathe&usb_1_ss1_qmpphy_out {
1518*72b50c2fSJens Glathe	remote-endpoint = <&pmic_glink_ss1_ss_in>;
1519*72b50c2fSJens Glathe};
1520*72b50c2fSJens Glathe
1521*72b50c2fSJens Glathe&usb_mp {
1522*72b50c2fSJens Glathe	status = "okay";
1523*72b50c2fSJens Glathe};
1524*72b50c2fSJens Glathe
1525*72b50c2fSJens Glathe&usb_mp_dwc3 {
1526*72b50c2fSJens Glathe	phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>;
1527*72b50c2fSJens Glathe	phy-names = "usb2-0", "usb3-0";
1528*72b50c2fSJens Glathe};
1529*72b50c2fSJens Glathe
1530*72b50c2fSJens Glathe&usb_mp_hsphy0 {
1531*72b50c2fSJens Glathe	vdd-supply = <&vreg_l2e_0p8>;
1532*72b50c2fSJens Glathe	vdda12-supply = <&vreg_l3e_1p2>;
1533*72b50c2fSJens Glathe
1534*72b50c2fSJens Glathe	phys = <&eusb3_repeater>;
1535*72b50c2fSJens Glathe
1536*72b50c2fSJens Glathe	status = "okay";
1537*72b50c2fSJens Glathe};
1538*72b50c2fSJens Glathe
1539*72b50c2fSJens Glathe&usb_mp_qmpphy0 {
1540*72b50c2fSJens Glathe	vdda-phy-supply = <&vreg_l3e_1p2>;
1541*72b50c2fSJens Glathe	vdda-pll-supply = <&vreg_l3c_0p8>;
1542*72b50c2fSJens Glathe
1543*72b50c2fSJens Glathe	status = "okay";
1544*72b50c2fSJens Glathe};
1545