15f82b9cdSKonrad Dybcio// SPDX-License-Identifier: BSD-3-Clause 25f82b9cdSKonrad Dybcio/* 35f82b9cdSKonrad Dybcio * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 438c5c4feSLuca Weiss * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 55f82b9cdSKonrad Dybcio */ 65f82b9cdSKonrad Dybcio 726c71d31SKonrad Dybcio#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8ab7cd7f3SKrzysztof Kozlowski#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 930de1108SKonrad Dybcio#include <dt-bindings/clock/qcom,gcc-sm6350.h> 1075a511b1SKonrad Dybcio#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 1130de1108SKonrad Dybcio#include <dt-bindings/clock/qcom,rpmh.h> 12033fb15fSLuca Weiss#include <dt-bindings/clock/qcom,sm6350-camcc.h> 139f0149caSLuca Weiss#include <dt-bindings/dma/qcom-gpi.h> 145f82b9cdSKonrad Dybcio#include <dt-bindings/gpio/gpio.h> 15bba95227SKonrad Dybcio#include <dt-bindings/interconnect/qcom,icc.h> 16bba95227SKonrad Dybcio#include <dt-bindings/interconnect/qcom,osm-l3.h> 1738c5c4feSLuca Weiss#include <dt-bindings/interconnect/qcom,sm6350.h> 185f82b9cdSKonrad Dybcio#include <dt-bindings/interrupt-controller/arm-gic.h> 195f82b9cdSKonrad Dybcio#include <dt-bindings/mailbox/qcom-ipcc.h> 205ed2b638SLuca Weiss#include <dt-bindings/phy/phy-qcom-qmp.h> 211797e1c9SKonrad Dybcio#include <dt-bindings/power/qcom-rpmpd.h> 22*a014ad1aSLuca Weiss#include <dt-bindings/soc/qcom,apr.h> 235f82b9cdSKonrad Dybcio#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24*a014ad1aSLuca Weiss#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 2564628795SLuca Weiss#include <dt-bindings/thermal/thermal.h> 265f82b9cdSKonrad Dybcio 275f82b9cdSKonrad Dybcio/ { 285f82b9cdSKonrad Dybcio interrupt-parent = <&intc>; 295f82b9cdSKonrad Dybcio #address-cells = <2>; 305f82b9cdSKonrad Dybcio #size-cells = <2>; 315f82b9cdSKonrad Dybcio 325f82b9cdSKonrad Dybcio clocks { 335f82b9cdSKonrad Dybcio xo_board: xo-board { 345f82b9cdSKonrad Dybcio compatible = "fixed-clock"; 355f82b9cdSKonrad Dybcio #clock-cells = <0>; 365f82b9cdSKonrad Dybcio clock-frequency = <76800000>; 375f82b9cdSKonrad Dybcio clock-output-names = "xo_board"; 385f82b9cdSKonrad Dybcio }; 395f82b9cdSKonrad Dybcio 405f82b9cdSKonrad Dybcio sleep_clk: sleep-clk { 415f82b9cdSKonrad Dybcio compatible = "fixed-clock"; 425f82b9cdSKonrad Dybcio clock-frequency = <32764>; 435f82b9cdSKonrad Dybcio #clock-cells = <0>; 445f82b9cdSKonrad Dybcio }; 455f82b9cdSKonrad Dybcio }; 465f82b9cdSKonrad Dybcio 475f82b9cdSKonrad Dybcio cpus { 485f82b9cdSKonrad Dybcio #address-cells = <2>; 495f82b9cdSKonrad Dybcio #size-cells = <0>; 505f82b9cdSKonrad Dybcio 51b0864ab2SKrzysztof Kozlowski cpu0: cpu@0 { 525f82b9cdSKonrad Dybcio device_type = "cpu"; 535f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 545f82b9cdSKonrad Dybcio reg = <0x0 0x0>; 55afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 565f82b9cdSKonrad Dybcio enable-method = "psci"; 575f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1024>; 585f82b9cdSKonrad Dybcio dynamic-power-coefficient = <100>; 59b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_0>; 603cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 0>; 61bba95227SKonrad Dybcio operating-points-v2 = <&cpu0_opp_table>; 62bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 63bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 64bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd0>; 66ade89bc0SKonrad Dybcio power-domain-names = "psci"; 675f82b9cdSKonrad Dybcio #cooling-cells = <2>; 68b0864ab2SKrzysztof Kozlowski l2_0: l2-cache { 695f82b9cdSKonrad Dybcio compatible = "cache"; 709435294cSPierre Gondois cache-level = <2>; 719c6e72fbSKrzysztof Kozlowski cache-unified; 72b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 73b0864ab2SKrzysztof Kozlowski l3_0: l3-cache { 745f82b9cdSKonrad Dybcio compatible = "cache"; 759435294cSPierre Gondois cache-level = <3>; 769c6e72fbSKrzysztof Kozlowski cache-unified; 775f82b9cdSKonrad Dybcio }; 785f82b9cdSKonrad Dybcio }; 795f82b9cdSKonrad Dybcio }; 805f82b9cdSKonrad Dybcio 81b0864ab2SKrzysztof Kozlowski cpu1: cpu@100 { 825f82b9cdSKonrad Dybcio device_type = "cpu"; 835f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 845f82b9cdSKonrad Dybcio reg = <0x0 0x100>; 85afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 865f82b9cdSKonrad Dybcio enable-method = "psci"; 875f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1024>; 885f82b9cdSKonrad Dybcio dynamic-power-coefficient = <100>; 89b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_100>; 903cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 0>; 91bba95227SKonrad Dybcio operating-points-v2 = <&cpu0_opp_table>; 92bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 93bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 94bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 95b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd1>; 96ade89bc0SKonrad Dybcio power-domain-names = "psci"; 975f82b9cdSKonrad Dybcio #cooling-cells = <2>; 98b0864ab2SKrzysztof Kozlowski l2_100: l2-cache { 995f82b9cdSKonrad Dybcio compatible = "cache"; 1009435294cSPierre Gondois cache-level = <2>; 1019c6e72fbSKrzysztof Kozlowski cache-unified; 102b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 1035f82b9cdSKonrad Dybcio }; 1045f82b9cdSKonrad Dybcio }; 1055f82b9cdSKonrad Dybcio 106b0864ab2SKrzysztof Kozlowski cpu2: cpu@200 { 1075f82b9cdSKonrad Dybcio device_type = "cpu"; 1085f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 1095f82b9cdSKonrad Dybcio reg = <0x0 0x200>; 110afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 1115f82b9cdSKonrad Dybcio enable-method = "psci"; 1125f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1024>; 1135f82b9cdSKonrad Dybcio dynamic-power-coefficient = <100>; 114b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_200>; 1153cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 0>; 116bba95227SKonrad Dybcio operating-points-v2 = <&cpu0_opp_table>; 117bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 118bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 119bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 120b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd2>; 121ade89bc0SKonrad Dybcio power-domain-names = "psci"; 1225f82b9cdSKonrad Dybcio #cooling-cells = <2>; 123b0864ab2SKrzysztof Kozlowski l2_200: l2-cache { 1245f82b9cdSKonrad Dybcio compatible = "cache"; 1259435294cSPierre Gondois cache-level = <2>; 1269c6e72fbSKrzysztof Kozlowski cache-unified; 127b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 1285f82b9cdSKonrad Dybcio }; 1295f82b9cdSKonrad Dybcio }; 1305f82b9cdSKonrad Dybcio 131b0864ab2SKrzysztof Kozlowski cpu3: cpu@300 { 1325f82b9cdSKonrad Dybcio device_type = "cpu"; 1335f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 1345f82b9cdSKonrad Dybcio reg = <0x0 0x300>; 135afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 1365f82b9cdSKonrad Dybcio enable-method = "psci"; 1375f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1024>; 1385f82b9cdSKonrad Dybcio dynamic-power-coefficient = <100>; 139b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_300>; 1403cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 0>; 141bba95227SKonrad Dybcio operating-points-v2 = <&cpu0_opp_table>; 142bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 143bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 144bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 145b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd3>; 146ade89bc0SKonrad Dybcio power-domain-names = "psci"; 1475f82b9cdSKonrad Dybcio #cooling-cells = <2>; 148b0864ab2SKrzysztof Kozlowski l2_300: l2-cache { 1495f82b9cdSKonrad Dybcio compatible = "cache"; 1509435294cSPierre Gondois cache-level = <2>; 1519c6e72fbSKrzysztof Kozlowski cache-unified; 152b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 1535f82b9cdSKonrad Dybcio }; 1545f82b9cdSKonrad Dybcio }; 1555f82b9cdSKonrad Dybcio 156b0864ab2SKrzysztof Kozlowski cpu4: cpu@400 { 1575f82b9cdSKonrad Dybcio device_type = "cpu"; 1585f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 1595f82b9cdSKonrad Dybcio reg = <0x0 0x400>; 160afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 1615f82b9cdSKonrad Dybcio enable-method = "psci"; 1625f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1024>; 1635f82b9cdSKonrad Dybcio dynamic-power-coefficient = <100>; 164b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_400>; 1653cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 0>; 166bba95227SKonrad Dybcio operating-points-v2 = <&cpu0_opp_table>; 167bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 168bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 169bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd4>; 171ade89bc0SKonrad Dybcio power-domain-names = "psci"; 1725f82b9cdSKonrad Dybcio #cooling-cells = <2>; 173b0864ab2SKrzysztof Kozlowski l2_400: l2-cache { 1745f82b9cdSKonrad Dybcio compatible = "cache"; 1759435294cSPierre Gondois cache-level = <2>; 1769c6e72fbSKrzysztof Kozlowski cache-unified; 177b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 1785f82b9cdSKonrad Dybcio }; 1795f82b9cdSKonrad Dybcio }; 1805f82b9cdSKonrad Dybcio 181b0864ab2SKrzysztof Kozlowski cpu5: cpu@500 { 1825f82b9cdSKonrad Dybcio device_type = "cpu"; 1835f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 1845f82b9cdSKonrad Dybcio reg = <0x0 0x500>; 185afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 1865f82b9cdSKonrad Dybcio enable-method = "psci"; 1875f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1024>; 1885f82b9cdSKonrad Dybcio dynamic-power-coefficient = <100>; 189b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_500>; 1903cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 0>; 191bba95227SKonrad Dybcio operating-points-v2 = <&cpu0_opp_table>; 192bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 193bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 194bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd5>; 196ade89bc0SKonrad Dybcio power-domain-names = "psci"; 1975f82b9cdSKonrad Dybcio #cooling-cells = <2>; 198b0864ab2SKrzysztof Kozlowski l2_500: l2-cache { 1995f82b9cdSKonrad Dybcio compatible = "cache"; 2009435294cSPierre Gondois cache-level = <2>; 2019c6e72fbSKrzysztof Kozlowski cache-unified; 202b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 2035f82b9cdSKonrad Dybcio }; 2045f82b9cdSKonrad Dybcio }; 2055f82b9cdSKonrad Dybcio 206b0864ab2SKrzysztof Kozlowski cpu6: cpu@600 { 2075f82b9cdSKonrad Dybcio device_type = "cpu"; 2085f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 2095f82b9cdSKonrad Dybcio reg = <0x0 0x600>; 210afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 2115f82b9cdSKonrad Dybcio enable-method = "psci"; 2125f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1894>; 2135f82b9cdSKonrad Dybcio dynamic-power-coefficient = <703>; 214b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_600>; 2153cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 1>; 216bba95227SKonrad Dybcio operating-points-v2 = <&cpu6_opp_table>; 217bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 218bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 219bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd6>; 221ade89bc0SKonrad Dybcio power-domain-names = "psci"; 2225f82b9cdSKonrad Dybcio #cooling-cells = <2>; 223b0864ab2SKrzysztof Kozlowski l2_600: l2-cache { 2245f82b9cdSKonrad Dybcio compatible = "cache"; 2259435294cSPierre Gondois cache-level = <2>; 2269c6e72fbSKrzysztof Kozlowski cache-unified; 227b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 2285f82b9cdSKonrad Dybcio }; 2295f82b9cdSKonrad Dybcio }; 2305f82b9cdSKonrad Dybcio 231b0864ab2SKrzysztof Kozlowski cpu7: cpu@700 { 2325f82b9cdSKonrad Dybcio device_type = "cpu"; 2335f82b9cdSKonrad Dybcio compatible = "qcom,kryo560"; 2345f82b9cdSKonrad Dybcio reg = <0x0 0x700>; 235afa34380SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 2365f82b9cdSKonrad Dybcio enable-method = "psci"; 2375f82b9cdSKonrad Dybcio capacity-dmips-mhz = <1894>; 2385f82b9cdSKonrad Dybcio dynamic-power-coefficient = <703>; 239b0864ab2SKrzysztof Kozlowski next-level-cache = <&l2_700>; 2403cc41541SKonrad Dybcio qcom,freq-domain = <&cpufreq_hw 1>; 241bba95227SKonrad Dybcio operating-points-v2 = <&cpu6_opp_table>; 242bba95227SKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 243bba95227SKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 244bba95227SKonrad Dybcio <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 245b0864ab2SKrzysztof Kozlowski power-domains = <&cpu_pd7>; 246ade89bc0SKonrad Dybcio power-domain-names = "psci"; 2475f82b9cdSKonrad Dybcio #cooling-cells = <2>; 248b0864ab2SKrzysztof Kozlowski l2_700: l2-cache { 2495f82b9cdSKonrad Dybcio compatible = "cache"; 2509435294cSPierre Gondois cache-level = <2>; 2519c6e72fbSKrzysztof Kozlowski cache-unified; 252b0864ab2SKrzysztof Kozlowski next-level-cache = <&l3_0>; 2535f82b9cdSKonrad Dybcio }; 2545f82b9cdSKonrad Dybcio }; 2555f82b9cdSKonrad Dybcio 2565f82b9cdSKonrad Dybcio cpu-map { 2575f82b9cdSKonrad Dybcio cluster0 { 2585f82b9cdSKonrad Dybcio core0 { 259b0864ab2SKrzysztof Kozlowski cpu = <&cpu0>; 2605f82b9cdSKonrad Dybcio }; 2615f82b9cdSKonrad Dybcio 2625f82b9cdSKonrad Dybcio core1 { 263b0864ab2SKrzysztof Kozlowski cpu = <&cpu1>; 2645f82b9cdSKonrad Dybcio }; 2655f82b9cdSKonrad Dybcio 2665f82b9cdSKonrad Dybcio core2 { 267b0864ab2SKrzysztof Kozlowski cpu = <&cpu2>; 2685f82b9cdSKonrad Dybcio }; 2695f82b9cdSKonrad Dybcio 2705f82b9cdSKonrad Dybcio core3 { 271b0864ab2SKrzysztof Kozlowski cpu = <&cpu3>; 2725f82b9cdSKonrad Dybcio }; 2735f82b9cdSKonrad Dybcio 2745f82b9cdSKonrad Dybcio core4 { 275b0864ab2SKrzysztof Kozlowski cpu = <&cpu4>; 2765f82b9cdSKonrad Dybcio }; 2775f82b9cdSKonrad Dybcio 2785f82b9cdSKonrad Dybcio core5 { 279b0864ab2SKrzysztof Kozlowski cpu = <&cpu5>; 2805f82b9cdSKonrad Dybcio }; 2815f82b9cdSKonrad Dybcio 2825f82b9cdSKonrad Dybcio core6 { 283b0864ab2SKrzysztof Kozlowski cpu = <&cpu6>; 2845f82b9cdSKonrad Dybcio }; 2855f82b9cdSKonrad Dybcio 2865f82b9cdSKonrad Dybcio core7 { 287b0864ab2SKrzysztof Kozlowski cpu = <&cpu7>; 2885f82b9cdSKonrad Dybcio }; 2895f82b9cdSKonrad Dybcio }; 2905f82b9cdSKonrad Dybcio }; 291ade89bc0SKonrad Dybcio 292ade89bc0SKonrad Dybcio domain-idle-states { 293b0864ab2SKrzysztof Kozlowski cluster_sleep_pc: cluster-sleep-0 { 294ade89bc0SKonrad Dybcio compatible = "domain-idle-state"; 295ade89bc0SKonrad Dybcio arm,psci-suspend-param = <0x41000044>; 296ade89bc0SKonrad Dybcio entry-latency-us = <2752>; 297ade89bc0SKonrad Dybcio exit-latency-us = <3048>; 298ade89bc0SKonrad Dybcio min-residency-us = <6118>; 299ade89bc0SKonrad Dybcio }; 300ade89bc0SKonrad Dybcio 301b0864ab2SKrzysztof Kozlowski cluster_sleep_cx_ret: cluster-sleep-1 { 302ade89bc0SKonrad Dybcio compatible = "domain-idle-state"; 303ade89bc0SKonrad Dybcio arm,psci-suspend-param = <0x41001244>; 304ade89bc0SKonrad Dybcio entry-latency-us = <3638>; 305ade89bc0SKonrad Dybcio exit-latency-us = <4562>; 306ade89bc0SKonrad Dybcio min-residency-us = <8467>; 307ade89bc0SKonrad Dybcio }; 308ade89bc0SKonrad Dybcio 309b0864ab2SKrzysztof Kozlowski cluster_aoss_sleep: cluster-sleep-2 { 310ade89bc0SKonrad Dybcio compatible = "domain-idle-state"; 311ade89bc0SKonrad Dybcio arm,psci-suspend-param = <0x4100b244>; 312ade89bc0SKonrad Dybcio entry-latency-us = <3263>; 313ade89bc0SKonrad Dybcio exit-latency-us = <6562>; 314ade89bc0SKonrad Dybcio min-residency-us = <9987>; 315ade89bc0SKonrad Dybcio }; 316ade89bc0SKonrad Dybcio }; 317ade89bc0SKonrad Dybcio 318ade89bc0SKonrad Dybcio cpu_idle_states: idle-states { 319ade89bc0SKonrad Dybcio entry-method = "psci"; 320ade89bc0SKonrad Dybcio 321b0864ab2SKrzysztof Kozlowski little_cpu_sleep_0: cpu-sleep-0-0 { 322ade89bc0SKonrad Dybcio compatible = "arm,idle-state"; 323ade89bc0SKonrad Dybcio idle-state-name = "little-power-collapse"; 324ade89bc0SKonrad Dybcio arm,psci-suspend-param = <0x40000003>; 325ade89bc0SKonrad Dybcio entry-latency-us = <549>; 326ade89bc0SKonrad Dybcio exit-latency-us = <901>; 327ade89bc0SKonrad Dybcio min-residency-us = <1774>; 328ade89bc0SKonrad Dybcio local-timer-stop; 329ade89bc0SKonrad Dybcio }; 330ade89bc0SKonrad Dybcio 331b0864ab2SKrzysztof Kozlowski little_cpu_sleep_1: cpu-sleep-0-1 { 332ade89bc0SKonrad Dybcio compatible = "arm,idle-state"; 333ade89bc0SKonrad Dybcio idle-state-name = "little-rail-power-collapse"; 334ade89bc0SKonrad Dybcio arm,psci-suspend-param = <0x40000004>; 335ade89bc0SKonrad Dybcio entry-latency-us = <702>; 336ade89bc0SKonrad Dybcio exit-latency-us = <915>; 337ade89bc0SKonrad Dybcio min-residency-us = <4001>; 338ade89bc0SKonrad Dybcio local-timer-stop; 339ade89bc0SKonrad Dybcio }; 340ade89bc0SKonrad Dybcio 341b0864ab2SKrzysztof Kozlowski big_cpu_sleep_0: cpu-sleep-1-0 { 342ade89bc0SKonrad Dybcio compatible = "arm,idle-state"; 343ade89bc0SKonrad Dybcio idle-state-name = "big-power-collapse"; 344ade89bc0SKonrad Dybcio arm,psci-suspend-param = <0x40000003>; 345ade89bc0SKonrad Dybcio entry-latency-us = <523>; 346ade89bc0SKonrad Dybcio exit-latency-us = <1244>; 347ade89bc0SKonrad Dybcio min-residency-us = <2207>; 348ade89bc0SKonrad Dybcio local-timer-stop; 349ade89bc0SKonrad Dybcio }; 350ade89bc0SKonrad Dybcio 351b0864ab2SKrzysztof Kozlowski big_cpu_sleep_1: cpu-sleep-1-1 { 352ade89bc0SKonrad Dybcio compatible = "arm,idle-state"; 353ade89bc0SKonrad Dybcio idle-state-name = "big-rail-power-collapse"; 354ade89bc0SKonrad Dybcio arm,psci-suspend-param = <0x40000004>; 355ade89bc0SKonrad Dybcio entry-latency-us = <526>; 356ade89bc0SKonrad Dybcio exit-latency-us = <1854>; 357ade89bc0SKonrad Dybcio min-residency-us = <5555>; 358ade89bc0SKonrad Dybcio local-timer-stop; 359ade89bc0SKonrad Dybcio }; 360ade89bc0SKonrad Dybcio }; 3615f82b9cdSKonrad Dybcio }; 3625f82b9cdSKonrad Dybcio 3635f82b9cdSKonrad Dybcio firmware { 3645f82b9cdSKonrad Dybcio scm: scm { 3655f82b9cdSKonrad Dybcio compatible = "qcom,scm-sm6350", "qcom,scm"; 3665f82b9cdSKonrad Dybcio #reset-cells = <1>; 3675f82b9cdSKonrad Dybcio }; 3685f82b9cdSKonrad Dybcio }; 3695f82b9cdSKonrad Dybcio 3705f82b9cdSKonrad Dybcio memory@80000000 { 3715f82b9cdSKonrad Dybcio device_type = "memory"; 3725f82b9cdSKonrad Dybcio /* We expect the bootloader to fill in the size */ 3735f82b9cdSKonrad Dybcio reg = <0x0 0x80000000 0x0 0x0>; 3745f82b9cdSKonrad Dybcio }; 3755f82b9cdSKonrad Dybcio 376bba95227SKonrad Dybcio cpu0_opp_table: opp-table-cpu0 { 377bba95227SKonrad Dybcio compatible = "operating-points-v2"; 378bba95227SKonrad Dybcio opp-shared; 379bba95227SKonrad Dybcio 380bba95227SKonrad Dybcio opp-300000000 { 381bba95227SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 382bba95227SKonrad Dybcio /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 383bba95227SKonrad Dybcio opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 384bba95227SKonrad Dybcio }; 385bba95227SKonrad Dybcio 386bba95227SKonrad Dybcio opp-576000000 { 387bba95227SKonrad Dybcio opp-hz = /bits/ 64 <576000000>; 388bba95227SKonrad Dybcio opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 389bba95227SKonrad Dybcio }; 390bba95227SKonrad Dybcio 391bba95227SKonrad Dybcio opp-768000000 { 392bba95227SKonrad Dybcio opp-hz = /bits/ 64 <768000000>; 393bba95227SKonrad Dybcio opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 394bba95227SKonrad Dybcio }; 395bba95227SKonrad Dybcio 396bba95227SKonrad Dybcio opp-1017600000 { 397bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1017600000>; 398bba95227SKonrad Dybcio opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 399bba95227SKonrad Dybcio }; 400bba95227SKonrad Dybcio 401bba95227SKonrad Dybcio opp-1248000000 { 402bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1248000000>; 403bba95227SKonrad Dybcio opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 404bba95227SKonrad Dybcio }; 405bba95227SKonrad Dybcio 406bba95227SKonrad Dybcio opp-1324800000 { 407bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1324800000>; 408bba95227SKonrad Dybcio opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 409bba95227SKonrad Dybcio }; 410bba95227SKonrad Dybcio 411bba95227SKonrad Dybcio opp-1516800000 { 412bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1516800000>; 413bba95227SKonrad Dybcio opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 414bba95227SKonrad Dybcio }; 415bba95227SKonrad Dybcio 416bba95227SKonrad Dybcio opp-1612800000 { 417bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1612800000>; 418bba95227SKonrad Dybcio opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 419bba95227SKonrad Dybcio }; 420bba95227SKonrad Dybcio 421bba95227SKonrad Dybcio opp-1708800000 { 422bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1708800000>; 423bba95227SKonrad Dybcio opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 424bba95227SKonrad Dybcio }; 425bba95227SKonrad Dybcio }; 426bba95227SKonrad Dybcio 427bba95227SKonrad Dybcio cpu6_opp_table: opp-table-cpu6 { 428bba95227SKonrad Dybcio compatible = "operating-points-v2"; 429bba95227SKonrad Dybcio opp-shared; 430bba95227SKonrad Dybcio 431bba95227SKonrad Dybcio opp-300000000 { 432bba95227SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 433bba95227SKonrad Dybcio opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 434bba95227SKonrad Dybcio }; 435bba95227SKonrad Dybcio 436bba95227SKonrad Dybcio opp-787200000 { 437bba95227SKonrad Dybcio opp-hz = /bits/ 64 <787200000>; 438bba95227SKonrad Dybcio opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 439bba95227SKonrad Dybcio }; 440bba95227SKonrad Dybcio 441bba95227SKonrad Dybcio opp-979200000 { 442bba95227SKonrad Dybcio opp-hz = /bits/ 64 <979200000>; 443bba95227SKonrad Dybcio opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 444bba95227SKonrad Dybcio }; 445bba95227SKonrad Dybcio 446bba95227SKonrad Dybcio opp-1036800000 { 447bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1036800000>; 448bba95227SKonrad Dybcio opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 449bba95227SKonrad Dybcio }; 450bba95227SKonrad Dybcio 451bba95227SKonrad Dybcio opp-1248000000 { 452bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1248000000>; 453bba95227SKonrad Dybcio opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 454bba95227SKonrad Dybcio }; 455bba95227SKonrad Dybcio 456bba95227SKonrad Dybcio opp-1401600000 { 457bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1401600000>; 458bba95227SKonrad Dybcio opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 459bba95227SKonrad Dybcio }; 460bba95227SKonrad Dybcio 461bba95227SKonrad Dybcio opp-1555200000 { 462bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1555200000>; 463bba95227SKonrad Dybcio opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 464bba95227SKonrad Dybcio }; 465bba95227SKonrad Dybcio 466bba95227SKonrad Dybcio opp-1766400000 { 467bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1766400000>; 468bba95227SKonrad Dybcio opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 469bba95227SKonrad Dybcio }; 470bba95227SKonrad Dybcio 471bba95227SKonrad Dybcio opp-1900800000 { 472bba95227SKonrad Dybcio opp-hz = /bits/ 64 <1900800000>; 473bba95227SKonrad Dybcio opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 474bba95227SKonrad Dybcio }; 475bba95227SKonrad Dybcio 476bba95227SKonrad Dybcio opp-2073600000 { 477bba95227SKonrad Dybcio opp-hz = /bits/ 64 <2073600000>; 478bba95227SKonrad Dybcio opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 479bba95227SKonrad Dybcio }; 480bba95227SKonrad Dybcio }; 481bba95227SKonrad Dybcio 482b179f35bSLuca Weiss qup_opp_table: opp-table-qup { 483b179f35bSLuca Weiss compatible = "operating-points-v2"; 484b179f35bSLuca Weiss 485b179f35bSLuca Weiss opp-75000000 { 486b179f35bSLuca Weiss opp-hz = /bits/ 64 <75000000>; 487b179f35bSLuca Weiss required-opps = <&rpmhpd_opp_low_svs>; 488b179f35bSLuca Weiss }; 489b179f35bSLuca Weiss 490b179f35bSLuca Weiss opp-100000000 { 491b179f35bSLuca Weiss opp-hz = /bits/ 64 <100000000>; 492b179f35bSLuca Weiss required-opps = <&rpmhpd_opp_svs>; 493b179f35bSLuca Weiss }; 494b179f35bSLuca Weiss 495b179f35bSLuca Weiss opp-128000000 { 496b179f35bSLuca Weiss opp-hz = /bits/ 64 <128000000>; 497b179f35bSLuca Weiss required-opps = <&rpmhpd_opp_nom>; 498b179f35bSLuca Weiss }; 499b179f35bSLuca Weiss }; 500b179f35bSLuca Weiss 5015f82b9cdSKonrad Dybcio pmu { 5025f82b9cdSKonrad Dybcio compatible = "arm,armv8-pmuv3"; 5035f82b9cdSKonrad Dybcio interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 5045f82b9cdSKonrad Dybcio }; 5055f82b9cdSKonrad Dybcio 5065f82b9cdSKonrad Dybcio psci { 5075f82b9cdSKonrad Dybcio compatible = "arm,psci-1.0"; 5085f82b9cdSKonrad Dybcio method = "smc"; 509ade89bc0SKonrad Dybcio 510b0864ab2SKrzysztof Kozlowski cpu_pd0: power-domain-cpu0 { 511ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 512b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 513b0864ab2SKrzysztof Kozlowski domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 514ade89bc0SKonrad Dybcio }; 515ade89bc0SKonrad Dybcio 516b0864ab2SKrzysztof Kozlowski cpu_pd1: power-domain-cpu1 { 517ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 518b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 519b0864ab2SKrzysztof Kozlowski domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 520ade89bc0SKonrad Dybcio }; 521ade89bc0SKonrad Dybcio 522b0864ab2SKrzysztof Kozlowski cpu_pd2: power-domain-cpu2 { 523ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 524b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 525b0864ab2SKrzysztof Kozlowski domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 526ade89bc0SKonrad Dybcio }; 527ade89bc0SKonrad Dybcio 528b0864ab2SKrzysztof Kozlowski cpu_pd3: power-domain-cpu3 { 529ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 530b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 531b0864ab2SKrzysztof Kozlowski domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 532ade89bc0SKonrad Dybcio }; 533ade89bc0SKonrad Dybcio 534b0864ab2SKrzysztof Kozlowski cpu_pd4: power-domain-cpu4 { 535ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 536b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 537b0864ab2SKrzysztof Kozlowski domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 538ade89bc0SKonrad Dybcio }; 539ade89bc0SKonrad Dybcio 540b0864ab2SKrzysztof Kozlowski cpu_pd5: power-domain-cpu5 { 541ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 542b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 543b0864ab2SKrzysztof Kozlowski domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 544ade89bc0SKonrad Dybcio }; 545ade89bc0SKonrad Dybcio 546b0864ab2SKrzysztof Kozlowski cpu_pd6: power-domain-cpu6 { 547ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 548b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 549b0864ab2SKrzysztof Kozlowski domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 550ade89bc0SKonrad Dybcio }; 551ade89bc0SKonrad Dybcio 552b0864ab2SKrzysztof Kozlowski cpu_pd7: power-domain-cpu7 { 553ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 554b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 555b0864ab2SKrzysztof Kozlowski domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 556ade89bc0SKonrad Dybcio }; 557ade89bc0SKonrad Dybcio 558b0864ab2SKrzysztof Kozlowski cluster_pd: power-domain-cpu-cluster0 { 559ade89bc0SKonrad Dybcio #power-domain-cells = <0>; 560b0864ab2SKrzysztof Kozlowski domain-idle-states = <&cluster_sleep_pc 561b0864ab2SKrzysztof Kozlowski &cluster_sleep_cx_ret 562b0864ab2SKrzysztof Kozlowski &cluster_aoss_sleep>; 563ade89bc0SKonrad Dybcio }; 5645f82b9cdSKonrad Dybcio }; 5655f82b9cdSKonrad Dybcio 5665f82b9cdSKonrad Dybcio reserved_memory: reserved-memory { 5675f82b9cdSKonrad Dybcio #address-cells = <2>; 5685f82b9cdSKonrad Dybcio #size-cells = <2>; 5695f82b9cdSKonrad Dybcio ranges; 5705f82b9cdSKonrad Dybcio 5715f82b9cdSKonrad Dybcio hyp_mem: memory@80000000 { 572a0a287b4SLuca Weiss reg = <0x0 0x80000000 0x0 0x600000>; 5735f82b9cdSKonrad Dybcio no-map; 5745f82b9cdSKonrad Dybcio }; 5755f82b9cdSKonrad Dybcio 5765f82b9cdSKonrad Dybcio xbl_aop_mem: memory@80700000 { 577a0a287b4SLuca Weiss reg = <0x0 0x80700000 0x0 0x160000>; 5785f82b9cdSKonrad Dybcio no-map; 5795f82b9cdSKonrad Dybcio }; 5805f82b9cdSKonrad Dybcio 5815f82b9cdSKonrad Dybcio cmd_db: memory@80860000 { 5825f82b9cdSKonrad Dybcio compatible = "qcom,cmd-db"; 583a0a287b4SLuca Weiss reg = <0x0 0x80860000 0x0 0x20000>; 5845f82b9cdSKonrad Dybcio no-map; 5855f82b9cdSKonrad Dybcio }; 5865f82b9cdSKonrad Dybcio 5875f82b9cdSKonrad Dybcio sec_apps_mem: memory@808ff000 { 588a0a287b4SLuca Weiss reg = <0x0 0x808ff000 0x0 0x1000>; 5895f82b9cdSKonrad Dybcio no-map; 5905f82b9cdSKonrad Dybcio }; 5915f82b9cdSKonrad Dybcio 5925f82b9cdSKonrad Dybcio smem_mem: memory@80900000 { 593a0a287b4SLuca Weiss reg = <0x0 0x80900000 0x0 0x200000>; 5945f82b9cdSKonrad Dybcio no-map; 5955f82b9cdSKonrad Dybcio }; 5965f82b9cdSKonrad Dybcio 5975f82b9cdSKonrad Dybcio cdsp_sec_mem: memory@80b00000 { 598a0a287b4SLuca Weiss reg = <0x0 0x80b00000 0x0 0x1e00000>; 5995f82b9cdSKonrad Dybcio no-map; 6005f82b9cdSKonrad Dybcio }; 6015f82b9cdSKonrad Dybcio 6025f82b9cdSKonrad Dybcio pil_camera_mem: memory@86000000 { 603a0a287b4SLuca Weiss reg = <0x0 0x86000000 0x0 0x500000>; 6045f82b9cdSKonrad Dybcio no-map; 6055f82b9cdSKonrad Dybcio }; 6065f82b9cdSKonrad Dybcio 6075f82b9cdSKonrad Dybcio pil_npu_mem: memory@86500000 { 608a0a287b4SLuca Weiss reg = <0x0 0x86500000 0x0 0x500000>; 6095f82b9cdSKonrad Dybcio no-map; 6105f82b9cdSKonrad Dybcio }; 6115f82b9cdSKonrad Dybcio 6125f82b9cdSKonrad Dybcio pil_video_mem: memory@86a00000 { 613a0a287b4SLuca Weiss reg = <0x0 0x86a00000 0x0 0x500000>; 6145f82b9cdSKonrad Dybcio no-map; 6155f82b9cdSKonrad Dybcio }; 6165f82b9cdSKonrad Dybcio 6175f82b9cdSKonrad Dybcio pil_cdsp_mem: memory@86f00000 { 618a0a287b4SLuca Weiss reg = <0x0 0x86f00000 0x0 0x1e00000>; 6195f82b9cdSKonrad Dybcio no-map; 6205f82b9cdSKonrad Dybcio }; 6215f82b9cdSKonrad Dybcio 6225f82b9cdSKonrad Dybcio pil_adsp_mem: memory@88d00000 { 623a0a287b4SLuca Weiss reg = <0x0 0x88d00000 0x0 0x2800000>; 6245f82b9cdSKonrad Dybcio no-map; 6255f82b9cdSKonrad Dybcio }; 6265f82b9cdSKonrad Dybcio 6275f82b9cdSKonrad Dybcio wlan_fw_mem: memory@8b500000 { 628a0a287b4SLuca Weiss reg = <0x0 0x8b500000 0x0 0x200000>; 6295f82b9cdSKonrad Dybcio no-map; 6305f82b9cdSKonrad Dybcio }; 6315f82b9cdSKonrad Dybcio 6325f82b9cdSKonrad Dybcio pil_ipa_fw_mem: memory@8b700000 { 633a0a287b4SLuca Weiss reg = <0x0 0x8b700000 0x0 0x10000>; 6345f82b9cdSKonrad Dybcio no-map; 6355f82b9cdSKonrad Dybcio }; 6365f82b9cdSKonrad Dybcio 6375f82b9cdSKonrad Dybcio pil_ipa_gsi_mem: memory@8b710000 { 638a0a287b4SLuca Weiss reg = <0x0 0x8b710000 0x0 0x5400>; 6395f82b9cdSKonrad Dybcio no-map; 6405f82b9cdSKonrad Dybcio }; 6415f82b9cdSKonrad Dybcio 6425f82b9cdSKonrad Dybcio pil_modem_mem: memory@8b800000 { 643a0a287b4SLuca Weiss reg = <0x0 0x8b800000 0x0 0xf800000>; 6445f82b9cdSKonrad Dybcio no-map; 6455f82b9cdSKonrad Dybcio }; 6465f82b9cdSKonrad Dybcio 6475f82b9cdSKonrad Dybcio cont_splash_memory: memory@a0000000 { 648a0a287b4SLuca Weiss reg = <0x0 0xa0000000 0x0 0x2300000>; 6495f82b9cdSKonrad Dybcio no-map; 6505f82b9cdSKonrad Dybcio }; 6515f82b9cdSKonrad Dybcio 6525f82b9cdSKonrad Dybcio dfps_data_memory: memory@a2300000 { 653a0a287b4SLuca Weiss reg = <0x0 0xa2300000 0x0 0x100000>; 6545f82b9cdSKonrad Dybcio no-map; 6555f82b9cdSKonrad Dybcio }; 6565f82b9cdSKonrad Dybcio 6575f82b9cdSKonrad Dybcio removed_region: memory@c0000000 { 658a0a287b4SLuca Weiss reg = <0x0 0xc0000000 0x0 0x3900000>; 6595f82b9cdSKonrad Dybcio no-map; 6605f82b9cdSKonrad Dybcio }; 6615f82b9cdSKonrad Dybcio 66244bcded2SKonrad Dybcio pil_gpu_mem: memory@f0d00000 { 663a0a287b4SLuca Weiss reg = <0x0 0xf0d00000 0x0 0x1000>; 66444bcded2SKonrad Dybcio no-map; 66544bcded2SKonrad Dybcio }; 66644bcded2SKonrad Dybcio 6675f82b9cdSKonrad Dybcio debug_region: memory@ffb00000 { 668a0a287b4SLuca Weiss reg = <0x0 0xffb00000 0x0 0xc0000>; 6695f82b9cdSKonrad Dybcio no-map; 6705f82b9cdSKonrad Dybcio }; 6715f82b9cdSKonrad Dybcio 6725f82b9cdSKonrad Dybcio last_log_region: memory@ffbc0000 { 673a0a287b4SLuca Weiss reg = <0x0 0xffbc0000 0x0 0x40000>; 6745f82b9cdSKonrad Dybcio no-map; 6755f82b9cdSKonrad Dybcio }; 6765f82b9cdSKonrad Dybcio 6775f82b9cdSKonrad Dybcio ramoops: ramoops@ffc00000 { 6783b2ff50dSKonrad Dybcio compatible = "ramoops"; 679a0a287b4SLuca Weiss reg = <0x0 0xffc00000 0x0 0x100000>; 6805f82b9cdSKonrad Dybcio record-size = <0x1000>; 6815f82b9cdSKonrad Dybcio console-size = <0x40000>; 682c86b97a7SKrzysztof Kozlowski pmsg-size = <0x20000>; 6833b2ff50dSKonrad Dybcio ecc-size = <16>; 6845f82b9cdSKonrad Dybcio no-map; 6855f82b9cdSKonrad Dybcio }; 6865f82b9cdSKonrad Dybcio 6875f82b9cdSKonrad Dybcio cmdline_region: memory@ffd00000 { 688a0a287b4SLuca Weiss reg = <0x0 0xffd00000 0x0 0x1000>; 6895f82b9cdSKonrad Dybcio no-map; 6905f82b9cdSKonrad Dybcio }; 6915f82b9cdSKonrad Dybcio }; 6925f82b9cdSKonrad Dybcio 6935f82b9cdSKonrad Dybcio smem { 6945f82b9cdSKonrad Dybcio compatible = "qcom,smem"; 6955f82b9cdSKonrad Dybcio memory-region = <&smem_mem>; 6965f82b9cdSKonrad Dybcio hwlocks = <&tcsr_mutex 3>; 6975f82b9cdSKonrad Dybcio }; 6985f82b9cdSKonrad Dybcio 699efc33c96SLuca Weiss smp2p-adsp { 700efc33c96SLuca Weiss compatible = "qcom,smp2p"; 701efc33c96SLuca Weiss qcom,smem = <443>, <429>; 702efc33c96SLuca Weiss interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 703efc33c96SLuca Weiss IPCC_MPROC_SIGNAL_SMP2P 704efc33c96SLuca Weiss IRQ_TYPE_EDGE_RISING>; 705efc33c96SLuca Weiss mboxes = <&ipcc IPCC_CLIENT_LPASS 706efc33c96SLuca Weiss IPCC_MPROC_SIGNAL_SMP2P>; 707efc33c96SLuca Weiss 708efc33c96SLuca Weiss qcom,local-pid = <0>; 709efc33c96SLuca Weiss qcom,remote-pid = <2>; 710efc33c96SLuca Weiss 711efc33c96SLuca Weiss smp2p_adsp_out: master-kernel { 712efc33c96SLuca Weiss qcom,entry-name = "master-kernel"; 713efc33c96SLuca Weiss #qcom,smem-state-cells = <1>; 714efc33c96SLuca Weiss }; 715efc33c96SLuca Weiss 716efc33c96SLuca Weiss smp2p_adsp_in: slave-kernel { 717efc33c96SLuca Weiss qcom,entry-name = "slave-kernel"; 718efc33c96SLuca Weiss interrupt-controller; 719efc33c96SLuca Weiss #interrupt-cells = <2>; 720efc33c96SLuca Weiss }; 721efc33c96SLuca Weiss }; 722efc33c96SLuca Weiss 7238eb5287eSLuca Weiss smp2p-cdsp { 7248eb5287eSLuca Weiss compatible = "qcom,smp2p"; 7258eb5287eSLuca Weiss qcom,smem = <94>, <432>; 7268eb5287eSLuca Weiss interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7278eb5287eSLuca Weiss IPCC_MPROC_SIGNAL_SMP2P 7288eb5287eSLuca Weiss IRQ_TYPE_EDGE_RISING>; 7298eb5287eSLuca Weiss mboxes = <&ipcc IPCC_CLIENT_CDSP 7308eb5287eSLuca Weiss IPCC_MPROC_SIGNAL_SMP2P>; 7318eb5287eSLuca Weiss 7328eb5287eSLuca Weiss qcom,local-pid = <0>; 7338eb5287eSLuca Weiss qcom,remote-pid = <5>; 7348eb5287eSLuca Weiss 7358eb5287eSLuca Weiss smp2p_cdsp_out: master-kernel { 7368eb5287eSLuca Weiss qcom,entry-name = "master-kernel"; 7378eb5287eSLuca Weiss #qcom,smem-state-cells = <1>; 7388eb5287eSLuca Weiss }; 7398eb5287eSLuca Weiss 7408eb5287eSLuca Weiss smp2p_cdsp_in: slave-kernel { 7418eb5287eSLuca Weiss qcom,entry-name = "slave-kernel"; 7428eb5287eSLuca Weiss interrupt-controller; 7438eb5287eSLuca Weiss #interrupt-cells = <2>; 7448eb5287eSLuca Weiss }; 7458eb5287eSLuca Weiss }; 7468eb5287eSLuca Weiss 747489be59bSLuca Weiss smp2p-mpss { 748489be59bSLuca Weiss compatible = "qcom,smp2p"; 749489be59bSLuca Weiss qcom,smem = <435>, <428>; 750489be59bSLuca Weiss 751489be59bSLuca Weiss interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 752489be59bSLuca Weiss IPCC_MPROC_SIGNAL_SMP2P 753489be59bSLuca Weiss IRQ_TYPE_EDGE_RISING>; 754489be59bSLuca Weiss mboxes = <&ipcc IPCC_CLIENT_MPSS 755489be59bSLuca Weiss IPCC_MPROC_SIGNAL_SMP2P>; 756489be59bSLuca Weiss 757489be59bSLuca Weiss qcom,local-pid = <0>; 758489be59bSLuca Weiss qcom,remote-pid = <1>; 759489be59bSLuca Weiss 760489be59bSLuca Weiss modem_smp2p_out: master-kernel { 761489be59bSLuca Weiss qcom,entry-name = "master-kernel"; 762489be59bSLuca Weiss #qcom,smem-state-cells = <1>; 763489be59bSLuca Weiss }; 764489be59bSLuca Weiss 765489be59bSLuca Weiss modem_smp2p_in: slave-kernel { 766489be59bSLuca Weiss qcom,entry-name = "slave-kernel"; 767aed7154aSLuca Weiss interrupt-controller; 768aed7154aSLuca Weiss #interrupt-cells = <2>; 769aed7154aSLuca Weiss }; 770489be59bSLuca Weiss 771aed7154aSLuca Weiss ipa_smp2p_out: ipa-ap-to-modem { 772aed7154aSLuca Weiss qcom,entry-name = "ipa"; 773aed7154aSLuca Weiss #qcom,smem-state-cells = <1>; 774aed7154aSLuca Weiss }; 775aed7154aSLuca Weiss 776aed7154aSLuca Weiss ipa_smp2p_in: ipa-modem-to-ap { 777aed7154aSLuca Weiss qcom,entry-name = "ipa"; 778489be59bSLuca Weiss interrupt-controller; 779489be59bSLuca Weiss #interrupt-cells = <2>; 780489be59bSLuca Weiss }; 781489be59bSLuca Weiss }; 782489be59bSLuca Weiss 7835f82b9cdSKonrad Dybcio soc: soc@0 { 7845f82b9cdSKonrad Dybcio #address-cells = <2>; 7855f82b9cdSKonrad Dybcio #size-cells = <2>; 7865f82b9cdSKonrad Dybcio ranges = <0 0 0 0 0x10 0>; 7875f82b9cdSKonrad Dybcio dma-ranges = <0 0 0 0 0x10 0>; 7885f82b9cdSKonrad Dybcio compatible = "simple-bus"; 7895f82b9cdSKonrad Dybcio 79030de1108SKonrad Dybcio gcc: clock-controller@100000 { 79130de1108SKonrad Dybcio compatible = "qcom,gcc-sm6350"; 792a0a287b4SLuca Weiss reg = <0x0 0x00100000 0x0 0x1f0000>; 79330de1108SKonrad Dybcio #clock-cells = <1>; 79430de1108SKonrad Dybcio #reset-cells = <1>; 79530de1108SKonrad Dybcio #power-domain-cells = <1>; 79630de1108SKonrad Dybcio clock-names = "bi_tcxo", 79730de1108SKonrad Dybcio "bi_tcxo_ao", 79830de1108SKonrad Dybcio "sleep_clk"; 79930de1108SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 80030de1108SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK_A>, 80130de1108SKonrad Dybcio <&sleep_clk>; 80230de1108SKonrad Dybcio }; 80330de1108SKonrad Dybcio 8045f82b9cdSKonrad Dybcio ipcc: mailbox@408000 { 8055f82b9cdSKonrad Dybcio compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 806a0a287b4SLuca Weiss reg = <0x0 0x00408000 0x0 0x1000>; 8075f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 8085f82b9cdSKonrad Dybcio interrupt-controller; 8095f82b9cdSKonrad Dybcio #interrupt-cells = <3>; 8105f82b9cdSKonrad Dybcio #mbox-cells = <2>; 8115f82b9cdSKonrad Dybcio }; 8125f82b9cdSKonrad Dybcio 8135b1e5d9aSKonrad Dybcio qfprom: qfprom@784000 { 8145b1e5d9aSKonrad Dybcio compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 815a0a287b4SLuca Weiss reg = <0x0 0x00784000 0x0 0x3000>; 8165b1e5d9aSKonrad Dybcio #address-cells = <1>; 8175b1e5d9aSKonrad Dybcio #size-cells = <1>; 8185b1e5d9aSKonrad Dybcio 8195b1e5d9aSKonrad Dybcio gpu_speed_bin: gpu-speed-bin@2015 { 8205b1e5d9aSKonrad Dybcio reg = <0x2015 0x1>; 8215b1e5d9aSKonrad Dybcio bits = <0 8>; 8225b1e5d9aSKonrad Dybcio }; 8235b1e5d9aSKonrad Dybcio }; 8245b1e5d9aSKonrad Dybcio 825574af545SKonrad Dybcio rng: rng@793000 { 826574af545SKonrad Dybcio compatible = "qcom,prng-ee"; 827a0a287b4SLuca Weiss reg = <0x0 0x00793000 0x0 0x1000>; 828574af545SKonrad Dybcio clocks = <&gcc GCC_PRNG_AHB_CLK>; 829574af545SKonrad Dybcio clock-names = "core"; 830574af545SKonrad Dybcio }; 831574af545SKonrad Dybcio 83296bb736fSBhupesh Sharma sdhc_1: mmc@7c4000 { 8331797e1c9SKonrad Dybcio compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 834a0a287b4SLuca Weiss reg = <0x0 0x007c4000 0x0 0x1000>, 835a0a287b4SLuca Weiss <0x0 0x007c5000 0x0 0x1000>, 836a0a287b4SLuca Weiss <0x0 0x007c8000 0x0 0x8000>; 83721857088SDouglas Anderson reg-names = "hc", "cqhci", "ice"; 8381797e1c9SKonrad Dybcio 8391797e1c9SKonrad Dybcio interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 8401797e1c9SKonrad Dybcio <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 8411797e1c9SKonrad Dybcio interrupt-names = "hc_irq", "pwr_irq"; 8427372b944SMarijn Suijten iommus = <&apps_smmu 0x60 0x0>; 8431797e1c9SKonrad Dybcio 8441797e1c9SKonrad Dybcio clocks = <&gcc GCC_SDCC1_AHB_CLK>, 8451797e1c9SKonrad Dybcio <&gcc GCC_SDCC1_APPS_CLK>, 8461797e1c9SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 8471797e1c9SKonrad Dybcio clock-names = "iface", "core", "xo"; 848e10d451eSMarijn Suijten resets = <&gcc GCC_SDCC1_BCR>; 8491797e1c9SKonrad Dybcio qcom,dll-config = <0x000f642c>; 8501797e1c9SKonrad Dybcio qcom,ddr-config = <0x80040868>; 8517a9016dbSMarijn Suijten power-domains = <&rpmhpd SM6350_CX>; 8521797e1c9SKonrad Dybcio operating-points-v2 = <&sdhc1_opp_table>; 8531797e1c9SKonrad Dybcio bus-width = <8>; 8541797e1c9SKonrad Dybcio non-removable; 8551797e1c9SKonrad Dybcio supports-cqe; 8561797e1c9SKonrad Dybcio 8571797e1c9SKonrad Dybcio status = "disabled"; 8581797e1c9SKonrad Dybcio 8590e3e6546SKrzysztof Kozlowski sdhc1_opp_table: opp-table { 8601797e1c9SKonrad Dybcio compatible = "operating-points-v2"; 8611797e1c9SKonrad Dybcio 8621797e1c9SKonrad Dybcio opp-19200000 { 8631797e1c9SKonrad Dybcio opp-hz = /bits/ 64 <19200000>; 8641797e1c9SKonrad Dybcio required-opps = <&rpmhpd_opp_min_svs>; 8651797e1c9SKonrad Dybcio }; 8661797e1c9SKonrad Dybcio 8671797e1c9SKonrad Dybcio opp-100000000 { 8681797e1c9SKonrad Dybcio opp-hz = /bits/ 64 <100000000>; 8691797e1c9SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 8701797e1c9SKonrad Dybcio }; 8711797e1c9SKonrad Dybcio 8721797e1c9SKonrad Dybcio opp-384000000 { 8731797e1c9SKonrad Dybcio opp-hz = /bits/ 64 <384000000>; 8741797e1c9SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 8751797e1c9SKonrad Dybcio }; 8761797e1c9SKonrad Dybcio }; 8771797e1c9SKonrad Dybcio }; 8781797e1c9SKonrad Dybcio 8799f0149caSLuca Weiss gpi_dma0: dma-controller@800000 { 8809f0149caSLuca Weiss compatible = "qcom,sm6350-gpi-dma"; 881a0a287b4SLuca Weiss reg = <0x0 0x00800000 0x0 0x60000>; 8829f0149caSLuca Weiss interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 8839f0149caSLuca Weiss <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 8849f0149caSLuca Weiss <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 8859f0149caSLuca Weiss <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 8869f0149caSLuca Weiss <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 8879f0149caSLuca Weiss <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 8889f0149caSLuca Weiss <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 8899f0149caSLuca Weiss <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 8909f0149caSLuca Weiss <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 8919f0149caSLuca Weiss <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 8929f0149caSLuca Weiss dma-channels = <10>; 8939f0149caSLuca Weiss dma-channel-mask = <0x1f>; 8949f0149caSLuca Weiss iommus = <&apps_smmu 0x56 0x0>; 8959f0149caSLuca Weiss #dma-cells = <3>; 8969f0149caSLuca Weiss status = "disabled"; 8979f0149caSLuca Weiss }; 8989f0149caSLuca Weiss 8997be9f3aeSLuca Weiss qupv3_id_0: geniqup@8c0000 { 9007be9f3aeSLuca Weiss compatible = "qcom,geni-se-qup"; 901f48dbb34SKonrad Dybcio reg = <0x0 0x008c0000 0x0 0x2000>; 9027be9f3aeSLuca Weiss clock-names = "m-ahb", "s-ahb"; 9037be9f3aeSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9047be9f3aeSLuca Weiss <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9057be9f3aeSLuca Weiss #address-cells = <2>; 9067be9f3aeSLuca Weiss #size-cells = <2>; 9077be9f3aeSLuca Weiss iommus = <&apps_smmu 0x43 0x0>; 9087be9f3aeSLuca Weiss ranges; 9097be9f3aeSLuca Weiss status = "disabled"; 9107be9f3aeSLuca Weiss 9117be9f3aeSLuca Weiss i2c0: i2c@880000 { 9127be9f3aeSLuca Weiss compatible = "qcom,geni-i2c"; 913a0a287b4SLuca Weiss reg = <0x0 0x00880000 0x0 0x4000>; 9147be9f3aeSLuca Weiss clock-names = "se"; 9157be9f3aeSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 9167be9f3aeSLuca Weiss pinctrl-names = "default"; 9177be9f3aeSLuca Weiss pinctrl-0 = <&qup_i2c0_default>; 9187be9f3aeSLuca Weiss interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 9199f0149caSLuca Weiss dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 9209f0149caSLuca Weiss <&gpi_dma0 1 0 QCOM_GPI_I2C>; 9219f0149caSLuca Weiss dma-names = "tx", "rx"; 9227be9f3aeSLuca Weiss #address-cells = <1>; 9237be9f3aeSLuca Weiss #size-cells = <0>; 92438c5c4feSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 92538c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 92638c5c4feSLuca Weiss <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 92738c5c4feSLuca Weiss interconnect-names = "qup-core", "qup-config", "qup-memory"; 9287be9f3aeSLuca Weiss status = "disabled"; 9297be9f3aeSLuca Weiss }; 9307be9f3aeSLuca Weiss 931b179f35bSLuca Weiss uart1: serial@884000 { 932b179f35bSLuca Weiss compatible = "qcom,geni-uart"; 933a0a287b4SLuca Weiss reg = <0x0 0x00884000 0x0 0x4000>; 934b179f35bSLuca Weiss clock-names = "se"; 935b179f35bSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 936b179f35bSLuca Weiss pinctrl-names = "default"; 937b179f35bSLuca Weiss pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 938b179f35bSLuca Weiss interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 939b179f35bSLuca Weiss power-domains = <&rpmhpd SM6350_CX>; 940b179f35bSLuca Weiss operating-points-v2 = <&qup_opp_table>; 941b179f35bSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942be2f81eaSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 943b179f35bSLuca Weiss interconnect-names = "qup-core", "qup-config"; 944b179f35bSLuca Weiss status = "disabled"; 945b179f35bSLuca Weiss }; 946b179f35bSLuca Weiss 9477be9f3aeSLuca Weiss i2c2: i2c@888000 { 9487be9f3aeSLuca Weiss compatible = "qcom,geni-i2c"; 949a0a287b4SLuca Weiss reg = <0x0 0x00888000 0x0 0x4000>; 9507be9f3aeSLuca Weiss clock-names = "se"; 9517be9f3aeSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 9527be9f3aeSLuca Weiss pinctrl-names = "default"; 9537be9f3aeSLuca Weiss pinctrl-0 = <&qup_i2c2_default>; 9547be9f3aeSLuca Weiss interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 9559f0149caSLuca Weiss dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 9569f0149caSLuca Weiss <&gpi_dma0 1 2 QCOM_GPI_I2C>; 9579f0149caSLuca Weiss dma-names = "tx", "rx"; 9587be9f3aeSLuca Weiss #address-cells = <1>; 9597be9f3aeSLuca Weiss #size-cells = <0>; 96038c5c4feSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 96138c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 96238c5c4feSLuca Weiss <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 96338c5c4feSLuca Weiss interconnect-names = "qup-core", "qup-config", "qup-memory"; 9647be9f3aeSLuca Weiss status = "disabled"; 9657be9f3aeSLuca Weiss }; 9667be9f3aeSLuca Weiss }; 9677be9f3aeSLuca Weiss 9689f0149caSLuca Weiss gpi_dma1: dma-controller@900000 { 9699f0149caSLuca Weiss compatible = "qcom,sm6350-gpi-dma"; 970a0a287b4SLuca Weiss reg = <0x0 0x00900000 0x0 0x60000>; 9719f0149caSLuca Weiss interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 9729f0149caSLuca Weiss <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 9739f0149caSLuca Weiss <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 9749f0149caSLuca Weiss <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 9759f0149caSLuca Weiss <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 9769f0149caSLuca Weiss <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 9779f0149caSLuca Weiss <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 9789f0149caSLuca Weiss <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 9799f0149caSLuca Weiss <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 9809f0149caSLuca Weiss <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 9819f0149caSLuca Weiss dma-channels = <10>; 9829f0149caSLuca Weiss dma-channel-mask = <0x3f>; 9839f0149caSLuca Weiss iommus = <&apps_smmu 0x4d6 0x0>; 9849f0149caSLuca Weiss #dma-cells = <3>; 9859f0149caSLuca Weiss status = "disabled"; 9869f0149caSLuca Weiss }; 9879f0149caSLuca Weiss 988cd10fb79SLuca Weiss qupv3_id_1: geniqup@9c0000 { 989cd10fb79SLuca Weiss compatible = "qcom,geni-se-qup"; 990f48dbb34SKonrad Dybcio reg = <0x0 0x009c0000 0x0 0x2000>; 991cd10fb79SLuca Weiss clock-names = "m-ahb", "s-ahb"; 992cd10fb79SLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 993cd10fb79SLuca Weiss <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 994cd10fb79SLuca Weiss #address-cells = <2>; 995cd10fb79SLuca Weiss #size-cells = <2>; 996cd10fb79SLuca Weiss iommus = <&apps_smmu 0x4c3 0x0>; 997cd10fb79SLuca Weiss ranges; 998cd10fb79SLuca Weiss status = "disabled"; 999cd10fb79SLuca Weiss 10007be9f3aeSLuca Weiss i2c6: i2c@980000 { 10017be9f3aeSLuca Weiss compatible = "qcom,geni-i2c"; 1002a0a287b4SLuca Weiss reg = <0x0 0x00980000 0x0 0x4000>; 10037be9f3aeSLuca Weiss clock-names = "se"; 10047be9f3aeSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 10057be9f3aeSLuca Weiss pinctrl-names = "default"; 10067be9f3aeSLuca Weiss pinctrl-0 = <&qup_i2c6_default>; 10077be9f3aeSLuca Weiss interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 10089f0149caSLuca Weiss dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 10099f0149caSLuca Weiss <&gpi_dma1 1 0 QCOM_GPI_I2C>; 10109f0149caSLuca Weiss dma-names = "tx", "rx"; 10117be9f3aeSLuca Weiss #address-cells = <1>; 10127be9f3aeSLuca Weiss #size-cells = <0>; 101338c5c4feSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 101438c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 101538c5c4feSLuca Weiss <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 101638c5c4feSLuca Weiss interconnect-names = "qup-core", "qup-config", "qup-memory"; 10177be9f3aeSLuca Weiss status = "disabled"; 10187be9f3aeSLuca Weiss }; 10197be9f3aeSLuca Weiss 10207be9f3aeSLuca Weiss i2c7: i2c@984000 { 10217be9f3aeSLuca Weiss compatible = "qcom,geni-i2c"; 1022a0a287b4SLuca Weiss reg = <0x0 0x00984000 0x0 0x4000>; 10237be9f3aeSLuca Weiss clock-names = "se"; 10247be9f3aeSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 10257be9f3aeSLuca Weiss pinctrl-names = "default"; 10267be9f3aeSLuca Weiss pinctrl-0 = <&qup_i2c7_default>; 10277be9f3aeSLuca Weiss interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 10289f0149caSLuca Weiss dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 10299f0149caSLuca Weiss <&gpi_dma1 1 1 QCOM_GPI_I2C>; 10309f0149caSLuca Weiss dma-names = "tx", "rx"; 10317be9f3aeSLuca Weiss #address-cells = <1>; 10327be9f3aeSLuca Weiss #size-cells = <0>; 103338c5c4feSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 103438c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 103538c5c4feSLuca Weiss <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 103638c5c4feSLuca Weiss interconnect-names = "qup-core", "qup-config", "qup-memory"; 10377be9f3aeSLuca Weiss status = "disabled"; 10387be9f3aeSLuca Weiss }; 10397be9f3aeSLuca Weiss 10407be9f3aeSLuca Weiss i2c8: i2c@988000 { 10417be9f3aeSLuca Weiss compatible = "qcom,geni-i2c"; 1042a0a287b4SLuca Weiss reg = <0x0 0x00988000 0x0 0x4000>; 10437be9f3aeSLuca Weiss clock-names = "se"; 10447be9f3aeSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 10457be9f3aeSLuca Weiss pinctrl-names = "default"; 10467be9f3aeSLuca Weiss pinctrl-0 = <&qup_i2c8_default>; 10477be9f3aeSLuca Weiss interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 10489f0149caSLuca Weiss dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 10499f0149caSLuca Weiss <&gpi_dma1 1 2 QCOM_GPI_I2C>; 10509f0149caSLuca Weiss dma-names = "tx", "rx"; 10517be9f3aeSLuca Weiss #address-cells = <1>; 10527be9f3aeSLuca Weiss #size-cells = <0>; 105338c5c4feSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 105438c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 105538c5c4feSLuca Weiss <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 105638c5c4feSLuca Weiss interconnect-names = "qup-core", "qup-config", "qup-memory"; 10577be9f3aeSLuca Weiss status = "disabled"; 10587be9f3aeSLuca Weiss }; 10597be9f3aeSLuca Weiss 10609e5c45a5SLuca Weiss uart9: serial@98c000 { 1061cd10fb79SLuca Weiss compatible = "qcom,geni-debug-uart"; 1062a0a287b4SLuca Weiss reg = <0x0 0x0098c000 0x0 0x4000>; 1063cd10fb79SLuca Weiss clock-names = "se"; 1064cd10fb79SLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1065cd10fb79SLuca Weiss pinctrl-names = "default"; 10669e5c45a5SLuca Weiss pinctrl-0 = <&qup_uart9_default>; 1067cd10fb79SLuca Weiss interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 106838c5c4feSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 106938c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 107038c5c4feSLuca Weiss interconnect-names = "qup-core", "qup-config"; 1071cd10fb79SLuca Weiss status = "disabled"; 1072cd10fb79SLuca Weiss }; 10737be9f3aeSLuca Weiss 10747be9f3aeSLuca Weiss i2c10: i2c@990000 { 10757be9f3aeSLuca Weiss compatible = "qcom,geni-i2c"; 1076a0a287b4SLuca Weiss reg = <0x0 0x00990000 0x0 0x4000>; 10777be9f3aeSLuca Weiss clock-names = "se"; 10787be9f3aeSLuca Weiss clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 10797be9f3aeSLuca Weiss pinctrl-names = "default"; 10807be9f3aeSLuca Weiss pinctrl-0 = <&qup_i2c10_default>; 10817be9f3aeSLuca Weiss interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 10829f0149caSLuca Weiss dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 10839f0149caSLuca Weiss <&gpi_dma1 1 4 QCOM_GPI_I2C>; 10849f0149caSLuca Weiss dma-names = "tx", "rx"; 10857be9f3aeSLuca Weiss #address-cells = <1>; 10867be9f3aeSLuca Weiss #size-cells = <0>; 108738c5c4feSLuca Weiss interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 108838c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 108938c5c4feSLuca Weiss <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 109038c5c4feSLuca Weiss interconnect-names = "qup-core", "qup-config", "qup-memory"; 10917be9f3aeSLuca Weiss status = "disabled"; 10927be9f3aeSLuca Weiss }; 1093cd10fb79SLuca Weiss }; 1094cd10fb79SLuca Weiss 109538c5c4feSLuca Weiss config_noc: interconnect@1500000 { 109638c5c4feSLuca Weiss compatible = "qcom,sm6350-config-noc"; 1097a0a287b4SLuca Weiss reg = <0x0 0x01500000 0x0 0x28000>; 109838c5c4feSLuca Weiss #interconnect-cells = <2>; 109938c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 110038c5c4feSLuca Weiss }; 110138c5c4feSLuca Weiss 110238c5c4feSLuca Weiss system_noc: interconnect@1620000 { 110338c5c4feSLuca Weiss compatible = "qcom,sm6350-system-noc"; 1104a0a287b4SLuca Weiss reg = <0x0 0x01620000 0x0 0x17080>; 110538c5c4feSLuca Weiss #interconnect-cells = <2>; 110638c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 110738c5c4feSLuca Weiss 110838c5c4feSLuca Weiss clk_virt: interconnect-clk-virt { 110938c5c4feSLuca Weiss compatible = "qcom,sm6350-clk-virt"; 111038c5c4feSLuca Weiss #interconnect-cells = <2>; 111138c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 111238c5c4feSLuca Weiss }; 111338c5c4feSLuca Weiss }; 111438c5c4feSLuca Weiss 111538c5c4feSLuca Weiss aggre1_noc: interconnect@16e0000 { 111638c5c4feSLuca Weiss compatible = "qcom,sm6350-aggre1-noc"; 1117a0a287b4SLuca Weiss reg = <0x0 0x016e0000 0x0 0x15080>; 111838c5c4feSLuca Weiss #interconnect-cells = <2>; 111938c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 112038c5c4feSLuca Weiss }; 112138c5c4feSLuca Weiss 112238c5c4feSLuca Weiss aggre2_noc: interconnect@1700000 { 112338c5c4feSLuca Weiss compatible = "qcom,sm6350-aggre2-noc"; 1124a0a287b4SLuca Weiss reg = <0x0 0x01700000 0x0 0x1f880>; 112538c5c4feSLuca Weiss #interconnect-cells = <2>; 112638c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 112738c5c4feSLuca Weiss 112838c5c4feSLuca Weiss compute_noc: interconnect-compute-noc { 112938c5c4feSLuca Weiss compatible = "qcom,sm6350-compute-noc"; 113038c5c4feSLuca Weiss #interconnect-cells = <2>; 113138c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 113238c5c4feSLuca Weiss }; 113338c5c4feSLuca Weiss }; 113438c5c4feSLuca Weiss 113538c5c4feSLuca Weiss mmss_noc: interconnect@1740000 { 113638c5c4feSLuca Weiss compatible = "qcom,sm6350-mmss-noc"; 1137a0a287b4SLuca Weiss reg = <0x0 0x01740000 0x0 0x1c100>; 113838c5c4feSLuca Weiss #interconnect-cells = <2>; 113938c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 114038c5c4feSLuca Weiss }; 114138c5c4feSLuca Weiss 114215288649SManivannan Sadhasivam ufs_mem_hc: ufshc@1d84000 { 11435a814af5SLuca Weiss compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 11445a814af5SLuca Weiss "jedec,ufs-2.0"; 1145a0a287b4SLuca Weiss reg = <0x0 0x01d84000 0x0 0x3000>, 1146a0a287b4SLuca Weiss <0x0 0x01d90000 0x0 0x8000>; 11475a814af5SLuca Weiss reg-names = "std", "ice"; 11485a814af5SLuca Weiss interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 11498e89beb3SDmitry Baryshkov phys = <&ufs_mem_phy>; 11505a814af5SLuca Weiss phy-names = "ufsphy"; 11515a814af5SLuca Weiss lanes-per-direction = <2>; 11525a814af5SLuca Weiss #reset-cells = <1>; 11535a814af5SLuca Weiss resets = <&gcc GCC_UFS_PHY_BCR>; 11545a814af5SLuca Weiss reset-names = "rst"; 11555a814af5SLuca Weiss 11565a814af5SLuca Weiss power-domains = <&gcc UFS_PHY_GDSC>; 11575a814af5SLuca Weiss 11585a814af5SLuca Weiss iommus = <&apps_smmu 0x80 0x0>; 11595a814af5SLuca Weiss 11605a814af5SLuca Weiss clock-names = "core_clk", 11615a814af5SLuca Weiss "bus_aggr_clk", 11625a814af5SLuca Weiss "iface_clk", 11635a814af5SLuca Weiss "core_clk_unipro", 11645a814af5SLuca Weiss "ref_clk", 11655a814af5SLuca Weiss "tx_lane0_sync_clk", 11665a814af5SLuca Weiss "rx_lane0_sync_clk", 11675a814af5SLuca Weiss "rx_lane1_sync_clk", 11685a814af5SLuca Weiss "ice_core_clk"; 11695a814af5SLuca Weiss clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 11705a814af5SLuca Weiss <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 11715a814af5SLuca Weiss <&gcc GCC_UFS_PHY_AHB_CLK>, 11725a814af5SLuca Weiss <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 11735a814af5SLuca Weiss <&rpmhcc RPMH_QLINK_CLK>, 11745a814af5SLuca Weiss <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 11755a814af5SLuca Weiss <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 11765a814af5SLuca Weiss <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 11775a814af5SLuca Weiss <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 11785a814af5SLuca Weiss freq-table-hz = 11795a814af5SLuca Weiss <50000000 200000000>, 11805a814af5SLuca Weiss <0 0>, 11815a814af5SLuca Weiss <0 0>, 11825a814af5SLuca Weiss <37500000 150000000>, 11835a814af5SLuca Weiss <75000000 300000000>, 11845a814af5SLuca Weiss <0 0>, 11855a814af5SLuca Weiss <0 0>, 11865a814af5SLuca Weiss <0 0>, 11875a814af5SLuca Weiss <0 0>; 11885a814af5SLuca Weiss 11895a814af5SLuca Weiss status = "disabled"; 11905a814af5SLuca Weiss }; 11915a814af5SLuca Weiss 11925a814af5SLuca Weiss ufs_mem_phy: phy@1d87000 { 11935a814af5SLuca Weiss compatible = "qcom,sm6350-qmp-ufs-phy"; 1194a0a287b4SLuca Weiss reg = <0x0 0x01d87000 0x0 0x1000>; 11955a814af5SLuca Weiss 119668f9fcbaSManivannan Sadhasivam clocks = <&rpmhcc RPMH_CXO_CLK>, 119768f9fcbaSManivannan Sadhasivam <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 119868f9fcbaSManivannan Sadhasivam <&gcc GCC_UFS_MEM_CLKREF_CLK>; 11995a814af5SLuca Weiss clock-names = "ref", 120068f9fcbaSManivannan Sadhasivam "ref_aux", 120168f9fcbaSManivannan Sadhasivam "qref"; 12025a814af5SLuca Weiss 120318c27272SDmitry Baryshkov power-domains = <&gcc UFS_PHY_GDSC>; 120418c27272SDmitry Baryshkov 12055a814af5SLuca Weiss resets = <&ufs_mem_hc 0>; 12065a814af5SLuca Weiss reset-names = "ufsphy"; 12075a814af5SLuca Weiss 12085a814af5SLuca Weiss #phy-cells = <0>; 12098e89beb3SDmitry Baryshkov 12108e89beb3SDmitry Baryshkov status = "disabled"; 12115a814af5SLuca Weiss }; 12125a814af5SLuca Weiss 1213fd5afa5dSLuca Weiss cryptobam: dma-controller@1dc4000 { 1214fd5afa5dSLuca Weiss compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1215a0a287b4SLuca Weiss reg = <0x0 0x01dc4000 0x0 0x24000>; 1216fd5afa5dSLuca Weiss interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1217fd5afa5dSLuca Weiss #dma-cells = <1>; 1218fd5afa5dSLuca Weiss qcom,ee = <0>; 1219fd5afa5dSLuca Weiss qcom,controlled-remotely; 1220fd5afa5dSLuca Weiss num-channels = <16>; 1221fd5afa5dSLuca Weiss qcom,num-ees = <4>; 1222fd5afa5dSLuca Weiss iommus = <&apps_smmu 0x426 0x11>, 1223fd5afa5dSLuca Weiss <&apps_smmu 0x432 0x0>, 1224fd5afa5dSLuca Weiss <&apps_smmu 0x436 0x11>, 1225fd5afa5dSLuca Weiss <&apps_smmu 0x438 0x1>, 1226fd5afa5dSLuca Weiss <&apps_smmu 0x43f 0x0>; 1227fd5afa5dSLuca Weiss }; 1228fd5afa5dSLuca Weiss 1229fd5afa5dSLuca Weiss crypto: crypto@1dfa000 { 1230fd5afa5dSLuca Weiss compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; 1231a0a287b4SLuca Weiss reg = <0x0 0x01dfa000 0x0 0x6000>; 1232fd5afa5dSLuca Weiss dmas = <&cryptobam 4>, <&cryptobam 5>; 1233fd5afa5dSLuca Weiss dma-names = "rx", "tx"; 1234fd5afa5dSLuca Weiss iommus = <&apps_smmu 0x426 0x11>, 1235fd5afa5dSLuca Weiss <&apps_smmu 0x432 0x0>, 1236fd5afa5dSLuca Weiss <&apps_smmu 0x436 0x11>, 1237fd5afa5dSLuca Weiss <&apps_smmu 0x438 0x1>, 1238fd5afa5dSLuca Weiss <&apps_smmu 0x43f 0x0>; 1239fd5afa5dSLuca Weiss interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS 1240fd5afa5dSLuca Weiss &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; 1241fd5afa5dSLuca Weiss interconnect-names = "memory"; 1242fd5afa5dSLuca Weiss }; 1243fd5afa5dSLuca Weiss 1244aed7154aSLuca Weiss ipa: ipa@1e40000 { 1245aed7154aSLuca Weiss compatible = "qcom,sm6350-ipa"; 1246aed7154aSLuca Weiss 1247aed7154aSLuca Weiss iommus = <&apps_smmu 0x440 0x0>, 1248aed7154aSLuca Weiss <&apps_smmu 0x442 0x0>; 1249a0a287b4SLuca Weiss reg = <0x0 0x01e40000 0x0 0x8000>, 1250a0a287b4SLuca Weiss <0x0 0x01e50000 0x0 0x3000>, 1251a0a287b4SLuca Weiss <0x0 0x01e04000 0x0 0x23000>; 1252aed7154aSLuca Weiss reg-names = "ipa-reg", 1253aed7154aSLuca Weiss "ipa-shared", 1254aed7154aSLuca Weiss "gsi"; 1255aed7154aSLuca Weiss 1256aed7154aSLuca Weiss interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1257aed7154aSLuca Weiss <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1258aed7154aSLuca Weiss <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1259aed7154aSLuca Weiss <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1260aed7154aSLuca Weiss interrupt-names = "ipa", 1261aed7154aSLuca Weiss "gsi", 1262aed7154aSLuca Weiss "ipa-clock-query", 1263aed7154aSLuca Weiss "ipa-setup-ready"; 1264aed7154aSLuca Weiss 1265aed7154aSLuca Weiss clocks = <&rpmhcc RPMH_IPA_CLK>; 1266aed7154aSLuca Weiss clock-names = "core"; 1267aed7154aSLuca Weiss 1268aed7154aSLuca Weiss interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1269aed7154aSLuca Weiss <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1270aed7154aSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1271aed7154aSLuca Weiss interconnect-names = "memory", "imem", "config"; 1272aed7154aSLuca Weiss 1273aed7154aSLuca Weiss qcom,smem-states = <&ipa_smp2p_out 0>, 1274aed7154aSLuca Weiss <&ipa_smp2p_out 1>; 1275aed7154aSLuca Weiss qcom,smem-state-names = "ipa-clock-enabled-valid", 1276aed7154aSLuca Weiss "ipa-clock-enabled"; 1277aed7154aSLuca Weiss 1278aed7154aSLuca Weiss status = "disabled"; 1279aed7154aSLuca Weiss }; 1280aed7154aSLuca Weiss 12815f82b9cdSKonrad Dybcio tcsr_mutex: hwlock@1f40000 { 12825f82b9cdSKonrad Dybcio compatible = "qcom,tcsr-mutex"; 12835f82b9cdSKonrad Dybcio reg = <0x0 0x01f40000 0x0 0x40000>; 12845f82b9cdSKonrad Dybcio #hwlock-cells = <1>; 12855f82b9cdSKonrad Dybcio }; 12865f82b9cdSKonrad Dybcio 1287efc33c96SLuca Weiss adsp: remoteproc@3000000 { 1288efc33c96SLuca Weiss compatible = "qcom,sm6350-adsp-pas"; 1289b0805a86SKrzysztof Kozlowski reg = <0x0 0x03000000 0x0 0x10000>; 1290efc33c96SLuca Weiss 1291f0116881SLuca Weiss interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1292efc33c96SLuca Weiss <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1293efc33c96SLuca Weiss <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1294efc33c96SLuca Weiss <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1295efc33c96SLuca Weiss <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1296efc33c96SLuca Weiss interrupt-names = "wdog", "fatal", "ready", 1297efc33c96SLuca Weiss "handover", "stop-ack"; 1298efc33c96SLuca Weiss 1299efc33c96SLuca Weiss clocks = <&rpmhcc RPMH_CXO_CLK>; 1300efc33c96SLuca Weiss clock-names = "xo"; 1301efc33c96SLuca Weiss 1302efc33c96SLuca Weiss power-domains = <&rpmhpd SM6350_LCX>, 1303efc33c96SLuca Weiss <&rpmhpd SM6350_LMX>; 1304efc33c96SLuca Weiss power-domain-names = "lcx", "lmx"; 1305efc33c96SLuca Weiss 1306efc33c96SLuca Weiss memory-region = <&pil_adsp_mem>; 1307efc33c96SLuca Weiss 1308efc33c96SLuca Weiss qcom,qmp = <&aoss_qmp>; 1309efc33c96SLuca Weiss 1310efc33c96SLuca Weiss qcom,smem-states = <&smp2p_adsp_out 0>; 1311efc33c96SLuca Weiss qcom,smem-state-names = "stop"; 1312efc33c96SLuca Weiss 1313efc33c96SLuca Weiss status = "disabled"; 1314efc33c96SLuca Weiss 1315efc33c96SLuca Weiss glink-edge { 1316efc33c96SLuca Weiss interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1317efc33c96SLuca Weiss IPCC_MPROC_SIGNAL_GLINK_QMP 1318efc33c96SLuca Weiss IRQ_TYPE_EDGE_RISING>; 1319efc33c96SLuca Weiss mboxes = <&ipcc IPCC_CLIENT_LPASS 1320efc33c96SLuca Weiss IPCC_MPROC_SIGNAL_GLINK_QMP>; 1321efc33c96SLuca Weiss 1322efc33c96SLuca Weiss label = "lpass"; 1323efc33c96SLuca Weiss qcom,remote-pid = <2>; 1324efc33c96SLuca Weiss 1325*a014ad1aSLuca Weiss apr { 1326*a014ad1aSLuca Weiss compatible = "qcom,apr-v2"; 1327*a014ad1aSLuca Weiss qcom,glink-channels = "apr_audio_svc"; 1328*a014ad1aSLuca Weiss qcom,domain = <APR_DOMAIN_ADSP>; 1329*a014ad1aSLuca Weiss #address-cells = <1>; 1330*a014ad1aSLuca Weiss #size-cells = <0>; 1331*a014ad1aSLuca Weiss 1332*a014ad1aSLuca Weiss service@3 { 1333*a014ad1aSLuca Weiss reg = <APR_SVC_ADSP_CORE>; 1334*a014ad1aSLuca Weiss compatible = "qcom,q6core"; 1335*a014ad1aSLuca Weiss qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1336*a014ad1aSLuca Weiss }; 1337*a014ad1aSLuca Weiss 1338*a014ad1aSLuca Weiss q6afe: service@4 { 1339*a014ad1aSLuca Weiss compatible = "qcom,q6afe"; 1340*a014ad1aSLuca Weiss reg = <APR_SVC_AFE>; 1341*a014ad1aSLuca Weiss qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1342*a014ad1aSLuca Weiss 1343*a014ad1aSLuca Weiss q6afedai: dais { 1344*a014ad1aSLuca Weiss compatible = "qcom,q6afe-dais"; 1345*a014ad1aSLuca Weiss #address-cells = <1>; 1346*a014ad1aSLuca Weiss #size-cells = <0>; 1347*a014ad1aSLuca Weiss #sound-dai-cells = <1>; 1348*a014ad1aSLuca Weiss }; 1349*a014ad1aSLuca Weiss 1350*a014ad1aSLuca Weiss q6afecc: clock-controller { 1351*a014ad1aSLuca Weiss compatible = "qcom,q6afe-clocks"; 1352*a014ad1aSLuca Weiss #clock-cells = <2>; 1353*a014ad1aSLuca Weiss }; 1354*a014ad1aSLuca Weiss }; 1355*a014ad1aSLuca Weiss 1356*a014ad1aSLuca Weiss q6asm: service@7 { 1357*a014ad1aSLuca Weiss compatible = "qcom,q6asm"; 1358*a014ad1aSLuca Weiss reg = <APR_SVC_ASM>; 1359*a014ad1aSLuca Weiss qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1360*a014ad1aSLuca Weiss 1361*a014ad1aSLuca Weiss q6asmdai: dais { 1362*a014ad1aSLuca Weiss compatible = "qcom,q6asm-dais"; 1363*a014ad1aSLuca Weiss #address-cells = <1>; 1364*a014ad1aSLuca Weiss #size-cells = <0>; 1365*a014ad1aSLuca Weiss #sound-dai-cells = <1>; 1366*a014ad1aSLuca Weiss iommus = <&apps_smmu 0x1001 0x0>; 1367*a014ad1aSLuca Weiss }; 1368*a014ad1aSLuca Weiss }; 1369*a014ad1aSLuca Weiss 1370*a014ad1aSLuca Weiss q6adm: service@8 { 1371*a014ad1aSLuca Weiss compatible = "qcom,q6adm"; 1372*a014ad1aSLuca Weiss reg = <APR_SVC_ADM>; 1373*a014ad1aSLuca Weiss qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1374*a014ad1aSLuca Weiss 1375*a014ad1aSLuca Weiss q6routing: routing { 1376*a014ad1aSLuca Weiss compatible = "qcom,q6adm-routing"; 1377*a014ad1aSLuca Weiss #sound-dai-cells = <0>; 1378*a014ad1aSLuca Weiss }; 1379*a014ad1aSLuca Weiss }; 1380*a014ad1aSLuca Weiss }; 1381*a014ad1aSLuca Weiss 1382efc33c96SLuca Weiss fastrpc { 1383efc33c96SLuca Weiss compatible = "qcom,fastrpc"; 1384efc33c96SLuca Weiss qcom,glink-channels = "fastrpcglink-apps-dsp"; 1385efc33c96SLuca Weiss label = "adsp"; 138681008068SLuca Weiss qcom,non-secure-domain; 1387efc33c96SLuca Weiss #address-cells = <1>; 1388efc33c96SLuca Weiss #size-cells = <0>; 1389efc33c96SLuca Weiss 1390efc33c96SLuca Weiss compute-cb@3 { 1391efc33c96SLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 1392efc33c96SLuca Weiss reg = <3>; 1393efc33c96SLuca Weiss iommus = <&apps_smmu 0x1003 0x0>; 1394efc33c96SLuca Weiss }; 1395efc33c96SLuca Weiss 1396efc33c96SLuca Weiss compute-cb@4 { 1397efc33c96SLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 1398efc33c96SLuca Weiss reg = <4>; 1399efc33c96SLuca Weiss iommus = <&apps_smmu 0x1004 0x0>; 1400efc33c96SLuca Weiss }; 1401efc33c96SLuca Weiss 1402efc33c96SLuca Weiss compute-cb@5 { 1403efc33c96SLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 1404efc33c96SLuca Weiss reg = <5>; 1405efc33c96SLuca Weiss iommus = <&apps_smmu 0x1005 0x0>; 1406efc33c96SLuca Weiss qcom,nsessions = <5>; 1407efc33c96SLuca Weiss }; 1408efc33c96SLuca Weiss }; 1409efc33c96SLuca Weiss }; 1410efc33c96SLuca Weiss }; 1411efc33c96SLuca Weiss 1412bd9b7675SKonrad Dybcio gpu: gpu@3d00000 { 1413bd9b7675SKonrad Dybcio compatible = "qcom,adreno-619.0", "qcom,adreno"; 1414a0a287b4SLuca Weiss reg = <0x0 0x03d00000 0x0 0x40000>, 1415a0a287b4SLuca Weiss <0x0 0x03d9e000 0x0 0x1000>; 1416bd9b7675SKonrad Dybcio reg-names = "kgsl_3d0_reg_memory", 1417bd9b7675SKonrad Dybcio "cx_mem"; 1418bd9b7675SKonrad Dybcio interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1419bd9b7675SKonrad Dybcio 1420bd9b7675SKonrad Dybcio iommus = <&adreno_smmu 0>; 1421bd9b7675SKonrad Dybcio operating-points-v2 = <&gpu_opp_table>; 1422bd9b7675SKonrad Dybcio qcom,gmu = <&gmu>; 1423bd9b7675SKonrad Dybcio nvmem-cells = <&gpu_speed_bin>; 1424bd9b7675SKonrad Dybcio nvmem-cell-names = "speed_bin"; 142564628795SLuca Weiss #cooling-cells = <2>; 1426bd9b7675SKonrad Dybcio 1427bd9b7675SKonrad Dybcio status = "disabled"; 1428bd9b7675SKonrad Dybcio 1429891af1aaSLuca Weiss gpu_zap_shader: zap-shader { 1430bd9b7675SKonrad Dybcio memory-region = <&pil_gpu_mem>; 1431bd9b7675SKonrad Dybcio }; 1432bd9b7675SKonrad Dybcio 1433bd9b7675SKonrad Dybcio gpu_opp_table: opp-table { 1434bd9b7675SKonrad Dybcio compatible = "operating-points-v2"; 1435bd9b7675SKonrad Dybcio 1436bd9b7675SKonrad Dybcio opp-850000000 { 1437bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <850000000>; 1438bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1439600c499fSLuca Weiss opp-supported-hw = <0x03>; 1440bd9b7675SKonrad Dybcio }; 1441bd9b7675SKonrad Dybcio 1442bd9b7675SKonrad Dybcio opp-800000000 { 1443bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <800000000>; 1444bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1445600c499fSLuca Weiss opp-supported-hw = <0x07>; 1446bd9b7675SKonrad Dybcio }; 1447bd9b7675SKonrad Dybcio 1448bd9b7675SKonrad Dybcio opp-650000000 { 1449bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <650000000>; 1450bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1451600c499fSLuca Weiss opp-supported-hw = <0x0f>; 1452bd9b7675SKonrad Dybcio }; 1453bd9b7675SKonrad Dybcio 1454bd9b7675SKonrad Dybcio opp-565000000 { 1455bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <565000000>; 1456bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1457600c499fSLuca Weiss opp-supported-hw = <0x1f>; 1458bd9b7675SKonrad Dybcio }; 1459bd9b7675SKonrad Dybcio 1460bd9b7675SKonrad Dybcio opp-430000000 { 1461bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <430000000>; 1462bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1463600c499fSLuca Weiss opp-supported-hw = <0x1f>; 1464bd9b7675SKonrad Dybcio }; 1465bd9b7675SKonrad Dybcio 1466bd9b7675SKonrad Dybcio opp-355000000 { 1467bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <355000000>; 1468bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1469600c499fSLuca Weiss opp-supported-hw = <0x1f>; 1470bd9b7675SKonrad Dybcio }; 1471bd9b7675SKonrad Dybcio 1472bd9b7675SKonrad Dybcio opp-253000000 { 1473bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <253000000>; 1474bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1475600c499fSLuca Weiss opp-supported-hw = <0x1f>; 1476bd9b7675SKonrad Dybcio }; 1477bd9b7675SKonrad Dybcio }; 1478bd9b7675SKonrad Dybcio }; 1479bd9b7675SKonrad Dybcio 1480bd9b7675SKonrad Dybcio adreno_smmu: iommu@3d40000 { 1481bd9b7675SKonrad Dybcio compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1482a0a287b4SLuca Weiss reg = <0x0 0x03d40000 0x0 0x10000>; 1483bd9b7675SKonrad Dybcio #iommu-cells = <1>; 1484bd9b7675SKonrad Dybcio #global-interrupts = <2>; 1485bd9b7675SKonrad Dybcio interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1486bd9b7675SKonrad Dybcio <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1487bd9b7675SKonrad Dybcio <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1488bd9b7675SKonrad Dybcio <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1489bd9b7675SKonrad Dybcio <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1490bd9b7675SKonrad Dybcio <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1491bd9b7675SKonrad Dybcio <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1492bd9b7675SKonrad Dybcio <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1493bd9b7675SKonrad Dybcio <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1494bd9b7675SKonrad Dybcio <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1495bd9b7675SKonrad Dybcio 1496bd9b7675SKonrad Dybcio clocks = <&gpucc GPU_CC_AHB_CLK>, 1497bd9b7675SKonrad Dybcio <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1498bd9b7675SKonrad Dybcio <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1499bd9b7675SKonrad Dybcio clock-names = "ahb", 1500bd9b7675SKonrad Dybcio "bus", 1501bd9b7675SKonrad Dybcio "iface"; 1502bd9b7675SKonrad Dybcio 1503bd9b7675SKonrad Dybcio power-domains = <&gpucc GPU_CX_GDSC>; 1504bd9b7675SKonrad Dybcio }; 1505bd9b7675SKonrad Dybcio 1506bd9b7675SKonrad Dybcio gmu: gmu@3d6a000 { 1507bd9b7675SKonrad Dybcio compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1508a0a287b4SLuca Weiss reg = <0x0 0x03d6a000 0x0 0x31000>, 1509a0a287b4SLuca Weiss <0x0 0x0b290000 0x0 0x10000>, 1510a0a287b4SLuca Weiss <0x0 0x0b490000 0x0 0x10000>; 1511bd9b7675SKonrad Dybcio reg-names = "gmu", 1512bd9b7675SKonrad Dybcio "gmu_pdc", 1513bd9b7675SKonrad Dybcio "gmu_pdc_seq"; 1514bd9b7675SKonrad Dybcio 1515bd9b7675SKonrad Dybcio interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1516bd9b7675SKonrad Dybcio <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1517bd9b7675SKonrad Dybcio interrupt-names = "hfi", 1518bd9b7675SKonrad Dybcio "gmu"; 1519bd9b7675SKonrad Dybcio 1520bd9b7675SKonrad Dybcio clocks = <&gpucc GPU_CC_AHB_CLK>, 1521bd9b7675SKonrad Dybcio <&gpucc GPU_CC_CX_GMU_CLK>, 1522bd9b7675SKonrad Dybcio <&gpucc GPU_CC_CXO_CLK>, 1523bd9b7675SKonrad Dybcio <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1524bd9b7675SKonrad Dybcio <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1525bd9b7675SKonrad Dybcio clock-names = "ahb", 1526bd9b7675SKonrad Dybcio "gmu", 1527bd9b7675SKonrad Dybcio "cxo", 1528bd9b7675SKonrad Dybcio "axi", 1529bd9b7675SKonrad Dybcio "memnoc"; 1530bd9b7675SKonrad Dybcio 1531bd9b7675SKonrad Dybcio power-domains = <&gpucc GPU_CX_GDSC>, 1532bd9b7675SKonrad Dybcio <&gpucc GPU_GX_GDSC>; 1533bd9b7675SKonrad Dybcio power-domain-names = "cx", 1534bd9b7675SKonrad Dybcio "gx"; 1535bd9b7675SKonrad Dybcio 1536bd9b7675SKonrad Dybcio iommus = <&adreno_smmu 5>; 1537bd9b7675SKonrad Dybcio 1538bd9b7675SKonrad Dybcio operating-points-v2 = <&gmu_opp_table>; 1539bd9b7675SKonrad Dybcio 1540bd9b7675SKonrad Dybcio gmu_opp_table: opp-table { 1541bd9b7675SKonrad Dybcio compatible = "operating-points-v2"; 1542bd9b7675SKonrad Dybcio 1543bd9b7675SKonrad Dybcio opp-200000000 { 1544bd9b7675SKonrad Dybcio opp-hz = /bits/ 64 <200000000>; 1545bd9b7675SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1546bd9b7675SKonrad Dybcio }; 1547bd9b7675SKonrad Dybcio }; 1548bd9b7675SKonrad Dybcio }; 1549bd9b7675SKonrad Dybcio 155075a511b1SKonrad Dybcio gpucc: clock-controller@3d90000 { 155175a511b1SKonrad Dybcio compatible = "qcom,sm6350-gpucc"; 1552a0a287b4SLuca Weiss reg = <0x0 0x03d90000 0x0 0x9000>; 155375a511b1SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 155475a511b1SKonrad Dybcio <&gcc GCC_GPU_GPLL0_CLK>, 155575a511b1SKonrad Dybcio <&gcc GCC_GPU_GPLL0_DIV_CLK>; 155675a511b1SKonrad Dybcio clock-names = "bi_tcxo", 155775a511b1SKonrad Dybcio "gcc_gpu_gpll0_clk_src", 155875a511b1SKonrad Dybcio "gcc_gpu_gpll0_div_clk_src"; 155975a511b1SKonrad Dybcio #clock-cells = <1>; 156075a511b1SKonrad Dybcio #reset-cells = <1>; 156175a511b1SKonrad Dybcio #power-domain-cells = <1>; 156275a511b1SKonrad Dybcio }; 156375a511b1SKonrad Dybcio 1564489be59bSLuca Weiss mpss: remoteproc@4080000 { 1565489be59bSLuca Weiss compatible = "qcom,sm6350-mpss-pas"; 1566cd8d83deSKrzysztof Kozlowski reg = <0x0 0x04080000 0x0 0x10000>; 1567489be59bSLuca Weiss 1568489be59bSLuca Weiss interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1569489be59bSLuca Weiss <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1570489be59bSLuca Weiss <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1571489be59bSLuca Weiss <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1572489be59bSLuca Weiss <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1573489be59bSLuca Weiss <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1574489be59bSLuca Weiss interrupt-names = "wdog", "fatal", "ready", "handover", 1575489be59bSLuca Weiss "stop-ack", "shutdown-ack"; 1576489be59bSLuca Weiss 1577489be59bSLuca Weiss clocks = <&rpmhcc RPMH_CXO_CLK>; 1578489be59bSLuca Weiss clock-names = "xo"; 1579489be59bSLuca Weiss 1580489be59bSLuca Weiss power-domains = <&rpmhpd SM6350_CX>, 1581489be59bSLuca Weiss <&rpmhpd SM6350_MSS>; 1582489be59bSLuca Weiss power-domain-names = "cx", "mss"; 1583489be59bSLuca Weiss 1584489be59bSLuca Weiss memory-region = <&pil_modem_mem>; 1585489be59bSLuca Weiss 1586489be59bSLuca Weiss qcom,qmp = <&aoss_qmp>; 1587489be59bSLuca Weiss 1588489be59bSLuca Weiss qcom,smem-states = <&modem_smp2p_out 0>; 1589489be59bSLuca Weiss qcom,smem-state-names = "stop"; 1590489be59bSLuca Weiss 1591489be59bSLuca Weiss status = "disabled"; 1592489be59bSLuca Weiss 1593489be59bSLuca Weiss glink-edge { 1594489be59bSLuca Weiss interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1595489be59bSLuca Weiss IPCC_MPROC_SIGNAL_GLINK_QMP 1596489be59bSLuca Weiss IRQ_TYPE_EDGE_RISING>; 1597489be59bSLuca Weiss mboxes = <&ipcc IPCC_CLIENT_MPSS 1598489be59bSLuca Weiss IPCC_MPROC_SIGNAL_GLINK_QMP>; 1599489be59bSLuca Weiss label = "modem"; 1600489be59bSLuca Weiss qcom,remote-pid = <1>; 1601489be59bSLuca Weiss }; 1602489be59bSLuca Weiss }; 1603489be59bSLuca Weiss 16048eb5287eSLuca Weiss cdsp: remoteproc@8300000 { 16058eb5287eSLuca Weiss compatible = "qcom,sm6350-cdsp-pas"; 1606a0a287b4SLuca Weiss reg = <0x0 0x08300000 0x0 0x10000>; 16078eb5287eSLuca Weiss 1608f0116881SLuca Weiss interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 16098eb5287eSLuca Weiss <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 16108eb5287eSLuca Weiss <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 16118eb5287eSLuca Weiss <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 16128eb5287eSLuca Weiss <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 16138eb5287eSLuca Weiss interrupt-names = "wdog", "fatal", "ready", 16148eb5287eSLuca Weiss "handover", "stop-ack"; 16158eb5287eSLuca Weiss 16168eb5287eSLuca Weiss clocks = <&rpmhcc RPMH_CXO_CLK>; 16178eb5287eSLuca Weiss clock-names = "xo"; 16188eb5287eSLuca Weiss 16198eb5287eSLuca Weiss power-domains = <&rpmhpd SM6350_CX>, 16208eb5287eSLuca Weiss <&rpmhpd SM6350_MX>; 16218eb5287eSLuca Weiss power-domain-names = "cx", "mx"; 16228eb5287eSLuca Weiss 16238eb5287eSLuca Weiss memory-region = <&pil_cdsp_mem>; 16248eb5287eSLuca Weiss 16258eb5287eSLuca Weiss qcom,qmp = <&aoss_qmp>; 16268eb5287eSLuca Weiss 16278eb5287eSLuca Weiss qcom,smem-states = <&smp2p_cdsp_out 0>; 16288eb5287eSLuca Weiss qcom,smem-state-names = "stop"; 16298eb5287eSLuca Weiss 16308eb5287eSLuca Weiss status = "disabled"; 16318eb5287eSLuca Weiss 16328eb5287eSLuca Weiss glink-edge { 16338eb5287eSLuca Weiss interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 16348eb5287eSLuca Weiss IPCC_MPROC_SIGNAL_GLINK_QMP 16358eb5287eSLuca Weiss IRQ_TYPE_EDGE_RISING>; 16368eb5287eSLuca Weiss mboxes = <&ipcc IPCC_CLIENT_CDSP 16378eb5287eSLuca Weiss IPCC_MPROC_SIGNAL_GLINK_QMP>; 16388eb5287eSLuca Weiss 16398eb5287eSLuca Weiss label = "cdsp"; 16408eb5287eSLuca Weiss qcom,remote-pid = <5>; 16418eb5287eSLuca Weiss 16428eb5287eSLuca Weiss fastrpc { 16438eb5287eSLuca Weiss compatible = "qcom,fastrpc"; 16448eb5287eSLuca Weiss qcom,glink-channels = "fastrpcglink-apps-dsp"; 16458eb5287eSLuca Weiss label = "cdsp"; 164681008068SLuca Weiss qcom,non-secure-domain; 16478eb5287eSLuca Weiss #address-cells = <1>; 16488eb5287eSLuca Weiss #size-cells = <0>; 16498eb5287eSLuca Weiss 16508eb5287eSLuca Weiss compute-cb@1 { 16518eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16528eb5287eSLuca Weiss reg = <1>; 16538eb5287eSLuca Weiss iommus = <&apps_smmu 0x1401 0x20>; 16548eb5287eSLuca Weiss }; 16558eb5287eSLuca Weiss 16568eb5287eSLuca Weiss compute-cb@2 { 16578eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16588eb5287eSLuca Weiss reg = <2>; 16598eb5287eSLuca Weiss iommus = <&apps_smmu 0x1402 0x20>; 16608eb5287eSLuca Weiss }; 16618eb5287eSLuca Weiss 16628eb5287eSLuca Weiss compute-cb@3 { 16638eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16648eb5287eSLuca Weiss reg = <3>; 16658eb5287eSLuca Weiss iommus = <&apps_smmu 0x1403 0x20>; 16668eb5287eSLuca Weiss }; 16678eb5287eSLuca Weiss 16688eb5287eSLuca Weiss compute-cb@4 { 16698eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16708eb5287eSLuca Weiss reg = <4>; 16718eb5287eSLuca Weiss iommus = <&apps_smmu 0x1404 0x20>; 16728eb5287eSLuca Weiss }; 16738eb5287eSLuca Weiss 16748eb5287eSLuca Weiss compute-cb@5 { 16758eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16768eb5287eSLuca Weiss reg = <5>; 16778eb5287eSLuca Weiss iommus = <&apps_smmu 0x1405 0x20>; 16788eb5287eSLuca Weiss }; 16798eb5287eSLuca Weiss 16808eb5287eSLuca Weiss compute-cb@6 { 16818eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16828eb5287eSLuca Weiss reg = <6>; 16838eb5287eSLuca Weiss iommus = <&apps_smmu 0x1406 0x20>; 16848eb5287eSLuca Weiss }; 16858eb5287eSLuca Weiss 16868eb5287eSLuca Weiss compute-cb@7 { 16878eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16888eb5287eSLuca Weiss reg = <7>; 16898eb5287eSLuca Weiss iommus = <&apps_smmu 0x1407 0x20>; 16908eb5287eSLuca Weiss }; 16918eb5287eSLuca Weiss 16928eb5287eSLuca Weiss compute-cb@8 { 16938eb5287eSLuca Weiss compatible = "qcom,fastrpc-compute-cb"; 16948eb5287eSLuca Weiss reg = <8>; 16958eb5287eSLuca Weiss iommus = <&apps_smmu 0x1408 0x20>; 16968eb5287eSLuca Weiss }; 16978eb5287eSLuca Weiss 16988eb5287eSLuca Weiss /* note: secure cb9 in downstream */ 16998eb5287eSLuca Weiss }; 17008eb5287eSLuca Weiss }; 17018eb5287eSLuca Weiss }; 17028eb5287eSLuca Weiss 170396bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 17041797e1c9SKonrad Dybcio compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1705a0a287b4SLuca Weiss reg = <0x0 0x08804000 0x0 0x1000>; 17061797e1c9SKonrad Dybcio 17071797e1c9SKonrad Dybcio interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 17081797e1c9SKonrad Dybcio <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 17091797e1c9SKonrad Dybcio interrupt-names = "hc_irq", "pwr_irq"; 17107372b944SMarijn Suijten iommus = <&apps_smmu 0x560 0x0>; 17111797e1c9SKonrad Dybcio 17121797e1c9SKonrad Dybcio clocks = <&gcc GCC_SDCC2_AHB_CLK>, 17131797e1c9SKonrad Dybcio <&gcc GCC_SDCC2_APPS_CLK>, 17141797e1c9SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 17151797e1c9SKonrad Dybcio clock-names = "iface", "core", "xo"; 1716e10d451eSMarijn Suijten resets = <&gcc GCC_SDCC2_BCR>; 171738c5c4feSLuca Weiss interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 171838c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 171938c5c4feSLuca Weiss interconnect-names = "sdhc-ddr", "cpu-sdhc"; 172038c5c4feSLuca Weiss 1721a5d0314bSMarijn Suijten pinctrl-0 = <&sdc2_on_state>; 1722a5d0314bSMarijn Suijten pinctrl-1 = <&sdc2_off_state>; 1723a5d0314bSMarijn Suijten pinctrl-names = "default", "sleep"; 1724a5d0314bSMarijn Suijten 17251797e1c9SKonrad Dybcio qcom,dll-config = <0x0007642c>; 17261797e1c9SKonrad Dybcio qcom,ddr-config = <0x80040868>; 17277a9016dbSMarijn Suijten power-domains = <&rpmhpd SM6350_CX>; 17281797e1c9SKonrad Dybcio operating-points-v2 = <&sdhc2_opp_table>; 17291797e1c9SKonrad Dybcio bus-width = <4>; 17301797e1c9SKonrad Dybcio 17311797e1c9SKonrad Dybcio status = "disabled"; 17321797e1c9SKonrad Dybcio 17330e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 17341797e1c9SKonrad Dybcio compatible = "operating-points-v2"; 17351797e1c9SKonrad Dybcio 17361797e1c9SKonrad Dybcio opp-100000000 { 17371797e1c9SKonrad Dybcio opp-hz = /bits/ 64 <100000000>; 17381797e1c9SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 173938c5c4feSLuca Weiss opp-peak-kBps = <790000 131000>; 174038c5c4feSLuca Weiss opp-avg-kBps = <50000 50000>; 17411797e1c9SKonrad Dybcio }; 17421797e1c9SKonrad Dybcio 17431797e1c9SKonrad Dybcio opp-202000000 { 17441797e1c9SKonrad Dybcio opp-hz = /bits/ 64 <202000000>; 17451797e1c9SKonrad Dybcio required-opps = <&rpmhpd_opp_nom>; 174638c5c4feSLuca Weiss opp-peak-kBps = <3190000 294000>; 174738c5c4feSLuca Weiss opp-avg-kBps = <261438 300000>; 17481797e1c9SKonrad Dybcio }; 17491797e1c9SKonrad Dybcio }; 17501797e1c9SKonrad Dybcio }; 17511797e1c9SKonrad Dybcio 175223737b95SKonrad Dybcio usb_1_hsphy: phy@88e3000 { 175323737b95SKonrad Dybcio compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1754a0a287b4SLuca Weiss reg = <0x0 0x088e3000 0x0 0x400>; 175523737b95SKonrad Dybcio status = "disabled"; 175623737b95SKonrad Dybcio #phy-cells = <0>; 175723737b95SKonrad Dybcio 175823737b95SKonrad Dybcio clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 175923737b95SKonrad Dybcio clock-names = "cfg_ahb", "ref"; 176023737b95SKonrad Dybcio 176123737b95SKonrad Dybcio resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 176223737b95SKonrad Dybcio }; 176323737b95SKonrad Dybcio 17645ed2b638SLuca Weiss usb_1_qmpphy: phy@88e8000 { 17655ed2b638SLuca Weiss compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1766a0a287b4SLuca Weiss reg = <0x0 0x088e8000 0x0 0x3000>; 176723737b95SKonrad Dybcio 176823737b95SKonrad Dybcio clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 17695ed2b638SLuca Weiss <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 17705ed2b638SLuca Weiss <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 17715ed2b638SLuca Weiss <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 17725ed2b638SLuca Weiss clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 177323737b95SKonrad Dybcio 17745ed2b638SLuca Weiss power-domains = <&gcc USB30_PRIM_GDSC>; 17755ed2b638SLuca Weiss 17765ed2b638SLuca Weiss resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 17775ed2b638SLuca Weiss <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 177823737b95SKonrad Dybcio reset-names = "phy", "common"; 177923737b95SKonrad Dybcio 17806814d454SLuca Weiss orientation-switch; 17816814d454SLuca Weiss 178223737b95SKonrad Dybcio #clock-cells = <1>; 17835ed2b638SLuca Weiss #phy-cells = <1>; 17845ed2b638SLuca Weiss 17855ed2b638SLuca Weiss status = "disabled"; 17866814d454SLuca Weiss 17876814d454SLuca Weiss ports { 17886814d454SLuca Weiss #address-cells = <1>; 17896814d454SLuca Weiss #size-cells = <0>; 17906814d454SLuca Weiss 17916814d454SLuca Weiss port@0 { 17926814d454SLuca Weiss reg = <0>; 17936814d454SLuca Weiss 17946814d454SLuca Weiss usb_1_qmpphy_out: endpoint { 17956814d454SLuca Weiss }; 17966814d454SLuca Weiss }; 17976814d454SLuca Weiss 17986814d454SLuca Weiss port@1 { 17996814d454SLuca Weiss reg = <1>; 18006814d454SLuca Weiss 18016814d454SLuca Weiss usb_1_qmpphy_usb_ss_in: endpoint { 18026814d454SLuca Weiss remote-endpoint = <&usb_1_dwc3_ss_out>; 18036814d454SLuca Weiss }; 18046814d454SLuca Weiss }; 18056814d454SLuca Weiss 18066814d454SLuca Weiss port@2 { 18076814d454SLuca Weiss reg = <2>; 18086814d454SLuca Weiss 18096814d454SLuca Weiss usb_1_qmpphy_dp_in: endpoint { 18106814d454SLuca Weiss }; 18116814d454SLuca Weiss }; 18126814d454SLuca Weiss }; 181323737b95SKonrad Dybcio }; 181423737b95SKonrad Dybcio 181538c5c4feSLuca Weiss dc_noc: interconnect@9160000 { 181638c5c4feSLuca Weiss compatible = "qcom,sm6350-dc-noc"; 1817a0a287b4SLuca Weiss reg = <0x0 0x09160000 0x0 0x3200>; 181838c5c4feSLuca Weiss #interconnect-cells = <2>; 181938c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 182038c5c4feSLuca Weiss }; 182138c5c4feSLuca Weiss 1822ced2f0d7SKonrad Dybcio system-cache-controller@9200000 { 1823ced2f0d7SKonrad Dybcio compatible = "qcom,sm6350-llcc"; 1824a0a287b4SLuca Weiss reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>; 182565d9975eSManivannan Sadhasivam reg-names = "llcc0_base", "llcc_broadcast_base"; 1826ced2f0d7SKonrad Dybcio }; 1827ced2f0d7SKonrad Dybcio 182838c5c4feSLuca Weiss gem_noc: interconnect@9680000 { 182938c5c4feSLuca Weiss compatible = "qcom,sm6350-gem-noc"; 1830a0a287b4SLuca Weiss reg = <0x0 0x09680000 0x0 0x3e200>; 183138c5c4feSLuca Weiss #interconnect-cells = <2>; 183238c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 183338c5c4feSLuca Weiss }; 183438c5c4feSLuca Weiss 183538c5c4feSLuca Weiss npu_noc: interconnect@9990000 { 183638c5c4feSLuca Weiss compatible = "qcom,sm6350-npu-noc"; 1837a0a287b4SLuca Weiss reg = <0x0 0x09990000 0x0 0x1600>; 183838c5c4feSLuca Weiss #interconnect-cells = <2>; 183938c5c4feSLuca Weiss qcom,bcm-voters = <&apps_bcm_voter>; 184038c5c4feSLuca Weiss }; 184138c5c4feSLuca Weiss 18421df6b32eSKonrad Dybcio pmu@90b6300 { 18431df6b32eSKonrad Dybcio compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 18441df6b32eSKonrad Dybcio reg = <0x0 0x090b6300 0x0 0x600>; 18451df6b32eSKonrad Dybcio interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 18461df6b32eSKonrad Dybcio 18471df6b32eSKonrad Dybcio operating-points-v2 = <&llcc_bwmon_opp_table>; 18481df6b32eSKonrad Dybcio interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 18491df6b32eSKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 18501df6b32eSKonrad Dybcio 18511df6b32eSKonrad Dybcio llcc_bwmon_opp_table: opp-table { 18521df6b32eSKonrad Dybcio compatible = "operating-points-v2"; 18531df6b32eSKonrad Dybcio 18541df6b32eSKonrad Dybcio opp-0 { 18551df6b32eSKonrad Dybcio opp-peak-kBps = <2288000>; 18561df6b32eSKonrad Dybcio }; 18571df6b32eSKonrad Dybcio 18581df6b32eSKonrad Dybcio opp-1 { 18591df6b32eSKonrad Dybcio opp-peak-kBps = <4577000>; 18601df6b32eSKonrad Dybcio }; 18611df6b32eSKonrad Dybcio 18621df6b32eSKonrad Dybcio opp-2 { 18631df6b32eSKonrad Dybcio opp-peak-kBps = <7110000>; 18641df6b32eSKonrad Dybcio }; 18651df6b32eSKonrad Dybcio 18661df6b32eSKonrad Dybcio opp-3 { 18671df6b32eSKonrad Dybcio opp-peak-kBps = <9155000>; 18681df6b32eSKonrad Dybcio }; 18691df6b32eSKonrad Dybcio 18701df6b32eSKonrad Dybcio opp-4 { 18711df6b32eSKonrad Dybcio opp-peak-kBps = <12298000>; 18721df6b32eSKonrad Dybcio }; 18731df6b32eSKonrad Dybcio 18741df6b32eSKonrad Dybcio opp-5 { 18751df6b32eSKonrad Dybcio opp-peak-kBps = <14236000>; 18761df6b32eSKonrad Dybcio }; 18771df6b32eSKonrad Dybcio 18781df6b32eSKonrad Dybcio }; 18791df6b32eSKonrad Dybcio }; 18801df6b32eSKonrad Dybcio 18811df6b32eSKonrad Dybcio pmu@90cd000 { 18821df6b32eSKonrad Dybcio compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 18831df6b32eSKonrad Dybcio reg = <0x0 0x090cd000 0x0 0x1000>; 18841df6b32eSKonrad Dybcio interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 18851df6b32eSKonrad Dybcio 18861df6b32eSKonrad Dybcio operating-points-v2 = <&cpu_bwmon_opp_table>; 18871df6b32eSKonrad Dybcio interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 18881df6b32eSKonrad Dybcio &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 18891df6b32eSKonrad Dybcio 18901df6b32eSKonrad Dybcio cpu_bwmon_opp_table: opp-table { 18911df6b32eSKonrad Dybcio compatible = "operating-points-v2"; 18921df6b32eSKonrad Dybcio 18931df6b32eSKonrad Dybcio opp-0 { 18941df6b32eSKonrad Dybcio opp-peak-kBps = <762000>; 18951df6b32eSKonrad Dybcio }; 18961df6b32eSKonrad Dybcio 18971df6b32eSKonrad Dybcio opp-1 { 18981df6b32eSKonrad Dybcio opp-peak-kBps = <1144000>; 18991df6b32eSKonrad Dybcio }; 19001df6b32eSKonrad Dybcio 19011df6b32eSKonrad Dybcio opp-2 { 19021df6b32eSKonrad Dybcio opp-peak-kBps = <1720000>; 19031df6b32eSKonrad Dybcio }; 19041df6b32eSKonrad Dybcio 19051df6b32eSKonrad Dybcio opp-3 { 19061df6b32eSKonrad Dybcio opp-peak-kBps = <2086000>; 19071df6b32eSKonrad Dybcio }; 19081df6b32eSKonrad Dybcio 19091df6b32eSKonrad Dybcio opp-4 { 19101df6b32eSKonrad Dybcio opp-peak-kBps = <2597000>; 19111df6b32eSKonrad Dybcio }; 19121df6b32eSKonrad Dybcio 19131df6b32eSKonrad Dybcio opp-5 { 19141df6b32eSKonrad Dybcio opp-peak-kBps = <2929000>; 19151df6b32eSKonrad Dybcio }; 19161df6b32eSKonrad Dybcio 19171df6b32eSKonrad Dybcio opp-6 { 19181df6b32eSKonrad Dybcio opp-peak-kBps = <3879000>; 19191df6b32eSKonrad Dybcio }; 19201df6b32eSKonrad Dybcio 19211df6b32eSKonrad Dybcio opp-7 { 19221df6b32eSKonrad Dybcio opp-peak-kBps = <5161000>; 19231df6b32eSKonrad Dybcio }; 19241df6b32eSKonrad Dybcio 19251df6b32eSKonrad Dybcio opp-8 { 19261df6b32eSKonrad Dybcio opp-peak-kBps = <5931000>; 19271df6b32eSKonrad Dybcio }; 19281df6b32eSKonrad Dybcio 19291df6b32eSKonrad Dybcio opp-9 { 19301df6b32eSKonrad Dybcio opp-peak-kBps = <6881000>; 19311df6b32eSKonrad Dybcio }; 19321df6b32eSKonrad Dybcio 19331df6b32eSKonrad Dybcio opp-10 { 19341df6b32eSKonrad Dybcio opp-peak-kBps = <7980000>; 19351df6b32eSKonrad Dybcio }; 19361df6b32eSKonrad Dybcio }; 19371df6b32eSKonrad Dybcio }; 19381df6b32eSKonrad Dybcio 193923737b95SKonrad Dybcio usb_1: usb@a6f8800 { 194023737b95SKonrad Dybcio compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1941a0a287b4SLuca Weiss reg = <0x0 0x0a6f8800 0x0 0x400>; 194223737b95SKonrad Dybcio status = "disabled"; 194323737b95SKonrad Dybcio #address-cells = <2>; 194423737b95SKonrad Dybcio #size-cells = <2>; 194523737b95SKonrad Dybcio ranges; 194623737b95SKonrad Dybcio 194723737b95SKonrad Dybcio clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 194823737b95SKonrad Dybcio <&gcc GCC_USB30_PRIM_MASTER_CLK>, 194923737b95SKonrad Dybcio <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 19508d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 19518d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 19528d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 19538d5fd4e4SKrzysztof Kozlowski "core", 19548d5fd4e4SKrzysztof Kozlowski "iface", 19558d5fd4e4SKrzysztof Kozlowski "sleep", 19568d5fd4e4SKrzysztof Kozlowski "mock_utmi"; 195723737b95SKonrad Dybcio 195823737b95SKonrad Dybcio interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 19597c9afa1fSKrishna Kurapati <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 19607c9afa1fSKrishna Kurapati <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 196123737b95SKonrad Dybcio <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 19627c9afa1fSKrishna Kurapati <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 19637c9afa1fSKrishna Kurapati interrupt-names = "pwr_event", 19647c9afa1fSKrishna Kurapati "hs_phy_irq", 19657c9afa1fSKrishna Kurapati "dp_hs_phy_irq", 19667c9afa1fSKrishna Kurapati "dm_hs_phy_irq", 19677c9afa1fSKrishna Kurapati "ss_phy_irq"; 196823737b95SKonrad Dybcio 196923737b95SKonrad Dybcio power-domains = <&gcc USB30_PRIM_GDSC>; 197023737b95SKonrad Dybcio 197123737b95SKonrad Dybcio resets = <&gcc GCC_USB30_PRIM_BCR>; 197223737b95SKonrad Dybcio 197338c5c4feSLuca Weiss interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 197438c5c4feSLuca Weiss <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 197538c5c4feSLuca Weiss interconnect-names = "usb-ddr", "apps-usb"; 197638c5c4feSLuca Weiss 197723737b95SKonrad Dybcio usb_1_dwc3: usb@a600000 { 197823737b95SKonrad Dybcio compatible = "snps,dwc3"; 1979a0a287b4SLuca Weiss reg = <0x0 0x0a600000 0x0 0xcd00>; 198023737b95SKonrad Dybcio interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 19814ef13f7fSKonrad Dybcio iommus = <&apps_smmu 0x540 0x0>; 198223737b95SKonrad Dybcio snps,dis_u2_susphy_quirk; 198323737b95SKonrad Dybcio snps,dis_enblslpm_quirk; 198423737b95SKonrad Dybcio snps,has-lpm-erratum; 198523737b95SKonrad Dybcio snps,hird-threshold = /bits/ 8 <0x10>; 1986c5d57eb7SKrishna Kurapati snps,parkmode-disable-ss-quirk; 19878e252c3eSKrishna Kurapati snps,dis-u1-entry-quirk; 19888e252c3eSKrishna Kurapati snps,dis-u2-entry-quirk; 19895ed2b638SLuca Weiss phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 199023737b95SKonrad Dybcio phy-names = "usb2-phy", "usb3-phy"; 19916814d454SLuca Weiss usb-role-switch; 19926814d454SLuca Weiss 19936814d454SLuca Weiss ports { 19946814d454SLuca Weiss #address-cells = <1>; 19956814d454SLuca Weiss #size-cells = <0>; 19966814d454SLuca Weiss 19976814d454SLuca Weiss port@0 { 19986814d454SLuca Weiss reg = <0>; 19996814d454SLuca Weiss 20006814d454SLuca Weiss usb_1_dwc3_hs_out: endpoint { 20016814d454SLuca Weiss }; 20026814d454SLuca Weiss }; 20036814d454SLuca Weiss 20046814d454SLuca Weiss port@1 { 20056814d454SLuca Weiss reg = <1>; 20066814d454SLuca Weiss 20076814d454SLuca Weiss usb_1_dwc3_ss_out: endpoint { 20086814d454SLuca Weiss remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 20096814d454SLuca Weiss }; 20106814d454SLuca Weiss }; 20116814d454SLuca Weiss }; 201223737b95SKonrad Dybcio }; 201323737b95SKonrad Dybcio }; 201423737b95SKonrad Dybcio 201567081281SLuca Weiss videocc: clock-controller@aaf0000 { 201667081281SLuca Weiss compatible = "qcom,sm6350-videocc"; 201767081281SLuca Weiss reg = <0x0 0x0aaf0000 0x0 0x10000>; 201867081281SLuca Weiss clocks = <&gcc GCC_VIDEO_AHB_CLK>, 201967081281SLuca Weiss <&rpmhcc RPMH_CXO_CLK>, 202067081281SLuca Weiss <&sleep_clk>; 202167081281SLuca Weiss clock-names = "iface", 202267081281SLuca Weiss "bi_tcxo", 202367081281SLuca Weiss "sleep_clk"; 202467081281SLuca Weiss #clock-cells = <1>; 202567081281SLuca Weiss #reset-cells = <1>; 202667081281SLuca Weiss #power-domain-cells = <1>; 202767081281SLuca Weiss }; 202867081281SLuca Weiss 2029033fb15fSLuca Weiss cci0: cci@ac4a000 { 2030033fb15fSLuca Weiss compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2031a0a287b4SLuca Weiss reg = <0x0 0x0ac4a000 0x0 0x1000>; 2032033fb15fSLuca Weiss interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 2033033fb15fSLuca Weiss power-domains = <&camcc TITAN_TOP_GDSC>; 2034033fb15fSLuca Weiss 2035033fb15fSLuca Weiss clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2036033fb15fSLuca Weiss <&camcc CAMCC_SOC_AHB_CLK>, 2037033fb15fSLuca Weiss <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2038033fb15fSLuca Weiss <&camcc CAMCC_CPAS_AHB_CLK>, 2039033fb15fSLuca Weiss <&camcc CAMCC_CCI_0_CLK>, 2040033fb15fSLuca Weiss <&camcc CAMCC_CCI_0_CLK_SRC>; 2041033fb15fSLuca Weiss clock-names = "camnoc_axi", 2042033fb15fSLuca Weiss "soc_ahb", 2043033fb15fSLuca Weiss "slow_ahb_src", 2044033fb15fSLuca Weiss "cpas_ahb", 2045033fb15fSLuca Weiss "cci", 2046033fb15fSLuca Weiss "cci_src"; 2047033fb15fSLuca Weiss 2048033fb15fSLuca Weiss assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2049033fb15fSLuca Weiss <&camcc CAMCC_CCI_0_CLK>; 2050033fb15fSLuca Weiss assigned-clock-rates = <80000000>, <37500000>; 2051033fb15fSLuca Weiss 2052033fb15fSLuca Weiss pinctrl-0 = <&cci0_default &cci1_default>; 2053033fb15fSLuca Weiss pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2054033fb15fSLuca Weiss pinctrl-names = "default", "sleep"; 2055033fb15fSLuca Weiss 2056033fb15fSLuca Weiss #address-cells = <1>; 2057033fb15fSLuca Weiss #size-cells = <0>; 2058033fb15fSLuca Weiss 2059033fb15fSLuca Weiss status = "disabled"; 2060033fb15fSLuca Weiss 2061033fb15fSLuca Weiss cci0_i2c0: i2c-bus@0 { 2062033fb15fSLuca Weiss reg = <0>; 2063033fb15fSLuca Weiss clock-frequency = <1000000>; 2064033fb15fSLuca Weiss #address-cells = <1>; 2065033fb15fSLuca Weiss #size-cells = <0>; 2066033fb15fSLuca Weiss }; 2067033fb15fSLuca Weiss 2068033fb15fSLuca Weiss cci0_i2c1: i2c-bus@1 { 2069033fb15fSLuca Weiss reg = <1>; 2070033fb15fSLuca Weiss clock-frequency = <1000000>; 2071033fb15fSLuca Weiss #address-cells = <1>; 2072033fb15fSLuca Weiss #size-cells = <0>; 2073033fb15fSLuca Weiss }; 2074033fb15fSLuca Weiss }; 2075033fb15fSLuca Weiss 2076033fb15fSLuca Weiss cci1: cci@ac4b000 { 2077033fb15fSLuca Weiss compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2078a0a287b4SLuca Weiss reg = <0x0 0x0ac4b000 0x0 0x1000>; 2079033fb15fSLuca Weiss interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 2080033fb15fSLuca Weiss power-domains = <&camcc TITAN_TOP_GDSC>; 2081033fb15fSLuca Weiss 2082033fb15fSLuca Weiss clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2083033fb15fSLuca Weiss <&camcc CAMCC_SOC_AHB_CLK>, 2084033fb15fSLuca Weiss <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2085033fb15fSLuca Weiss <&camcc CAMCC_CPAS_AHB_CLK>, 2086033fb15fSLuca Weiss <&camcc CAMCC_CCI_1_CLK>, 2087033fb15fSLuca Weiss <&camcc CAMCC_CCI_1_CLK_SRC>; 2088033fb15fSLuca Weiss clock-names = "camnoc_axi", 2089033fb15fSLuca Weiss "soc_ahb", 2090033fb15fSLuca Weiss "slow_ahb_src", 2091033fb15fSLuca Weiss "cpas_ahb", 2092033fb15fSLuca Weiss "cci", 2093033fb15fSLuca Weiss "cci_src"; 2094033fb15fSLuca Weiss 2095033fb15fSLuca Weiss assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2096033fb15fSLuca Weiss <&camcc CAMCC_CCI_1_CLK>; 2097033fb15fSLuca Weiss assigned-clock-rates = <80000000>, <37500000>; 2098033fb15fSLuca Weiss 2099033fb15fSLuca Weiss pinctrl-0 = <&cci2_default>; 2100033fb15fSLuca Weiss pinctrl-1 = <&cci2_sleep>; 2101033fb15fSLuca Weiss pinctrl-names = "default", "sleep"; 2102033fb15fSLuca Weiss 2103033fb15fSLuca Weiss #address-cells = <1>; 2104033fb15fSLuca Weiss #size-cells = <0>; 2105033fb15fSLuca Weiss 2106033fb15fSLuca Weiss status = "disabled"; 2107033fb15fSLuca Weiss 2108033fb15fSLuca Weiss cci1_i2c0: i2c-bus@0 { 2109033fb15fSLuca Weiss reg = <0>; 2110033fb15fSLuca Weiss clock-frequency = <1000000>; 2111033fb15fSLuca Weiss #address-cells = <1>; 2112033fb15fSLuca Weiss #size-cells = <0>; 2113033fb15fSLuca Weiss }; 2114033fb15fSLuca Weiss 2115033fb15fSLuca Weiss /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 2116033fb15fSLuca Weiss }; 2117033fb15fSLuca Weiss 21184ab96c9cSLuca Weiss camcc: clock-controller@ad00000 { 21194ab96c9cSLuca Weiss compatible = "qcom,sm6350-camcc"; 2120a0a287b4SLuca Weiss reg = <0x0 0x0ad00000 0x0 0x16000>; 21214ab96c9cSLuca Weiss clocks = <&rpmhcc RPMH_CXO_CLK>; 21224ab96c9cSLuca Weiss #clock-cells = <1>; 21234ab96c9cSLuca Weiss #reset-cells = <1>; 21244ab96c9cSLuca Weiss #power-domain-cells = <1>; 21254ab96c9cSLuca Weiss }; 21264ab96c9cSLuca Weiss 212726c71d31SKonrad Dybcio mdss: display-subsystem@ae00000 { 212826c71d31SKonrad Dybcio compatible = "qcom,sm6350-mdss"; 2129a0a287b4SLuca Weiss reg = <0x0 0x0ae00000 0x0 0x1000>; 213026c71d31SKonrad Dybcio reg-names = "mdss"; 213126c71d31SKonrad Dybcio 213226c71d31SKonrad Dybcio interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 213326c71d31SKonrad Dybcio interrupt-controller; 213426c71d31SKonrad Dybcio #interrupt-cells = <1>; 213526c71d31SKonrad Dybcio 2136fc48bb31SLuca Weiss interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2137fc48bb31SLuca Weiss &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2138fc48bb31SLuca Weiss <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 2139fc48bb31SLuca Weiss &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2140fc48bb31SLuca Weiss interconnect-names = "mdp0-mem", 2141fc48bb31SLuca Weiss "cpu-cfg"; 2142fc48bb31SLuca Weiss 214326c71d31SKonrad Dybcio clocks = <&gcc GCC_DISP_AHB_CLK>, 214426c71d31SKonrad Dybcio <&gcc GCC_DISP_AXI_CLK>, 214526c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>; 214626c71d31SKonrad Dybcio clock-names = "iface", 214726c71d31SKonrad Dybcio "bus", 214826c71d31SKonrad Dybcio "core"; 214926c71d31SKonrad Dybcio 215026c71d31SKonrad Dybcio power-domains = <&dispcc MDSS_GDSC>; 215126c71d31SKonrad Dybcio iommus = <&apps_smmu 0x800 0x2>; 215226c71d31SKonrad Dybcio 215326c71d31SKonrad Dybcio #address-cells = <2>; 215426c71d31SKonrad Dybcio #size-cells = <2>; 215526c71d31SKonrad Dybcio ranges; 215626c71d31SKonrad Dybcio 215726c71d31SKonrad Dybcio status = "disabled"; 215826c71d31SKonrad Dybcio 215926c71d31SKonrad Dybcio mdss_mdp: display-controller@ae01000 { 216026c71d31SKonrad Dybcio compatible = "qcom,sm6350-dpu"; 2161a0a287b4SLuca Weiss reg = <0x0 0x0ae01000 0x0 0x8f000>, 2162a0a287b4SLuca Weiss <0x0 0x0aeb0000 0x0 0x2008>; 216326c71d31SKonrad Dybcio reg-names = "mdp", "vbif"; 216426c71d31SKonrad Dybcio 216526c71d31SKonrad Dybcio interrupt-parent = <&mdss>; 216626c71d31SKonrad Dybcio interrupts = <0>; 216726c71d31SKonrad Dybcio 216826c71d31SKonrad Dybcio clocks = <&gcc GCC_DISP_AXI_CLK>, 216926c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 217026c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_ROT_CLK>, 217126c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 217226c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>, 217326c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 217426c71d31SKonrad Dybcio clock-names = "bus", 217526c71d31SKonrad Dybcio "iface", 217626c71d31SKonrad Dybcio "rot", 217726c71d31SKonrad Dybcio "lut", 217826c71d31SKonrad Dybcio "core", 217926c71d31SKonrad Dybcio "vsync"; 218026c71d31SKonrad Dybcio 218126c71d31SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 218226c71d31SKonrad Dybcio assigned-clock-rates = <19200000>; 218326c71d31SKonrad Dybcio 218426c71d31SKonrad Dybcio operating-points-v2 = <&mdp_opp_table>; 218526c71d31SKonrad Dybcio power-domains = <&rpmhpd SM6350_CX>; 218626c71d31SKonrad Dybcio 218726c71d31SKonrad Dybcio ports { 218826c71d31SKonrad Dybcio #address-cells = <1>; 218926c71d31SKonrad Dybcio #size-cells = <0>; 219026c71d31SKonrad Dybcio 219126c71d31SKonrad Dybcio port@0 { 219226c71d31SKonrad Dybcio reg = <0>; 219326c71d31SKonrad Dybcio 219426c71d31SKonrad Dybcio dpu_intf1_out: endpoint { 219526c71d31SKonrad Dybcio remote-endpoint = <&mdss_dsi0_in>; 219626c71d31SKonrad Dybcio }; 219726c71d31SKonrad Dybcio }; 219862f87a3cSLuca Weiss 219962f87a3cSLuca Weiss port@2 { 220062f87a3cSLuca Weiss reg = <2>; 220162f87a3cSLuca Weiss 220262f87a3cSLuca Weiss dpu_intf0_out: endpoint { 220362f87a3cSLuca Weiss remote-endpoint = <&mdss_dp_in>; 220462f87a3cSLuca Weiss }; 220562f87a3cSLuca Weiss }; 220626c71d31SKonrad Dybcio }; 220726c71d31SKonrad Dybcio 220826c71d31SKonrad Dybcio mdp_opp_table: opp-table { 220926c71d31SKonrad Dybcio compatible = "operating-points-v2"; 221026c71d31SKonrad Dybcio 221126c71d31SKonrad Dybcio opp-19200000 { 221226c71d31SKonrad Dybcio opp-hz = /bits/ 64 <19200000>; 221326c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_min_svs>; 221426c71d31SKonrad Dybcio }; 221526c71d31SKonrad Dybcio 221626c71d31SKonrad Dybcio opp-200000000 { 221726c71d31SKonrad Dybcio opp-hz = /bits/ 64 <200000000>; 221826c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 221926c71d31SKonrad Dybcio }; 222026c71d31SKonrad Dybcio 222126c71d31SKonrad Dybcio opp-300000000 { 222226c71d31SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 222326c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 222426c71d31SKonrad Dybcio }; 222526c71d31SKonrad Dybcio 222626c71d31SKonrad Dybcio opp-373333333 { 222726c71d31SKonrad Dybcio opp-hz = /bits/ 64 <373333333>; 222826c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 222926c71d31SKonrad Dybcio }; 223026c71d31SKonrad Dybcio 223126c71d31SKonrad Dybcio opp-448000000 { 223226c71d31SKonrad Dybcio opp-hz = /bits/ 64 <448000000>; 223326c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_nom>; 223426c71d31SKonrad Dybcio }; 223526c71d31SKonrad Dybcio 223626c71d31SKonrad Dybcio opp-560000000 { 223726c71d31SKonrad Dybcio opp-hz = /bits/ 64 <560000000>; 223826c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_turbo>; 223926c71d31SKonrad Dybcio }; 224026c71d31SKonrad Dybcio }; 224126c71d31SKonrad Dybcio }; 224226c71d31SKonrad Dybcio 224362f87a3cSLuca Weiss mdss_dp: displayport-controller@ae90000 { 224462f87a3cSLuca Weiss compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; 2245a0a287b4SLuca Weiss reg = <0x0 0xae90000 0x0 0x200>, 2246a0a287b4SLuca Weiss <0x0 0xae90200 0x0 0x200>, 2247a0a287b4SLuca Weiss <0x0 0xae90400 0x0 0x600>, 2248a0a287b4SLuca Weiss <0x0 0xae91000 0x0 0x400>, 2249a0a287b4SLuca Weiss <0x0 0xae91400 0x0 0x400>; 225062f87a3cSLuca Weiss interrupt-parent = <&mdss>; 225162f87a3cSLuca Weiss interrupts = <12>; 225262f87a3cSLuca Weiss clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 225362f87a3cSLuca Weiss <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 225462f87a3cSLuca Weiss <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 225562f87a3cSLuca Weiss <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 225662f87a3cSLuca Weiss <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 225762f87a3cSLuca Weiss clock-names = "core_iface", 225862f87a3cSLuca Weiss "core_aux", 225962f87a3cSLuca Weiss "ctrl_link", 226062f87a3cSLuca Weiss "ctrl_link_iface", 226162f87a3cSLuca Weiss "stream_pixel"; 226262f87a3cSLuca Weiss 226362f87a3cSLuca Weiss assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 226462f87a3cSLuca Weiss <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 226562f87a3cSLuca Weiss assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 226662f87a3cSLuca Weiss <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 226762f87a3cSLuca Weiss 226862f87a3cSLuca Weiss phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 226962f87a3cSLuca Weiss phy-names = "dp"; 227062f87a3cSLuca Weiss 227162f87a3cSLuca Weiss #sound-dai-cells = <0>; 227262f87a3cSLuca Weiss 227362f87a3cSLuca Weiss operating-points-v2 = <&dp_opp_table>; 227462f87a3cSLuca Weiss power-domains = <&rpmhpd SM6350_CX>; 227562f87a3cSLuca Weiss 227662f87a3cSLuca Weiss status = "disabled"; 227762f87a3cSLuca Weiss 227862f87a3cSLuca Weiss ports { 227962f87a3cSLuca Weiss #address-cells = <1>; 228062f87a3cSLuca Weiss #size-cells = <0>; 228162f87a3cSLuca Weiss 228262f87a3cSLuca Weiss port@0 { 228362f87a3cSLuca Weiss reg = <0>; 228462f87a3cSLuca Weiss 228562f87a3cSLuca Weiss mdss_dp_in: endpoint { 228662f87a3cSLuca Weiss remote-endpoint = <&dpu_intf0_out>; 228762f87a3cSLuca Weiss }; 228862f87a3cSLuca Weiss }; 228962f87a3cSLuca Weiss 229062f87a3cSLuca Weiss port@1 { 229162f87a3cSLuca Weiss reg = <1>; 229262f87a3cSLuca Weiss 229362f87a3cSLuca Weiss mdss_dp_out: endpoint { 229462f87a3cSLuca Weiss }; 229562f87a3cSLuca Weiss }; 229662f87a3cSLuca Weiss }; 229762f87a3cSLuca Weiss 229862f87a3cSLuca Weiss dp_opp_table: opp-table { 229962f87a3cSLuca Weiss compatible = "operating-points-v2"; 230062f87a3cSLuca Weiss 230162f87a3cSLuca Weiss opp-160000000 { 230262f87a3cSLuca Weiss opp-hz = /bits/ 64 <160000000>; 230362f87a3cSLuca Weiss required-opps = <&rpmhpd_opp_low_svs>; 230462f87a3cSLuca Weiss }; 230562f87a3cSLuca Weiss 230662f87a3cSLuca Weiss opp-270000000 { 230762f87a3cSLuca Weiss opp-hz = /bits/ 64 <270000000>; 230862f87a3cSLuca Weiss required-opps = <&rpmhpd_opp_svs>; 230962f87a3cSLuca Weiss }; 231062f87a3cSLuca Weiss 231162f87a3cSLuca Weiss opp-540000000 { 231262f87a3cSLuca Weiss opp-hz = /bits/ 64 <540000000>; 231362f87a3cSLuca Weiss required-opps = <&rpmhpd_opp_svs_l1>; 231462f87a3cSLuca Weiss }; 231562f87a3cSLuca Weiss 231662f87a3cSLuca Weiss opp-810000000 { 231762f87a3cSLuca Weiss opp-hz = /bits/ 64 <810000000>; 231862f87a3cSLuca Weiss required-opps = <&rpmhpd_opp_nom>; 231962f87a3cSLuca Weiss }; 232062f87a3cSLuca Weiss }; 232162f87a3cSLuca Weiss }; 232262f87a3cSLuca Weiss 232326c71d31SKonrad Dybcio mdss_dsi0: dsi@ae94000 { 232426c71d31SKonrad Dybcio compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2325a0a287b4SLuca Weiss reg = <0x0 0x0ae94000 0x0 0x400>; 232626c71d31SKonrad Dybcio reg-names = "dsi_ctrl"; 232726c71d31SKonrad Dybcio 232826c71d31SKonrad Dybcio interrupt-parent = <&mdss>; 232926c71d31SKonrad Dybcio interrupts = <4>; 233026c71d31SKonrad Dybcio 233126c71d31SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 233226c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 233326c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 233426c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC0_CLK>, 233526c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 233626c71d31SKonrad Dybcio <&gcc GCC_DISP_AXI_CLK>; 233726c71d31SKonrad Dybcio clock-names = "byte", 233826c71d31SKonrad Dybcio "byte_intf", 233926c71d31SKonrad Dybcio "pixel", 234026c71d31SKonrad Dybcio "core", 234126c71d31SKonrad Dybcio "iface", 234226c71d31SKonrad Dybcio "bus"; 234326c71d31SKonrad Dybcio 234426c71d31SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 234526c71d31SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2346ab7cd7f3SKrzysztof Kozlowski assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2347ab7cd7f3SKrzysztof Kozlowski <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 234826c71d31SKonrad Dybcio 234926c71d31SKonrad Dybcio operating-points-v2 = <&mdss_dsi_opp_table>; 235026c71d31SKonrad Dybcio power-domains = <&rpmhpd SM6350_MX>; 235126c71d31SKonrad Dybcio 235226c71d31SKonrad Dybcio phys = <&mdss_dsi0_phy>; 235326c71d31SKonrad Dybcio phy-names = "dsi"; 235426c71d31SKonrad Dybcio 235526c71d31SKonrad Dybcio #address-cells = <1>; 235626c71d31SKonrad Dybcio #size-cells = <0>; 235726c71d31SKonrad Dybcio 235826c71d31SKonrad Dybcio status = "disabled"; 235926c71d31SKonrad Dybcio 236026c71d31SKonrad Dybcio ports { 236126c71d31SKonrad Dybcio #address-cells = <1>; 236226c71d31SKonrad Dybcio #size-cells = <0>; 236326c71d31SKonrad Dybcio 236426c71d31SKonrad Dybcio port@0 { 236526c71d31SKonrad Dybcio reg = <0>; 236626c71d31SKonrad Dybcio 236726c71d31SKonrad Dybcio mdss_dsi0_in: endpoint { 236826c71d31SKonrad Dybcio remote-endpoint = <&dpu_intf1_out>; 236926c71d31SKonrad Dybcio }; 237026c71d31SKonrad Dybcio }; 237126c71d31SKonrad Dybcio 237226c71d31SKonrad Dybcio port@1 { 237326c71d31SKonrad Dybcio reg = <1>; 237426c71d31SKonrad Dybcio 237526c71d31SKonrad Dybcio mdss_dsi0_out: endpoint { 237626c71d31SKonrad Dybcio }; 237726c71d31SKonrad Dybcio }; 237826c71d31SKonrad Dybcio }; 237926c71d31SKonrad Dybcio 238026c71d31SKonrad Dybcio mdss_dsi_opp_table: opp-table { 238126c71d31SKonrad Dybcio compatible = "operating-points-v2"; 238226c71d31SKonrad Dybcio 238326c71d31SKonrad Dybcio opp-187500000 { 238426c71d31SKonrad Dybcio opp-hz = /bits/ 64 <187500000>; 238526c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 238626c71d31SKonrad Dybcio }; 238726c71d31SKonrad Dybcio 238826c71d31SKonrad Dybcio opp-300000000 { 238926c71d31SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 239026c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 239126c71d31SKonrad Dybcio }; 239226c71d31SKonrad Dybcio 239326c71d31SKonrad Dybcio opp-358000000 { 239426c71d31SKonrad Dybcio opp-hz = /bits/ 64 <358000000>; 239526c71d31SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 239626c71d31SKonrad Dybcio }; 239726c71d31SKonrad Dybcio }; 239826c71d31SKonrad Dybcio }; 239926c71d31SKonrad Dybcio 240026c71d31SKonrad Dybcio mdss_dsi0_phy: phy@ae94400 { 240126c71d31SKonrad Dybcio compatible = "qcom,dsi-phy-10nm"; 2402a0a287b4SLuca Weiss reg = <0x0 0x0ae94400 0x0 0x200>, 2403a0a287b4SLuca Weiss <0x0 0x0ae94600 0x0 0x280>, 2404a0a287b4SLuca Weiss <0x0 0x0ae94a00 0x0 0x1e0>; 240526c71d31SKonrad Dybcio reg-names = "dsi_phy", 240626c71d31SKonrad Dybcio "dsi_phy_lane", 240726c71d31SKonrad Dybcio "dsi_pll"; 240826c71d31SKonrad Dybcio 240926c71d31SKonrad Dybcio #clock-cells = <1>; 241026c71d31SKonrad Dybcio #phy-cells = <0>; 241126c71d31SKonrad Dybcio 241226c71d31SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 241326c71d31SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 241426c71d31SKonrad Dybcio clock-names = "iface", "ref"; 241526c71d31SKonrad Dybcio 241626c71d31SKonrad Dybcio status = "disabled"; 241726c71d31SKonrad Dybcio }; 241826c71d31SKonrad Dybcio }; 241926c71d31SKonrad Dybcio 242026c71d31SKonrad Dybcio dispcc: clock-controller@af00000 { 242126c71d31SKonrad Dybcio compatible = "qcom,sm6350-dispcc"; 2422a0a287b4SLuca Weiss reg = <0x0 0x0af00000 0x0 0x20000>; 242326c71d31SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 242426c71d31SKonrad Dybcio <&gcc GCC_DISP_GPLL0_CLK>, 2425ab7cd7f3SKrzysztof Kozlowski <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2426ab7cd7f3SKrzysztof Kozlowski <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 242726c71d31SKonrad Dybcio <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 242826c71d31SKonrad Dybcio <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 242926c71d31SKonrad Dybcio clock-names = "bi_tcxo", 243026c71d31SKonrad Dybcio "gcc_disp_gpll0_clk", 243126c71d31SKonrad Dybcio "dsi0_phy_pll_out_byteclk", 243226c71d31SKonrad Dybcio "dsi0_phy_pll_out_dsiclk", 243326c71d31SKonrad Dybcio "dp_phy_pll_link_clk", 243426c71d31SKonrad Dybcio "dp_phy_pll_vco_div_clk"; 243526c71d31SKonrad Dybcio #clock-cells = <1>; 243626c71d31SKonrad Dybcio #reset-cells = <1>; 243726c71d31SKonrad Dybcio #power-domain-cells = <1>; 243826c71d31SKonrad Dybcio }; 243926c71d31SKonrad Dybcio 24405f82b9cdSKonrad Dybcio pdc: interrupt-controller@b220000 { 24415f82b9cdSKonrad Dybcio compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2442a0a287b4SLuca Weiss reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; 24435f82b9cdSKonrad Dybcio qcom,pdc-ranges = <0 480 94>, <94 609 31>, 24445f82b9cdSKonrad Dybcio <125 63 1>, <126 655 12>, <138 139 15>; 24455f82b9cdSKonrad Dybcio #interrupt-cells = <2>; 24465f82b9cdSKonrad Dybcio interrupt-parent = <&intc>; 24475f82b9cdSKonrad Dybcio interrupt-controller; 24485f82b9cdSKonrad Dybcio }; 24495f82b9cdSKonrad Dybcio 245025e0ae68SKonrad Dybcio tsens0: thermal-sensor@c263000 { 245125e0ae68SKonrad Dybcio compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2452a0a287b4SLuca Weiss reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ 2453a0a287b4SLuca Weiss <0x0 0x0c222000 0x0 0x8>; /* SROT */ 245425e0ae68SKonrad Dybcio #qcom,sensors = <16>; 24559e7f7b65SKonrad Dybcio interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 245625e0ae68SKonrad Dybcio <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 245725e0ae68SKonrad Dybcio interrupt-names = "uplow", "critical"; 245825e0ae68SKonrad Dybcio #thermal-sensor-cells = <1>; 245925e0ae68SKonrad Dybcio }; 246025e0ae68SKonrad Dybcio 246125e0ae68SKonrad Dybcio tsens1: thermal-sensor@c265000 { 246225e0ae68SKonrad Dybcio compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2463a0a287b4SLuca Weiss reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ 2464a0a287b4SLuca Weiss <0x0 0x0c223000 0x0 0x8>; /* SROT */ 246525e0ae68SKonrad Dybcio #qcom,sensors = <16>; 24669e7f7b65SKonrad Dybcio interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 246725e0ae68SKonrad Dybcio <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 246825e0ae68SKonrad Dybcio interrupt-names = "uplow", "critical"; 246925e0ae68SKonrad Dybcio #thermal-sensor-cells = <1>; 247025e0ae68SKonrad Dybcio }; 247125e0ae68SKonrad Dybcio 2472bb99820dSKrzysztof Kozlowski aoss_qmp: power-management@c300000 { 24738fe2e0d9SKonrad Dybcio compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2474a0a287b4SLuca Weiss reg = <0x0 0x0c300000 0x0 0x1000>; 24758fe2e0d9SKonrad Dybcio interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 24768fe2e0d9SKonrad Dybcio IRQ_TYPE_EDGE_RISING>; 24778fe2e0d9SKonrad Dybcio mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 24788fe2e0d9SKonrad Dybcio 24798fe2e0d9SKonrad Dybcio #clock-cells = <0>; 24808fe2e0d9SKonrad Dybcio }; 24818fe2e0d9SKonrad Dybcio 2482001eaf95SKonrad Dybcio spmi_bus: spmi@c440000 { 2483001eaf95SKonrad Dybcio compatible = "qcom,spmi-pmic-arb"; 2484a0a287b4SLuca Weiss reg = <0x0 0x0c440000 0x0 0x1100>, 2485a0a287b4SLuca Weiss <0x0 0x0c600000 0x0 0x2000000>, 2486a0a287b4SLuca Weiss <0x0 0x0e600000 0x0 0x100000>, 2487a0a287b4SLuca Weiss <0x0 0x0e700000 0x0 0xa0000>, 2488a0a287b4SLuca Weiss <0x0 0x0c40a000 0x0 0x26000>; 2489001eaf95SKonrad Dybcio reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2490001eaf95SKonrad Dybcio interrupt-names = "periph_irq"; 2491001eaf95SKonrad Dybcio interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2492001eaf95SKonrad Dybcio qcom,ee = <0>; 2493001eaf95SKonrad Dybcio qcom,channel = <0>; 2494001eaf95SKonrad Dybcio #address-cells = <2>; 2495001eaf95SKonrad Dybcio #size-cells = <0>; 2496001eaf95SKonrad Dybcio interrupt-controller; 2497001eaf95SKonrad Dybcio #interrupt-cells = <4>; 2498001eaf95SKonrad Dybcio }; 2499001eaf95SKonrad Dybcio 2500538f4bcdSKonrad Dybcio tlmm: pinctrl@f100000 { 2501538f4bcdSKonrad Dybcio compatible = "qcom,sm6350-tlmm"; 2502a0a287b4SLuca Weiss reg = <0x0 0x0f100000 0x0 0x300000>; 2503538f4bcdSKonrad Dybcio interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2504538f4bcdSKonrad Dybcio <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2505538f4bcdSKonrad Dybcio <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2506538f4bcdSKonrad Dybcio <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2507538f4bcdSKonrad Dybcio <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2508538f4bcdSKonrad Dybcio <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2509538f4bcdSKonrad Dybcio <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2510538f4bcdSKonrad Dybcio <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2511538f4bcdSKonrad Dybcio <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2512538f4bcdSKonrad Dybcio gpio-controller; 2513538f4bcdSKonrad Dybcio #gpio-cells = <2>; 2514538f4bcdSKonrad Dybcio interrupt-controller; 2515538f4bcdSKonrad Dybcio #interrupt-cells = <2>; 2516538f4bcdSKonrad Dybcio gpio-ranges = <&tlmm 0 0 157>; 251790282403SKonrad Dybcio wakeup-parent = <&pdc>; 2518cd10fb79SLuca Weiss 2519033fb15fSLuca Weiss cci0_default: cci0-default-state { 2520033fb15fSLuca Weiss pins = "gpio39", "gpio40"; 2521033fb15fSLuca Weiss function = "cci_i2c"; 2522033fb15fSLuca Weiss drive-strength = <2>; 2523033fb15fSLuca Weiss bias-pull-up; 2524033fb15fSLuca Weiss }; 2525033fb15fSLuca Weiss 2526033fb15fSLuca Weiss cci0_sleep: cci0-sleep-state { 2527033fb15fSLuca Weiss pins = "gpio39", "gpio40"; 2528033fb15fSLuca Weiss function = "cci_i2c"; 2529033fb15fSLuca Weiss drive-strength = <2>; 2530033fb15fSLuca Weiss bias-pull-down; 2531033fb15fSLuca Weiss }; 2532033fb15fSLuca Weiss 2533033fb15fSLuca Weiss cci1_default: cci1-default-state { 2534033fb15fSLuca Weiss pins = "gpio41", "gpio42"; 2535033fb15fSLuca Weiss function = "cci_i2c"; 2536033fb15fSLuca Weiss drive-strength = <2>; 2537033fb15fSLuca Weiss bias-pull-up; 2538033fb15fSLuca Weiss }; 2539033fb15fSLuca Weiss 2540033fb15fSLuca Weiss cci1_sleep: cci1-sleep-state { 2541033fb15fSLuca Weiss pins = "gpio41", "gpio42"; 2542033fb15fSLuca Weiss function = "cci_i2c"; 2543033fb15fSLuca Weiss drive-strength = <2>; 2544033fb15fSLuca Weiss bias-pull-down; 2545033fb15fSLuca Weiss }; 2546033fb15fSLuca Weiss 2547033fb15fSLuca Weiss cci2_default: cci2-default-state { 2548033fb15fSLuca Weiss pins = "gpio43", "gpio44"; 2549033fb15fSLuca Weiss function = "cci_i2c"; 2550033fb15fSLuca Weiss drive-strength = <2>; 2551033fb15fSLuca Weiss bias-pull-up; 2552033fb15fSLuca Weiss }; 2553033fb15fSLuca Weiss 2554033fb15fSLuca Weiss cci2_sleep: cci2-sleep-state { 2555033fb15fSLuca Weiss pins = "gpio43", "gpio44"; 2556033fb15fSLuca Weiss function = "cci_i2c"; 2557033fb15fSLuca Weiss drive-strength = <2>; 2558033fb15fSLuca Weiss bias-pull-down; 2559033fb15fSLuca Weiss }; 2560033fb15fSLuca Weiss 2561a5d0314bSMarijn Suijten sdc2_off_state: sdc2-off-state { 2562a5d0314bSMarijn Suijten clk-pins { 2563a5d0314bSMarijn Suijten pins = "sdc2_clk"; 2564a5d0314bSMarijn Suijten drive-strength = <2>; 2565a5d0314bSMarijn Suijten bias-disable; 2566a5d0314bSMarijn Suijten }; 2567a5d0314bSMarijn Suijten 2568a5d0314bSMarijn Suijten cmd-pins { 2569a5d0314bSMarijn Suijten pins = "sdc2_cmd"; 2570a5d0314bSMarijn Suijten drive-strength = <2>; 2571a5d0314bSMarijn Suijten bias-pull-up; 2572a5d0314bSMarijn Suijten }; 2573a5d0314bSMarijn Suijten 2574a5d0314bSMarijn Suijten data-pins { 2575a5d0314bSMarijn Suijten pins = "sdc2_data"; 2576a5d0314bSMarijn Suijten drive-strength = <2>; 2577a5d0314bSMarijn Suijten bias-pull-up; 2578a5d0314bSMarijn Suijten }; 2579a5d0314bSMarijn Suijten }; 2580a5d0314bSMarijn Suijten 2581a5d0314bSMarijn Suijten sdc2_on_state: sdc2-on-state { 2582a5d0314bSMarijn Suijten clk-pins { 2583a5d0314bSMarijn Suijten pins = "sdc2_clk"; 2584a5d0314bSMarijn Suijten drive-strength = <16>; 2585a5d0314bSMarijn Suijten bias-disable; 2586a5d0314bSMarijn Suijten }; 2587a5d0314bSMarijn Suijten 2588a5d0314bSMarijn Suijten cmd-pins { 2589a5d0314bSMarijn Suijten pins = "sdc2_cmd"; 2590a5d0314bSMarijn Suijten drive-strength = <10>; 2591a5d0314bSMarijn Suijten bias-pull-up; 2592a5d0314bSMarijn Suijten }; 2593a5d0314bSMarijn Suijten 2594a5d0314bSMarijn Suijten data-pins { 2595a5d0314bSMarijn Suijten pins = "sdc2_data"; 2596a5d0314bSMarijn Suijten drive-strength = <10>; 2597a5d0314bSMarijn Suijten bias-pull-up; 2598a5d0314bSMarijn Suijten }; 2599a5d0314bSMarijn Suijten }; 2600a5d0314bSMarijn Suijten 2601448f5a00SKrzysztof Kozlowski qup_uart9_default: qup-uart9-default-state { 2602cd10fb79SLuca Weiss pins = "gpio25", "gpio26"; 2603cd10fb79SLuca Weiss function = "qup13_f2"; 2604cd10fb79SLuca Weiss drive-strength = <2>; 2605cd10fb79SLuca Weiss bias-disable; 2606cd10fb79SLuca Weiss }; 26077be9f3aeSLuca Weiss 2608448f5a00SKrzysztof Kozlowski qup_i2c0_default: qup-i2c0-default-state { 26097be9f3aeSLuca Weiss pins = "gpio0", "gpio1"; 26107be9f3aeSLuca Weiss function = "qup00"; 26117be9f3aeSLuca Weiss drive-strength = <2>; 26127be9f3aeSLuca Weiss bias-pull-up; 26137be9f3aeSLuca Weiss }; 26147be9f3aeSLuca Weiss 2615448f5a00SKrzysztof Kozlowski qup_i2c2_default: qup-i2c2-default-state { 26167be9f3aeSLuca Weiss pins = "gpio45", "gpio46"; 26177be9f3aeSLuca Weiss function = "qup02"; 26187be9f3aeSLuca Weiss drive-strength = <2>; 26197be9f3aeSLuca Weiss bias-pull-up; 26207be9f3aeSLuca Weiss }; 26217be9f3aeSLuca Weiss 2622448f5a00SKrzysztof Kozlowski qup_i2c6_default: qup-i2c6-default-state { 26237be9f3aeSLuca Weiss pins = "gpio13", "gpio14"; 26247be9f3aeSLuca Weiss function = "qup10"; 26257be9f3aeSLuca Weiss drive-strength = <2>; 26267be9f3aeSLuca Weiss bias-pull-up; 26277be9f3aeSLuca Weiss }; 26287be9f3aeSLuca Weiss 2629448f5a00SKrzysztof Kozlowski qup_i2c7_default: qup-i2c7-default-state { 26307be9f3aeSLuca Weiss pins = "gpio27", "gpio28"; 26317be9f3aeSLuca Weiss function = "qup11"; 26327be9f3aeSLuca Weiss drive-strength = <2>; 26337be9f3aeSLuca Weiss bias-pull-up; 26347be9f3aeSLuca Weiss }; 26357be9f3aeSLuca Weiss 2636448f5a00SKrzysztof Kozlowski qup_i2c8_default: qup-i2c8-default-state { 26377be9f3aeSLuca Weiss pins = "gpio19", "gpio20"; 26387be9f3aeSLuca Weiss function = "qup12"; 26397be9f3aeSLuca Weiss drive-strength = <2>; 26407be9f3aeSLuca Weiss bias-pull-up; 26417be9f3aeSLuca Weiss }; 26427be9f3aeSLuca Weiss 2643448f5a00SKrzysztof Kozlowski qup_i2c10_default: qup-i2c10-default-state { 26447be9f3aeSLuca Weiss pins = "gpio4", "gpio5"; 26457be9f3aeSLuca Weiss function = "qup14"; 26467be9f3aeSLuca Weiss drive-strength = <2>; 26477be9f3aeSLuca Weiss bias-pull-up; 26487be9f3aeSLuca Weiss }; 2649b179f35bSLuca Weiss 2650b179f35bSLuca Weiss qup_uart1_cts: qup-uart1-cts-default-state { 2651b179f35bSLuca Weiss pins = "gpio61"; 2652b179f35bSLuca Weiss function = "qup01"; 2653b179f35bSLuca Weiss drive-strength = <2>; 2654b179f35bSLuca Weiss bias-disable; 2655b179f35bSLuca Weiss }; 2656b179f35bSLuca Weiss 2657b179f35bSLuca Weiss qup_uart1_rts: qup-uart1-rts-default-state { 2658b179f35bSLuca Weiss pins = "gpio62"; 2659b179f35bSLuca Weiss function = "qup01"; 2660b179f35bSLuca Weiss drive-strength = <2>; 2661b179f35bSLuca Weiss bias-pull-down; 2662b179f35bSLuca Weiss }; 2663b179f35bSLuca Weiss 2664b179f35bSLuca Weiss qup_uart1_rx: qup-uart1-rx-default-state { 2665b179f35bSLuca Weiss pins = "gpio64"; 2666b179f35bSLuca Weiss function = "qup01"; 2667b179f35bSLuca Weiss drive-strength = <2>; 2668b179f35bSLuca Weiss bias-disable; 2669b179f35bSLuca Weiss }; 2670b179f35bSLuca Weiss 2671b179f35bSLuca Weiss qup_uart1_tx: qup-uart1-tx-default-state { 2672b179f35bSLuca Weiss pins = "gpio63"; 2673b179f35bSLuca Weiss function = "qup01"; 2674b179f35bSLuca Weiss drive-strength = <2>; 2675b179f35bSLuca Weiss bias-pull-up; 2676b179f35bSLuca Weiss }; 2677538f4bcdSKonrad Dybcio }; 2678538f4bcdSKonrad Dybcio 26794ef13f7fSKonrad Dybcio apps_smmu: iommu@15000000 { 26804ef13f7fSKonrad Dybcio compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2681a0a287b4SLuca Weiss reg = <0x0 0x15000000 0x0 0x100000>; 26824ef13f7fSKonrad Dybcio #iommu-cells = <2>; 26834ef13f7fSKonrad Dybcio #global-interrupts = <1>; 26844ef13f7fSKonrad Dybcio interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 26854ef13f7fSKonrad Dybcio <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 26864ef13f7fSKonrad Dybcio <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 26874ef13f7fSKonrad Dybcio <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 26884ef13f7fSKonrad Dybcio <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 26894ef13f7fSKonrad Dybcio <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 26904ef13f7fSKonrad Dybcio <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 26914ef13f7fSKonrad Dybcio <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 26924ef13f7fSKonrad Dybcio <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 26934ef13f7fSKonrad Dybcio <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 26944ef13f7fSKonrad Dybcio <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 26954ef13f7fSKonrad Dybcio <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 26964ef13f7fSKonrad Dybcio <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 26974ef13f7fSKonrad Dybcio <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 26984ef13f7fSKonrad Dybcio <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 26994ef13f7fSKonrad Dybcio <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 27004ef13f7fSKonrad Dybcio <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 27014ef13f7fSKonrad Dybcio <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 27024ef13f7fSKonrad Dybcio <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 27034ef13f7fSKonrad Dybcio <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 27044ef13f7fSKonrad Dybcio <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 27054ef13f7fSKonrad Dybcio <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 27064ef13f7fSKonrad Dybcio <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 27074ef13f7fSKonrad Dybcio <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 27084ef13f7fSKonrad Dybcio <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 27094ef13f7fSKonrad Dybcio <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 27104ef13f7fSKonrad Dybcio <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 27114ef13f7fSKonrad Dybcio <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 27124ef13f7fSKonrad Dybcio <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 27134ef13f7fSKonrad Dybcio <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 27144ef13f7fSKonrad Dybcio <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 27154ef13f7fSKonrad Dybcio <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 27164ef13f7fSKonrad Dybcio <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 27174ef13f7fSKonrad Dybcio <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 27184ef13f7fSKonrad Dybcio <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 27194ef13f7fSKonrad Dybcio <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 27204ef13f7fSKonrad Dybcio <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 27214ef13f7fSKonrad Dybcio <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 27224ef13f7fSKonrad Dybcio <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 27234ef13f7fSKonrad Dybcio <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 27244ef13f7fSKonrad Dybcio <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 27254ef13f7fSKonrad Dybcio <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 27264ef13f7fSKonrad Dybcio <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 27274ef13f7fSKonrad Dybcio <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 27284ef13f7fSKonrad Dybcio <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 27294ef13f7fSKonrad Dybcio <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 27304ef13f7fSKonrad Dybcio <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 27314ef13f7fSKonrad Dybcio <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 27324ef13f7fSKonrad Dybcio <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 27334ef13f7fSKonrad Dybcio <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 27344ef13f7fSKonrad Dybcio <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 27354ef13f7fSKonrad Dybcio <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 27364ef13f7fSKonrad Dybcio <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 27374ef13f7fSKonrad Dybcio <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 27384ef13f7fSKonrad Dybcio <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 27394ef13f7fSKonrad Dybcio <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 27404ef13f7fSKonrad Dybcio <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 27414ef13f7fSKonrad Dybcio <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 27424ef13f7fSKonrad Dybcio <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 27434ef13f7fSKonrad Dybcio <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 27444ef13f7fSKonrad Dybcio <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 27454ef13f7fSKonrad Dybcio <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 27464ef13f7fSKonrad Dybcio <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 27474ef13f7fSKonrad Dybcio <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 27484ef13f7fSKonrad Dybcio <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 27494ef13f7fSKonrad Dybcio <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 27504ef13f7fSKonrad Dybcio <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 27514ef13f7fSKonrad Dybcio <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 27524ef13f7fSKonrad Dybcio <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 27534ef13f7fSKonrad Dybcio <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 27544ef13f7fSKonrad Dybcio <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 27554ef13f7fSKonrad Dybcio <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 27564ef13f7fSKonrad Dybcio <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 27574ef13f7fSKonrad Dybcio <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 27584ef13f7fSKonrad Dybcio <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 27594ef13f7fSKonrad Dybcio <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 27604ef13f7fSKonrad Dybcio <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 27614ef13f7fSKonrad Dybcio <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 27624ef13f7fSKonrad Dybcio <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 27634ef13f7fSKonrad Dybcio <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 27644ef13f7fSKonrad Dybcio <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 27657abe7276SKonrad Dybcio dma-coherent; 27664ef13f7fSKonrad Dybcio }; 27674ef13f7fSKonrad Dybcio 27685f82b9cdSKonrad Dybcio intc: interrupt-controller@17a00000 { 27695f82b9cdSKonrad Dybcio compatible = "arm,gic-v3"; 27705f82b9cdSKonrad Dybcio #interrupt-cells = <3>; 27715f82b9cdSKonrad Dybcio interrupt-controller; 27725f82b9cdSKonrad Dybcio reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 27735f82b9cdSKonrad Dybcio <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 27745f82b9cdSKonrad Dybcio interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 27755f82b9cdSKonrad Dybcio }; 27765f82b9cdSKonrad Dybcio 27775f82b9cdSKonrad Dybcio watchdog@17c10000 { 27785f82b9cdSKonrad Dybcio compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2779a0a287b4SLuca Weiss reg = <0x0 0x17c10000 0x0 0x1000>; 27805f82b9cdSKonrad Dybcio clocks = <&sleep_clk>; 27815b84bb2bSDouglas Anderson interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 27825f82b9cdSKonrad Dybcio }; 27835f82b9cdSKonrad Dybcio 27845f82b9cdSKonrad Dybcio timer@17c20000 { 27855f82b9cdSKonrad Dybcio compatible = "arm,armv7-timer-mem"; 27865f82b9cdSKonrad Dybcio reg = <0x0 0x17c20000 0x0 0x1000>; 27875f82b9cdSKonrad Dybcio clock-frequency = <19200000>; 2788458ebdbbSDavid Heidelberg #address-cells = <1>; 2789458ebdbbSDavid Heidelberg #size-cells = <1>; 2790458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 27915f82b9cdSKonrad Dybcio 27925f82b9cdSKonrad Dybcio frame@17c21000 { 27935f82b9cdSKonrad Dybcio frame-number = <0>; 27945f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 27955f82b9cdSKonrad Dybcio <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2796458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 2797458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 27985f82b9cdSKonrad Dybcio }; 27995f82b9cdSKonrad Dybcio 28005f82b9cdSKonrad Dybcio frame@17c23000 { 28015f82b9cdSKonrad Dybcio frame-number = <1>; 28025f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2803458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 28045f82b9cdSKonrad Dybcio status = "disabled"; 28055f82b9cdSKonrad Dybcio }; 28065f82b9cdSKonrad Dybcio 28075f82b9cdSKonrad Dybcio frame@17c25000 { 28085f82b9cdSKonrad Dybcio frame-number = <2>; 28095f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2810458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 28115f82b9cdSKonrad Dybcio status = "disabled"; 28125f82b9cdSKonrad Dybcio }; 28135f82b9cdSKonrad Dybcio 28145f82b9cdSKonrad Dybcio frame@17c27000 { 28155f82b9cdSKonrad Dybcio frame-number = <3>; 28165f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2817458ebdbbSDavid Heidelberg reg = <0x17c27000 0x1000>; 28185f82b9cdSKonrad Dybcio status = "disabled"; 28195f82b9cdSKonrad Dybcio }; 28205f82b9cdSKonrad Dybcio 28215f82b9cdSKonrad Dybcio frame@17c29000 { 28225f82b9cdSKonrad Dybcio frame-number = <4>; 28235f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2824458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 28255f82b9cdSKonrad Dybcio status = "disabled"; 28265f82b9cdSKonrad Dybcio }; 28275f82b9cdSKonrad Dybcio 28285f82b9cdSKonrad Dybcio frame@17c2b000 { 28295f82b9cdSKonrad Dybcio frame-number = <5>; 28305f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2831458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 28325f82b9cdSKonrad Dybcio status = "disabled"; 28335f82b9cdSKonrad Dybcio }; 28345f82b9cdSKonrad Dybcio 28355f82b9cdSKonrad Dybcio frame@17c2d000 { 28365f82b9cdSKonrad Dybcio frame-number = <6>; 28375f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2838458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 28395f82b9cdSKonrad Dybcio status = "disabled"; 28405f82b9cdSKonrad Dybcio }; 28415f82b9cdSKonrad Dybcio }; 28425f82b9cdSKonrad Dybcio 28435f82b9cdSKonrad Dybcio apps_rsc: rsc@18200000 { 28445f82b9cdSKonrad Dybcio compatible = "qcom,rpmh-rsc"; 28455f82b9cdSKonrad Dybcio label = "apps_rsc"; 28465f82b9cdSKonrad Dybcio reg = <0x0 0x18200000 0x0 0x10000>, 28475f82b9cdSKonrad Dybcio <0x0 0x18210000 0x0 0x10000>, 28485f82b9cdSKonrad Dybcio <0x0 0x18220000 0x0 0x10000>; 28495f82b9cdSKonrad Dybcio reg-names = "drv-0", "drv-1", "drv-2"; 28505f82b9cdSKonrad Dybcio interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 28515f82b9cdSKonrad Dybcio <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 28525f82b9cdSKonrad Dybcio <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 28535f82b9cdSKonrad Dybcio qcom,tcs-offset = <0xd00>; 28545f82b9cdSKonrad Dybcio qcom,drv-id = <2>; 28555f82b9cdSKonrad Dybcio qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 28565f82b9cdSKonrad Dybcio <WAKE_TCS 3>, <CONTROL_TCS 1>; 2857b0864ab2SKrzysztof Kozlowski power-domains = <&cluster_pd>; 2858985e02e7SKonrad Dybcio 2859985e02e7SKonrad Dybcio rpmhcc: clock-controller { 2860985e02e7SKonrad Dybcio compatible = "qcom,sm6350-rpmh-clk"; 2861985e02e7SKonrad Dybcio #clock-cells = <1>; 2862985e02e7SKonrad Dybcio clock-names = "xo"; 2863985e02e7SKonrad Dybcio clocks = <&xo_board>; 2864985e02e7SKonrad Dybcio }; 28659264d3c8SKonrad Dybcio 28669264d3c8SKonrad Dybcio rpmhpd: power-controller { 28679264d3c8SKonrad Dybcio compatible = "qcom,sm6350-rpmhpd"; 28689264d3c8SKonrad Dybcio #power-domain-cells = <1>; 28699264d3c8SKonrad Dybcio operating-points-v2 = <&rpmhpd_opp_table>; 28709264d3c8SKonrad Dybcio 28719264d3c8SKonrad Dybcio rpmhpd_opp_table: opp-table { 28729264d3c8SKonrad Dybcio compatible = "operating-points-v2"; 28739264d3c8SKonrad Dybcio 28749264d3c8SKonrad Dybcio rpmhpd_opp_ret: opp1 { 28759264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 28769264d3c8SKonrad Dybcio }; 28779264d3c8SKonrad Dybcio 28789264d3c8SKonrad Dybcio rpmhpd_opp_min_svs: opp2 { 28799264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 28809264d3c8SKonrad Dybcio }; 28819264d3c8SKonrad Dybcio 28829264d3c8SKonrad Dybcio rpmhpd_opp_low_svs: opp3 { 28839264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 28849264d3c8SKonrad Dybcio }; 28859264d3c8SKonrad Dybcio 28869264d3c8SKonrad Dybcio rpmhpd_opp_svs: opp4 { 28879264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 28889264d3c8SKonrad Dybcio }; 28899264d3c8SKonrad Dybcio 28909264d3c8SKonrad Dybcio rpmhpd_opp_svs_l1: opp5 { 28919264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 28929264d3c8SKonrad Dybcio }; 28939264d3c8SKonrad Dybcio 28949264d3c8SKonrad Dybcio rpmhpd_opp_nom: opp6 { 28959264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 28969264d3c8SKonrad Dybcio }; 28979264d3c8SKonrad Dybcio 28989264d3c8SKonrad Dybcio rpmhpd_opp_nom_l1: opp7 { 28999264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 29009264d3c8SKonrad Dybcio }; 29019264d3c8SKonrad Dybcio 29029264d3c8SKonrad Dybcio rpmhpd_opp_nom_l2: opp8 { 29039264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 29049264d3c8SKonrad Dybcio }; 29059264d3c8SKonrad Dybcio 29069264d3c8SKonrad Dybcio rpmhpd_opp_turbo: opp9 { 29079264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 29089264d3c8SKonrad Dybcio }; 29099264d3c8SKonrad Dybcio 29109264d3c8SKonrad Dybcio rpmhpd_opp_turbo_l1: opp10 { 29119264d3c8SKonrad Dybcio opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 29129264d3c8SKonrad Dybcio }; 29139264d3c8SKonrad Dybcio }; 29149264d3c8SKonrad Dybcio }; 29159264d3c8SKonrad Dybcio 2916fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 29179264d3c8SKonrad Dybcio compatible = "qcom,bcm-voter"; 29189264d3c8SKonrad Dybcio }; 29195f82b9cdSKonrad Dybcio }; 29203cc41541SKonrad Dybcio 2921e17a8065SKonrad Dybcio osm_l3: interconnect@18321000 { 2922e17a8065SKonrad Dybcio compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2923e17a8065SKonrad Dybcio reg = <0x0 0x18321000 0x0 0x1000>; 2924e17a8065SKonrad Dybcio 2925e17a8065SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2926e17a8065SKonrad Dybcio clock-names = "xo", "alternate"; 2927e17a8065SKonrad Dybcio 2928e17a8065SKonrad Dybcio #interconnect-cells = <1>; 2929e17a8065SKonrad Dybcio }; 2930e17a8065SKonrad Dybcio 29313cc41541SKonrad Dybcio cpufreq_hw: cpufreq@18323000 { 293264917707SKonrad Dybcio compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2933a0a287b4SLuca Weiss reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>; 29343cc41541SKonrad Dybcio reg-names = "freq-domain0", "freq-domain1"; 29353cc41541SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 29363cc41541SKonrad Dybcio clock-names = "xo", "alternate"; 29373cc41541SKonrad Dybcio 29383cc41541SKonrad Dybcio #freq-domain-cells = <1>; 2939afa34380SManivannan Sadhasivam #clock-cells = <1>; 29403cc41541SKonrad Dybcio }; 2941fbd47f83SLuca Weiss 2942fbd47f83SLuca Weiss wifi: wifi@18800000 { 2943fbd47f83SLuca Weiss compatible = "qcom,wcn3990-wifi"; 2944a0a287b4SLuca Weiss reg = <0x0 0x18800000 0x0 0x800000>; 2945fbd47f83SLuca Weiss reg-names = "membase"; 2946fbd47f83SLuca Weiss memory-region = <&wlan_fw_mem>; 2947fbd47f83SLuca Weiss interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2948fbd47f83SLuca Weiss <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2949fbd47f83SLuca Weiss <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2950fbd47f83SLuca Weiss <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2951fbd47f83SLuca Weiss <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2952fbd47f83SLuca Weiss <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2953fbd47f83SLuca Weiss <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2954fbd47f83SLuca Weiss <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2955fbd47f83SLuca Weiss <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2956fbd47f83SLuca Weiss <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2957fbd47f83SLuca Weiss <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2958fbd47f83SLuca Weiss <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2959fbd47f83SLuca Weiss iommus = <&apps_smmu 0x20 0x1>; 2960fbd47f83SLuca Weiss qcom,msa-fixed-perm; 2961fbd47f83SLuca Weiss status = "disabled"; 2962fbd47f83SLuca Weiss }; 29635f82b9cdSKonrad Dybcio }; 29645f82b9cdSKonrad Dybcio 296564628795SLuca Weiss thermal-zones { 296664628795SLuca Weiss aoss0-thermal { 296764628795SLuca Weiss thermal-sensors = <&tsens0 0>; 296864628795SLuca Weiss 296964628795SLuca Weiss trips { 297064628795SLuca Weiss aoss0-crit { 297164628795SLuca Weiss temperature = <125000>; 297264628795SLuca Weiss hysteresis = <0>; 297364628795SLuca Weiss type = "critical"; 297464628795SLuca Weiss }; 297564628795SLuca Weiss }; 297664628795SLuca Weiss }; 297764628795SLuca Weiss 297864628795SLuca Weiss aoss1-thermal { 297964628795SLuca Weiss thermal-sensors = <&tsens1 0>; 298064628795SLuca Weiss 298164628795SLuca Weiss trips { 298264628795SLuca Weiss aoss1-crit { 298364628795SLuca Weiss temperature = <125000>; 298464628795SLuca Weiss hysteresis = <0>; 298564628795SLuca Weiss type = "critical"; 298664628795SLuca Weiss }; 298764628795SLuca Weiss }; 298864628795SLuca Weiss }; 298964628795SLuca Weiss 299064628795SLuca Weiss audio-thermal { 299164628795SLuca Weiss thermal-sensors = <&tsens1 2>; 299264628795SLuca Weiss 299364628795SLuca Weiss trips { 299464628795SLuca Weiss audio-crit { 299564628795SLuca Weiss temperature = <125000>; 299664628795SLuca Weiss hysteresis = <0>; 299764628795SLuca Weiss type = "critical"; 299864628795SLuca Weiss }; 299964628795SLuca Weiss }; 300064628795SLuca Weiss }; 300164628795SLuca Weiss 300264628795SLuca Weiss camera-thermal { 300364628795SLuca Weiss thermal-sensors = <&tsens1 5>; 300464628795SLuca Weiss 300564628795SLuca Weiss trips { 300664628795SLuca Weiss camera-crit { 300764628795SLuca Weiss temperature = <125000>; 300864628795SLuca Weiss hysteresis = <0>; 300964628795SLuca Weiss type = "critical"; 301064628795SLuca Weiss }; 301164628795SLuca Weiss }; 301264628795SLuca Weiss }; 301364628795SLuca Weiss 301464628795SLuca Weiss cpu0-thermal { 301564628795SLuca Weiss thermal-sensors = <&tsens0 1>; 301664628795SLuca Weiss 301764628795SLuca Weiss trips { 301864628795SLuca Weiss cpu0_alert0: trip-point0 { 301964628795SLuca Weiss temperature = <95000>; 302064628795SLuca Weiss hysteresis = <2000>; 302164628795SLuca Weiss type = "passive"; 302264628795SLuca Weiss }; 302364628795SLuca Weiss 302464628795SLuca Weiss cpu0-crit { 302564628795SLuca Weiss temperature = <115000>; 302664628795SLuca Weiss hysteresis = <0>; 302764628795SLuca Weiss type = "critical"; 302864628795SLuca Weiss }; 302964628795SLuca Weiss }; 303064628795SLuca Weiss 303164628795SLuca Weiss cooling-maps { 303264628795SLuca Weiss map0 { 303364628795SLuca Weiss trip = <&cpu0_alert0>; 3034b0864ab2SKrzysztof Kozlowski cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 303564628795SLuca Weiss }; 303664628795SLuca Weiss }; 303764628795SLuca Weiss }; 303864628795SLuca Weiss 303964628795SLuca Weiss cpu1-thermal { 304064628795SLuca Weiss thermal-sensors = <&tsens0 2>; 304164628795SLuca Weiss 304264628795SLuca Weiss trips { 304364628795SLuca Weiss cpu1_alert0: trip-point0 { 304464628795SLuca Weiss temperature = <95000>; 304564628795SLuca Weiss hysteresis = <2000>; 304664628795SLuca Weiss type = "passive"; 304764628795SLuca Weiss }; 304864628795SLuca Weiss 304964628795SLuca Weiss cpu1-crit { 305064628795SLuca Weiss temperature = <115000>; 305164628795SLuca Weiss hysteresis = <0>; 305264628795SLuca Weiss type = "critical"; 305364628795SLuca Weiss }; 305464628795SLuca Weiss }; 305564628795SLuca Weiss 305664628795SLuca Weiss cooling-maps { 305764628795SLuca Weiss map0 { 305864628795SLuca Weiss trip = <&cpu1_alert0>; 3059b0864ab2SKrzysztof Kozlowski cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 306064628795SLuca Weiss }; 306164628795SLuca Weiss }; 306264628795SLuca Weiss }; 306364628795SLuca Weiss 306464628795SLuca Weiss cpu2-thermal { 306564628795SLuca Weiss thermal-sensors = <&tsens0 3>; 306664628795SLuca Weiss 306764628795SLuca Weiss trips { 306864628795SLuca Weiss cpu2_alert0: trip-point0 { 306964628795SLuca Weiss temperature = <95000>; 307064628795SLuca Weiss hysteresis = <2000>; 307164628795SLuca Weiss type = "passive"; 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Weiss }; 330964628795SLuca Weiss }; 331064628795SLuca Weiss }; 331164628795SLuca Weiss 331264628795SLuca Weiss gpuss0-thermal { 33131a558bbfSKonrad Dybcio polling-delay-passive = <250>; 33141a558bbfSKonrad Dybcio 331564628795SLuca Weiss thermal-sensors = <&tsens0 13>; 331664628795SLuca Weiss 331764628795SLuca Weiss trips { 331864628795SLuca Weiss gpuss0_alert0: trip-point0 { 33191a558bbfSKonrad Dybcio temperature = <85000>; 332064628795SLuca Weiss hysteresis = <2000>; 332164628795SLuca Weiss type = "passive"; 332264628795SLuca Weiss }; 332364628795SLuca Weiss 332464628795SLuca Weiss gpuss0-crit { 33251a558bbfSKonrad Dybcio temperature = <110000>; 33261a558bbfSKonrad Dybcio hysteresis = <1000>; 332764628795SLuca Weiss type = "critical"; 332864628795SLuca Weiss }; 332964628795SLuca Weiss }; 333064628795SLuca Weiss 333164628795SLuca Weiss cooling-maps { 333264628795SLuca Weiss map0 { 333364628795SLuca Weiss trip = <&gpuss0_alert0>; 333464628795SLuca Weiss cooling-device = <&gpu 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336164628795SLuca Weiss cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 336264628795SLuca Weiss }; 336364628795SLuca Weiss }; 336464628795SLuca Weiss }; 336564628795SLuca Weiss 336664628795SLuca Weiss modem-core0-thermal { 336764628795SLuca Weiss thermal-sensors = <&tsens1 6>; 336864628795SLuca Weiss 336964628795SLuca Weiss trips { 337064628795SLuca Weiss modem-core0-crit { 337164628795SLuca Weiss temperature = <125000>; 337264628795SLuca Weiss hysteresis = <0>; 337364628795SLuca Weiss type = "critical"; 337464628795SLuca Weiss }; 337564628795SLuca Weiss }; 337664628795SLuca Weiss }; 337764628795SLuca Weiss 337864628795SLuca Weiss modem-core1-thermal { 337964628795SLuca Weiss thermal-sensors = <&tsens1 7>; 338064628795SLuca Weiss 338164628795SLuca Weiss trips { 338264628795SLuca Weiss modem-core1-crit { 338364628795SLuca Weiss temperature = <125000>; 338464628795SLuca Weiss hysteresis = <0>; 338564628795SLuca Weiss type = "critical"; 338664628795SLuca Weiss }; 338764628795SLuca Weiss }; 338864628795SLuca Weiss }; 338964628795SLuca Weiss 339064628795SLuca Weiss modem-scl-thermal { 339164628795SLuca Weiss thermal-sensors = <&tsens1 9>; 339264628795SLuca Weiss 339364628795SLuca Weiss trips { 339464628795SLuca Weiss modem-scl-crit { 339564628795SLuca Weiss temperature = <125000>; 339664628795SLuca Weiss hysteresis = <0>; 339764628795SLuca Weiss type = "critical"; 339864628795SLuca Weiss }; 339964628795SLuca Weiss }; 340064628795SLuca Weiss }; 340164628795SLuca Weiss 340264628795SLuca Weiss modem-vec-thermal { 340364628795SLuca Weiss thermal-sensors = <&tsens1 8>; 340464628795SLuca Weiss 340564628795SLuca Weiss trips { 340664628795SLuca Weiss modem-vec-crit { 340764628795SLuca Weiss temperature = <125000>; 340864628795SLuca Weiss hysteresis = <0>; 340964628795SLuca Weiss type = "critical"; 341064628795SLuca Weiss }; 341164628795SLuca Weiss }; 341264628795SLuca Weiss }; 341364628795SLuca Weiss 341464628795SLuca Weiss npu-thermal { 341564628795SLuca Weiss thermal-sensors = <&tsens1 10>; 341664628795SLuca Weiss 341764628795SLuca Weiss trips { 341864628795SLuca Weiss npu-crit { 341964628795SLuca Weiss temperature = <125000>; 342064628795SLuca Weiss hysteresis = <0>; 342164628795SLuca Weiss type = "critical"; 342264628795SLuca Weiss }; 342364628795SLuca Weiss }; 342464628795SLuca Weiss }; 342564628795SLuca Weiss 342664628795SLuca Weiss q6-hvx-thermal { 342764628795SLuca Weiss thermal-sensors = <&tsens1 4>; 342864628795SLuca Weiss 342964628795SLuca Weiss trips { 343064628795SLuca Weiss q6-hvx-crit { 343164628795SLuca Weiss temperature = <125000>; 343264628795SLuca Weiss hysteresis = <0>; 343364628795SLuca Weiss type = "critical"; 343464628795SLuca Weiss }; 343564628795SLuca Weiss }; 343664628795SLuca Weiss }; 343764628795SLuca Weiss 343864628795SLuca Weiss video-thermal { 343964628795SLuca Weiss thermal-sensors = <&tsens1 11>; 344064628795SLuca Weiss 344164628795SLuca Weiss trips { 344264628795SLuca Weiss video-crit { 344364628795SLuca Weiss temperature = <125000>; 344464628795SLuca Weiss hysteresis = <0>; 344564628795SLuca Weiss type = "critical"; 344664628795SLuca Weiss }; 344764628795SLuca Weiss }; 344864628795SLuca Weiss }; 344964628795SLuca Weiss }; 345064628795SLuca Weiss 34515f82b9cdSKonrad Dybcio timer { 34525f82b9cdSKonrad Dybcio compatible = "arm,armv8-timer"; 34535f82b9cdSKonrad Dybcio clock-frequency = <19200000>; 34545f82b9cdSKonrad Dybcio interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 34555f82b9cdSKonrad Dybcio <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 34565f82b9cdSKonrad Dybcio <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 34575f82b9cdSKonrad Dybcio <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 34585f82b9cdSKonrad Dybcio }; 34595f82b9cdSKonrad Dybcio}; 3460