1*1cde54c5SRoger Shimizu// SPDX-License-Identifier: BSD-3-Clause 2*1cde54c5SRoger Shimizu/* 3*1cde54c5SRoger Shimizu * Copyright (c) 2026, Roger Shimizu <rosh@debian.org> 4*1cde54c5SRoger Shimizu */ 5*1cde54c5SRoger Shimizu 6*1cde54c5SRoger Shimizu/dts-v1/; 7*1cde54c5SRoger Shimizu 8*1cde54c5SRoger Shimizu/* PM7250B is configured to use SID8/9 */ 9*1cde54c5SRoger Shimizu#define PM7250B_SID 8 10*1cde54c5SRoger Shimizu#define PM7250B_SID1 9 11*1cde54c5SRoger Shimizu 12*1cde54c5SRoger Shimizu#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> 13*1cde54c5SRoger Shimizu#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> 14*1cde54c5SRoger Shimizu#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 15*1cde54c5SRoger Shimizu#include "kodiak.dtsi" 16*1cde54c5SRoger Shimizu#include "pm7250b.dtsi" 17*1cde54c5SRoger Shimizu#include "pm7325.dtsi" 18*1cde54c5SRoger Shimizu#include "pm8350c.dtsi" /* PM7350C */ 19*1cde54c5SRoger Shimizu#include "pmk8350.dtsi" /* PMK7325 */ 20*1cde54c5SRoger Shimizu 21*1cde54c5SRoger Shimizu/delete-node/ &adsp_mem; 22*1cde54c5SRoger Shimizu/delete-node/ &cdsp_mem; 23*1cde54c5SRoger Shimizu/delete-node/ &ipa_fw_mem; 24*1cde54c5SRoger Shimizu/delete-node/ &mpss_mem; 25*1cde54c5SRoger Shimizu/delete-node/ &remoteproc_mpss; 26*1cde54c5SRoger Shimizu/delete-node/ &remoteproc_wpss; 27*1cde54c5SRoger Shimizu/delete-node/ &rmtfs_mem; 28*1cde54c5SRoger Shimizu/delete-node/ &video_mem; 29*1cde54c5SRoger Shimizu/delete-node/ &wifi; 30*1cde54c5SRoger Shimizu/delete-node/ &wlan_ce_mem; 31*1cde54c5SRoger Shimizu/delete-node/ &wlan_fw_mem; 32*1cde54c5SRoger Shimizu/delete-node/ &wpss_mem; 33*1cde54c5SRoger Shimizu/delete-node/ &xbl_mem; 34*1cde54c5SRoger Shimizu 35*1cde54c5SRoger Shimizu/ { 36*1cde54c5SRoger Shimizu model = "Thundercomm AI Mini PC G1 IoT"; 37*1cde54c5SRoger Shimizu compatible = "thundercomm,minipc-g1iot", "qcom,qcm6490"; 38*1cde54c5SRoger Shimizu chassis-type = "desktop"; 39*1cde54c5SRoger Shimizu 40*1cde54c5SRoger Shimizu aliases { 41*1cde54c5SRoger Shimizu serial0 = &uart5; 42*1cde54c5SRoger Shimizu }; 43*1cde54c5SRoger Shimizu 44*1cde54c5SRoger Shimizu chosen { 45*1cde54c5SRoger Shimizu stdout-path = "serial0:115200n8"; 46*1cde54c5SRoger Shimizu }; 47*1cde54c5SRoger Shimizu 48*1cde54c5SRoger Shimizu hdmi-connector { 49*1cde54c5SRoger Shimizu compatible = "hdmi-connector"; 50*1cde54c5SRoger Shimizu type = "a"; 51*1cde54c5SRoger Shimizu 52*1cde54c5SRoger Shimizu port { 53*1cde54c5SRoger Shimizu hdmi_con: endpoint { 54*1cde54c5SRoger Shimizu remote-endpoint = <<9611_out>; 55*1cde54c5SRoger Shimizu }; 56*1cde54c5SRoger Shimizu }; 57*1cde54c5SRoger Shimizu }; 58*1cde54c5SRoger Shimizu 59*1cde54c5SRoger Shimizu pmic-glink { 60*1cde54c5SRoger Shimizu compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; 61*1cde54c5SRoger Shimizu 62*1cde54c5SRoger Shimizu #address-cells = <1>; 63*1cde54c5SRoger Shimizu #size-cells = <0>; 64*1cde54c5SRoger Shimizu orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; 65*1cde54c5SRoger Shimizu 66*1cde54c5SRoger Shimizu connector@0 { 67*1cde54c5SRoger Shimizu compatible = "usb-c-connector"; 68*1cde54c5SRoger Shimizu reg = <0>; 69*1cde54c5SRoger Shimizu power-role = "dual"; 70*1cde54c5SRoger Shimizu data-role = "dual"; 71*1cde54c5SRoger Shimizu 72*1cde54c5SRoger Shimizu ports { 73*1cde54c5SRoger Shimizu #address-cells = <1>; 74*1cde54c5SRoger Shimizu #size-cells = <0>; 75*1cde54c5SRoger Shimizu 76*1cde54c5SRoger Shimizu port@0 { 77*1cde54c5SRoger Shimizu reg = <0>; 78*1cde54c5SRoger Shimizu 79*1cde54c5SRoger Shimizu pmic_glink_hs_in: endpoint { 80*1cde54c5SRoger Shimizu remote-endpoint = <&usb_1_dwc3_hs>; 81*1cde54c5SRoger Shimizu }; 82*1cde54c5SRoger Shimizu }; 83*1cde54c5SRoger Shimizu 84*1cde54c5SRoger Shimizu port@1 { 85*1cde54c5SRoger Shimizu reg = <1>; 86*1cde54c5SRoger Shimizu 87*1cde54c5SRoger Shimizu pmic_glink_ss_in: endpoint { 88*1cde54c5SRoger Shimizu remote-endpoint = <&redriver_usb_con_ss>; 89*1cde54c5SRoger Shimizu }; 90*1cde54c5SRoger Shimizu }; 91*1cde54c5SRoger Shimizu 92*1cde54c5SRoger Shimizu port@2 { 93*1cde54c5SRoger Shimizu reg = <2>; 94*1cde54c5SRoger Shimizu 95*1cde54c5SRoger Shimizu pmic_glink_sbu_in: endpoint { 96*1cde54c5SRoger Shimizu remote-endpoint = <&redriver_usb_con_sbu>; 97*1cde54c5SRoger Shimizu }; 98*1cde54c5SRoger Shimizu }; 99*1cde54c5SRoger Shimizu }; 100*1cde54c5SRoger Shimizu }; 101*1cde54c5SRoger Shimizu }; 102*1cde54c5SRoger Shimizu 103*1cde54c5SRoger Shimizu lt9611_1v2: regulator-lt9611-vdd12 { 104*1cde54c5SRoger Shimizu compatible = "regulator-fixed"; 105*1cde54c5SRoger Shimizu regulator-name = "LT9611_1V2"; 106*1cde54c5SRoger Shimizu 107*1cde54c5SRoger Shimizu regulator-min-microvolt = <1200000>; 108*1cde54c5SRoger Shimizu regulator-max-microvolt = <1200000>; 109*1cde54c5SRoger Shimizu }; 110*1cde54c5SRoger Shimizu 111*1cde54c5SRoger Shimizu reserved-memory { 112*1cde54c5SRoger Shimizu xbl_mem: xbl@80700000 { 113*1cde54c5SRoger Shimizu reg = <0x0 0x80700000 0x0 0x100000>; 114*1cde54c5SRoger Shimizu no-map; 115*1cde54c5SRoger Shimizu }; 116*1cde54c5SRoger Shimizu 117*1cde54c5SRoger Shimizu cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { 118*1cde54c5SRoger Shimizu reg = <0x0 0x81800000 0x0 0x1e00000>; 119*1cde54c5SRoger Shimizu no-map; 120*1cde54c5SRoger Shimizu }; 121*1cde54c5SRoger Shimizu 122*1cde54c5SRoger Shimizu camera_mem: camera@84300000 { 123*1cde54c5SRoger Shimizu reg = <0x0 0x84300000 0x0 0x500000>; 124*1cde54c5SRoger Shimizu no-map; 125*1cde54c5SRoger Shimizu }; 126*1cde54c5SRoger Shimizu 127*1cde54c5SRoger Shimizu adsp_mem: adsp@86100000 { 128*1cde54c5SRoger Shimizu reg = <0x0 0x86100000 0x0 0x2800000>; 129*1cde54c5SRoger Shimizu no-map; 130*1cde54c5SRoger Shimizu }; 131*1cde54c5SRoger Shimizu 132*1cde54c5SRoger Shimizu cdsp_mem: cdsp@88900000 { 133*1cde54c5SRoger Shimizu reg = <0x0 0x88900000 0x0 0x1e00000>; 134*1cde54c5SRoger Shimizu no-map; 135*1cde54c5SRoger Shimizu }; 136*1cde54c5SRoger Shimizu 137*1cde54c5SRoger Shimizu video_mem: video@8a700000 { 138*1cde54c5SRoger Shimizu reg = <0x0 0x8a700000 0x0 0x700000>; 139*1cde54c5SRoger Shimizu no-map; 140*1cde54c5SRoger Shimizu }; 141*1cde54c5SRoger Shimizu 142*1cde54c5SRoger Shimizu cvp_mem: cvp@8ae00000 { 143*1cde54c5SRoger Shimizu reg = <0x0 0x8ae00000 0x0 0x500000>; 144*1cde54c5SRoger Shimizu no-map; 145*1cde54c5SRoger Shimizu }; 146*1cde54c5SRoger Shimizu 147*1cde54c5SRoger Shimizu gpu_microcode_mem: gpu-microcode@8b31a000 { 148*1cde54c5SRoger Shimizu reg = <0x0 0x8b31a000 0x0 0x2000>; 149*1cde54c5SRoger Shimizu no-map; 150*1cde54c5SRoger Shimizu }; 151*1cde54c5SRoger Shimizu 152*1cde54c5SRoger Shimizu tz_stat_mem: tz-stat@c0000000 { 153*1cde54c5SRoger Shimizu reg = <0x0 0xc0000000 0x0 0x100000>; 154*1cde54c5SRoger Shimizu no-map; 155*1cde54c5SRoger Shimizu }; 156*1cde54c5SRoger Shimizu 157*1cde54c5SRoger Shimizu tags_mem: tags@c0100000 { 158*1cde54c5SRoger Shimizu reg = <0x0 0xc0100000 0x0 0x1200000>; 159*1cde54c5SRoger Shimizu no-map; 160*1cde54c5SRoger Shimizu }; 161*1cde54c5SRoger Shimizu 162*1cde54c5SRoger Shimizu qtee_mem: qtee@c1300000 { 163*1cde54c5SRoger Shimizu reg = <0x0 0xc1300000 0x0 0x500000>; 164*1cde54c5SRoger Shimizu no-map; 165*1cde54c5SRoger Shimizu }; 166*1cde54c5SRoger Shimizu 167*1cde54c5SRoger Shimizu trusted_apps_mem: trusted-apps@c1800000 { 168*1cde54c5SRoger Shimizu reg = <0x0 0xc1800000 0x0 0x1c00000>; 169*1cde54c5SRoger Shimizu no-map; 170*1cde54c5SRoger Shimizu }; 171*1cde54c5SRoger Shimizu 172*1cde54c5SRoger Shimizu debug_vm_mem: debug-vm@d0600000 { 173*1cde54c5SRoger Shimizu reg = <0x0 0xd0600000 0x0 0x100000>; 174*1cde54c5SRoger Shimizu no-map; 175*1cde54c5SRoger Shimizu }; 176*1cde54c5SRoger Shimizu }; 177*1cde54c5SRoger Shimizu 178*1cde54c5SRoger Shimizu vdd_ntn_0p9: regulator-vdd-ntn-0p9 { 179*1cde54c5SRoger Shimizu compatible = "regulator-fixed"; 180*1cde54c5SRoger Shimizu regulator-name = "VDD_NTN_0P9"; 181*1cde54c5SRoger Shimizu gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; 182*1cde54c5SRoger Shimizu regulator-min-microvolt = <899400>; 183*1cde54c5SRoger Shimizu regulator-max-microvolt = <899400>; 184*1cde54c5SRoger Shimizu enable-active-high; 185*1cde54c5SRoger Shimizu pinctrl-0 = <&ntn_0p9_en>; 186*1cde54c5SRoger Shimizu pinctrl-names = "default"; 187*1cde54c5SRoger Shimizu regulator-enable-ramp-delay = <4300>; 188*1cde54c5SRoger Shimizu }; 189*1cde54c5SRoger Shimizu 190*1cde54c5SRoger Shimizu vdd_ntn_1p8: regulator-vdd-ntn-1p8 { 191*1cde54c5SRoger Shimizu compatible = "regulator-fixed"; 192*1cde54c5SRoger Shimizu regulator-name = "VDD_NTN_1P8"; 193*1cde54c5SRoger Shimizu gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; 194*1cde54c5SRoger Shimizu regulator-min-microvolt = <1800000>; 195*1cde54c5SRoger Shimizu regulator-max-microvolt = <1800000>; 196*1cde54c5SRoger Shimizu enable-active-high; 197*1cde54c5SRoger Shimizu pinctrl-0 = <&ntn_1p8_en>; 198*1cde54c5SRoger Shimizu pinctrl-names = "default"; 199*1cde54c5SRoger Shimizu regulator-enable-ramp-delay = <10000>; 200*1cde54c5SRoger Shimizu }; 201*1cde54c5SRoger Shimizu 202*1cde54c5SRoger Shimizu vph_pwr: regulator-vph-pwr { 203*1cde54c5SRoger Shimizu compatible = "regulator-fixed"; 204*1cde54c5SRoger Shimizu regulator-name = "vph_pwr"; 205*1cde54c5SRoger Shimizu regulator-min-microvolt = <3700000>; 206*1cde54c5SRoger Shimizu regulator-max-microvolt = <3700000>; 207*1cde54c5SRoger Shimizu }; 208*1cde54c5SRoger Shimizu 209*1cde54c5SRoger Shimizu thermal-zones { 210*1cde54c5SRoger Shimizu sdm-skin-thermal { 211*1cde54c5SRoger Shimizu thermal-sensors = <&pmk8350_adc_tm 3>; 212*1cde54c5SRoger Shimizu 213*1cde54c5SRoger Shimizu trips { 214*1cde54c5SRoger Shimizu active-config0 { 215*1cde54c5SRoger Shimizu temperature = <125000>; 216*1cde54c5SRoger Shimizu hysteresis = <1000>; 217*1cde54c5SRoger Shimizu type = "passive"; 218*1cde54c5SRoger Shimizu }; 219*1cde54c5SRoger Shimizu }; 220*1cde54c5SRoger Shimizu }; 221*1cde54c5SRoger Shimizu 222*1cde54c5SRoger Shimizu quiet-thermal { 223*1cde54c5SRoger Shimizu thermal-sensors = <&pmk8350_adc_tm 1>; 224*1cde54c5SRoger Shimizu 225*1cde54c5SRoger Shimizu trips { 226*1cde54c5SRoger Shimizu active-config0 { 227*1cde54c5SRoger Shimizu temperature = <125000>; 228*1cde54c5SRoger Shimizu hysteresis = <1000>; 229*1cde54c5SRoger Shimizu type = "passive"; 230*1cde54c5SRoger Shimizu }; 231*1cde54c5SRoger Shimizu }; 232*1cde54c5SRoger Shimizu }; 233*1cde54c5SRoger Shimizu 234*1cde54c5SRoger Shimizu xo-thermal { 235*1cde54c5SRoger Shimizu thermal-sensors = <&pmk8350_adc_tm 0>; 236*1cde54c5SRoger Shimizu 237*1cde54c5SRoger Shimizu trips { 238*1cde54c5SRoger Shimizu active-config0 { 239*1cde54c5SRoger Shimizu temperature = <125000>; 240*1cde54c5SRoger Shimizu hysteresis = <1000>; 241*1cde54c5SRoger Shimizu type = "passive"; 242*1cde54c5SRoger Shimizu }; 243*1cde54c5SRoger Shimizu }; 244*1cde54c5SRoger Shimizu }; 245*1cde54c5SRoger Shimizu }; 246*1cde54c5SRoger Shimizu}; 247*1cde54c5SRoger Shimizu 248*1cde54c5SRoger Shimizu&apps_rsc { 249*1cde54c5SRoger Shimizu regulators-0 { 250*1cde54c5SRoger Shimizu compatible = "qcom,pm7325-rpmh-regulators"; 251*1cde54c5SRoger Shimizu qcom,pmic-id = "b"; 252*1cde54c5SRoger Shimizu 253*1cde54c5SRoger Shimizu vdd-s1-supply = <&vph_pwr>; 254*1cde54c5SRoger Shimizu vdd-s2-supply = <&vph_pwr>; 255*1cde54c5SRoger Shimizu vdd-s3-supply = <&vph_pwr>; 256*1cde54c5SRoger Shimizu vdd-s4-supply = <&vph_pwr>; 257*1cde54c5SRoger Shimizu vdd-s5-supply = <&vph_pwr>; 258*1cde54c5SRoger Shimizu vdd-s6-supply = <&vph_pwr>; 259*1cde54c5SRoger Shimizu vdd-s7-supply = <&vph_pwr>; 260*1cde54c5SRoger Shimizu vdd-s8-supply = <&vph_pwr>; 261*1cde54c5SRoger Shimizu vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; 262*1cde54c5SRoger Shimizu vdd-l2-l7-supply = <&vreg_bob_3p296>; 263*1cde54c5SRoger Shimizu vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; 264*1cde54c5SRoger Shimizu vdd-l8-supply = <&vreg_s7b_0p972>; 265*1cde54c5SRoger Shimizu vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; 266*1cde54c5SRoger Shimizu vdd-l13-supply = <&vreg_s7b_0p972>; 267*1cde54c5SRoger Shimizu vdd-l14-l16-supply = <&vreg_s8b_1p272>; 268*1cde54c5SRoger Shimizu 269*1cde54c5SRoger Shimizu vreg_s1b_1p872: smps1 { 270*1cde54c5SRoger Shimizu regulator-name = "vreg_s1b_1p872"; 271*1cde54c5SRoger Shimizu regulator-min-microvolt = <1840000>; 272*1cde54c5SRoger Shimizu regulator-max-microvolt = <2040000>; 273*1cde54c5SRoger Shimizu }; 274*1cde54c5SRoger Shimizu 275*1cde54c5SRoger Shimizu vreg_s7b_0p972: smps7 { 276*1cde54c5SRoger Shimizu regulator-name = "vreg_s7b_0p972"; 277*1cde54c5SRoger Shimizu regulator-min-microvolt = <535000>; 278*1cde54c5SRoger Shimizu regulator-max-microvolt = <1120000>; 279*1cde54c5SRoger Shimizu }; 280*1cde54c5SRoger Shimizu 281*1cde54c5SRoger Shimizu vreg_s8b_1p272: smps8 { 282*1cde54c5SRoger Shimizu regulator-name = "vreg_s8b_1p272"; 283*1cde54c5SRoger Shimizu regulator-min-microvolt = <1200000>; 284*1cde54c5SRoger Shimizu regulator-max-microvolt = <1500000>; 285*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; 286*1cde54c5SRoger Shimizu }; 287*1cde54c5SRoger Shimizu 288*1cde54c5SRoger Shimizu vreg_l1b_0p912: ldo1 { 289*1cde54c5SRoger Shimizu regulator-name = "vreg_l1b_0p912"; 290*1cde54c5SRoger Shimizu regulator-min-microvolt = <825000>; 291*1cde54c5SRoger Shimizu regulator-max-microvolt = <925000>; 292*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 293*1cde54c5SRoger Shimizu }; 294*1cde54c5SRoger Shimizu 295*1cde54c5SRoger Shimizu vreg_l2b_3p072: ldo2 { 296*1cde54c5SRoger Shimizu regulator-name = "vreg_l2b_3p072"; 297*1cde54c5SRoger Shimizu regulator-min-microvolt = <2700000>; 298*1cde54c5SRoger Shimizu regulator-max-microvolt = <3544000>; 299*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 300*1cde54c5SRoger Shimizu }; 301*1cde54c5SRoger Shimizu 302*1cde54c5SRoger Shimizu vreg_l3b_0p504: ldo3 { 303*1cde54c5SRoger Shimizu regulator-name = "vreg_l3b_0p504"; 304*1cde54c5SRoger Shimizu regulator-min-microvolt = <312000>; 305*1cde54c5SRoger Shimizu regulator-max-microvolt = <650000>; 306*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 307*1cde54c5SRoger Shimizu }; 308*1cde54c5SRoger Shimizu 309*1cde54c5SRoger Shimizu vreg_l6b_1p2: ldo6 { 310*1cde54c5SRoger Shimizu regulator-name = "vreg_l6b_1p2"; 311*1cde54c5SRoger Shimizu regulator-min-microvolt = <1200000>; 312*1cde54c5SRoger Shimizu regulator-max-microvolt = <1260000>; 313*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 314*1cde54c5SRoger Shimizu }; 315*1cde54c5SRoger Shimizu 316*1cde54c5SRoger Shimizu vreg_l7b_2p952: ldo7 { 317*1cde54c5SRoger Shimizu regulator-name = "vreg_l7b_2p952"; 318*1cde54c5SRoger Shimizu regulator-min-microvolt = <2952000>; 319*1cde54c5SRoger Shimizu regulator-max-microvolt = <2952000>; 320*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 321*1cde54c5SRoger Shimizu }; 322*1cde54c5SRoger Shimizu 323*1cde54c5SRoger Shimizu vreg_l8b_0p904: ldo8 { 324*1cde54c5SRoger Shimizu regulator-name = "vreg_l8b_0p904"; 325*1cde54c5SRoger Shimizu regulator-min-microvolt = <870000>; 326*1cde54c5SRoger Shimizu regulator-max-microvolt = <970000>; 327*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 328*1cde54c5SRoger Shimizu }; 329*1cde54c5SRoger Shimizu 330*1cde54c5SRoger Shimizu vreg_l9b_1p2: ldo9 { 331*1cde54c5SRoger Shimizu regulator-name = "vreg_l9b_1p2"; 332*1cde54c5SRoger Shimizu regulator-min-microvolt = <1200000>; 333*1cde54c5SRoger Shimizu regulator-max-microvolt = <1200000>; 334*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 335*1cde54c5SRoger Shimizu regulator-allow-set-load; 336*1cde54c5SRoger Shimizu regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM 337*1cde54c5SRoger Shimizu RPMH_REGULATOR_MODE_HPM>; 338*1cde54c5SRoger Shimizu }; 339*1cde54c5SRoger Shimizu 340*1cde54c5SRoger Shimizu vreg_l11b_1p504: ldo11 { 341*1cde54c5SRoger Shimizu regulator-name = "vreg_l11b_1p504"; 342*1cde54c5SRoger Shimizu regulator-min-microvolt = <1776000>; 343*1cde54c5SRoger Shimizu regulator-max-microvolt = <2000000>; 344*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 345*1cde54c5SRoger Shimizu }; 346*1cde54c5SRoger Shimizu 347*1cde54c5SRoger Shimizu vreg_l12b_0p751: ldo12 { 348*1cde54c5SRoger Shimizu regulator-name = "vreg_l12b_0p751"; 349*1cde54c5SRoger Shimizu regulator-min-microvolt = <751000>; 350*1cde54c5SRoger Shimizu regulator-max-microvolt = <824000>; 351*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 352*1cde54c5SRoger Shimizu }; 353*1cde54c5SRoger Shimizu 354*1cde54c5SRoger Shimizu vreg_l13b_0p53: ldo13 { 355*1cde54c5SRoger Shimizu regulator-name = "vreg_l13b_0p53"; 356*1cde54c5SRoger Shimizu regulator-min-microvolt = <530000>; 357*1cde54c5SRoger Shimizu regulator-max-microvolt = <824000>; 358*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 359*1cde54c5SRoger Shimizu }; 360*1cde54c5SRoger Shimizu 361*1cde54c5SRoger Shimizu vreg_l14b_1p08: ldo14 { 362*1cde54c5SRoger Shimizu regulator-name = "vreg_l14b_1p08"; 363*1cde54c5SRoger Shimizu regulator-min-microvolt = <1200000>; 364*1cde54c5SRoger Shimizu regulator-max-microvolt = <1304000>; 365*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 366*1cde54c5SRoger Shimizu }; 367*1cde54c5SRoger Shimizu 368*1cde54c5SRoger Shimizu vreg_l15b_0p765: ldo15 { 369*1cde54c5SRoger Shimizu regulator-name = "vreg_l15b_0p765"; 370*1cde54c5SRoger Shimizu regulator-min-microvolt = <765000>; 371*1cde54c5SRoger Shimizu regulator-max-microvolt = <1020000>; 372*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 373*1cde54c5SRoger Shimizu }; 374*1cde54c5SRoger Shimizu 375*1cde54c5SRoger Shimizu vreg_l16b_1p1: ldo16 { 376*1cde54c5SRoger Shimizu regulator-name = "vreg_l16b_1p1"; 377*1cde54c5SRoger Shimizu regulator-min-microvolt = <1100000>; 378*1cde54c5SRoger Shimizu regulator-max-microvolt = <1300000>; 379*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 380*1cde54c5SRoger Shimizu }; 381*1cde54c5SRoger Shimizu 382*1cde54c5SRoger Shimizu vreg_l17b_1p7: ldo17 { 383*1cde54c5SRoger Shimizu regulator-name = "vreg_l17b_1p7"; 384*1cde54c5SRoger Shimizu regulator-min-microvolt = <1700000>; 385*1cde54c5SRoger Shimizu regulator-max-microvolt = <1900000>; 386*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 387*1cde54c5SRoger Shimizu }; 388*1cde54c5SRoger Shimizu 389*1cde54c5SRoger Shimizu vreg_l18b_1p8: ldo18 { 390*1cde54c5SRoger Shimizu regulator-name = "vreg_l18b_1p8"; 391*1cde54c5SRoger Shimizu regulator-min-microvolt = <1800000>; 392*1cde54c5SRoger Shimizu regulator-max-microvolt = <2000000>; 393*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 394*1cde54c5SRoger Shimizu }; 395*1cde54c5SRoger Shimizu 396*1cde54c5SRoger Shimizu vreg_l19b_1p8: ldo19 { 397*1cde54c5SRoger Shimizu regulator-name = "vreg_l19b_1p8"; 398*1cde54c5SRoger Shimizu regulator-min-microvolt = <1800000>; 399*1cde54c5SRoger Shimizu regulator-max-microvolt = <2000000>; 400*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 401*1cde54c5SRoger Shimizu }; 402*1cde54c5SRoger Shimizu }; 403*1cde54c5SRoger Shimizu 404*1cde54c5SRoger Shimizu regulators-1 { 405*1cde54c5SRoger Shimizu compatible = "qcom,pm8350c-rpmh-regulators"; 406*1cde54c5SRoger Shimizu qcom,pmic-id = "c"; 407*1cde54c5SRoger Shimizu 408*1cde54c5SRoger Shimizu vdd-s1-supply = <&vph_pwr>; 409*1cde54c5SRoger Shimizu vdd-s2-supply = <&vph_pwr>; 410*1cde54c5SRoger Shimizu vdd-s3-supply = <&vph_pwr>; 411*1cde54c5SRoger Shimizu vdd-s4-supply = <&vph_pwr>; 412*1cde54c5SRoger Shimizu vdd-s5-supply = <&vph_pwr>; 413*1cde54c5SRoger Shimizu vdd-s6-supply = <&vph_pwr>; 414*1cde54c5SRoger Shimizu vdd-s7-supply = <&vph_pwr>; 415*1cde54c5SRoger Shimizu vdd-s8-supply = <&vph_pwr>; 416*1cde54c5SRoger Shimizu vdd-s9-supply = <&vph_pwr>; 417*1cde54c5SRoger Shimizu vdd-s10-supply = <&vph_pwr>; 418*1cde54c5SRoger Shimizu vdd-l1-l12-supply = <&vreg_s1b_1p872>; 419*1cde54c5SRoger Shimizu vdd-l2-l8-supply = <&vreg_s1b_1p872>; 420*1cde54c5SRoger Shimizu vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; 421*1cde54c5SRoger Shimizu vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; 422*1cde54c5SRoger Shimizu vdd-l10-supply = <&vreg_s7b_0p972>; 423*1cde54c5SRoger Shimizu vdd-bob-supply = <&vph_pwr>; 424*1cde54c5SRoger Shimizu 425*1cde54c5SRoger Shimizu vreg_s1c_2p19: smps1 { 426*1cde54c5SRoger Shimizu regulator-name = "vreg_s1c_2p19"; 427*1cde54c5SRoger Shimizu regulator-min-microvolt = <2200000>; 428*1cde54c5SRoger Shimizu regulator-max-microvolt = <2208000>; 429*1cde54c5SRoger Shimizu }; 430*1cde54c5SRoger Shimizu 431*1cde54c5SRoger Shimizu vreg_s9c_1p084: smps9 { 432*1cde54c5SRoger Shimizu regulator-name = "vreg_s9c_1p084"; 433*1cde54c5SRoger Shimizu regulator-min-microvolt = <1010000>; 434*1cde54c5SRoger Shimizu regulator-max-microvolt = <1170000>; 435*1cde54c5SRoger Shimizu }; 436*1cde54c5SRoger Shimizu 437*1cde54c5SRoger Shimizu vreg_l1c_1p8: ldo1 { 438*1cde54c5SRoger Shimizu regulator-name = "vreg_l1c_1p8"; 439*1cde54c5SRoger Shimizu regulator-min-microvolt = <1800000>; 440*1cde54c5SRoger Shimizu regulator-max-microvolt = <1980000>; 441*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 442*1cde54c5SRoger Shimizu }; 443*1cde54c5SRoger Shimizu 444*1cde54c5SRoger Shimizu vreg_l2c_1p62: ldo2 { 445*1cde54c5SRoger Shimizu regulator-name = "vreg_l2c_1p62"; 446*1cde54c5SRoger Shimizu regulator-min-microvolt = <1620000>; 447*1cde54c5SRoger Shimizu regulator-max-microvolt = <1980000>; 448*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 449*1cde54c5SRoger Shimizu }; 450*1cde54c5SRoger Shimizu 451*1cde54c5SRoger Shimizu vreg_l3c_2p8: ldo3 { 452*1cde54c5SRoger Shimizu regulator-name = "vreg_l3c_2p8"; 453*1cde54c5SRoger Shimizu regulator-min-microvolt = <2800000>; 454*1cde54c5SRoger Shimizu regulator-max-microvolt = <3540000>; 455*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 456*1cde54c5SRoger Shimizu }; 457*1cde54c5SRoger Shimizu 458*1cde54c5SRoger Shimizu vreg_l4c_1p62: ldo4 { 459*1cde54c5SRoger Shimizu regulator-name = "vreg_l4c_1p62"; 460*1cde54c5SRoger Shimizu regulator-min-microvolt = <1620000>; 461*1cde54c5SRoger Shimizu regulator-max-microvolt = <3300000>; 462*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 463*1cde54c5SRoger Shimizu }; 464*1cde54c5SRoger Shimizu 465*1cde54c5SRoger Shimizu vreg_l5c_1p62: ldo5 { 466*1cde54c5SRoger Shimizu regulator-name = "vreg_l5c_1p62"; 467*1cde54c5SRoger Shimizu regulator-min-microvolt = <1620000>; 468*1cde54c5SRoger Shimizu regulator-max-microvolt = <3300000>; 469*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 470*1cde54c5SRoger Shimizu }; 471*1cde54c5SRoger Shimizu 472*1cde54c5SRoger Shimizu vreg_l6c_2p96: ldo6 { 473*1cde54c5SRoger Shimizu regulator-name = "vreg_l6c_2p96"; 474*1cde54c5SRoger Shimizu regulator-min-microvolt = <1650000>; 475*1cde54c5SRoger Shimizu regulator-max-microvolt = <2960000>; 476*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 477*1cde54c5SRoger Shimizu }; 478*1cde54c5SRoger Shimizu 479*1cde54c5SRoger Shimizu vreg_l7c_3p0: ldo7 { 480*1cde54c5SRoger Shimizu regulator-name = "vreg_l7c_3p0"; 481*1cde54c5SRoger Shimizu regulator-min-microvolt = <3000000>; 482*1cde54c5SRoger Shimizu regulator-max-microvolt = <3544000>; 483*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 484*1cde54c5SRoger Shimizu }; 485*1cde54c5SRoger Shimizu 486*1cde54c5SRoger Shimizu vreg_l8c_1p62: ldo8 { 487*1cde54c5SRoger Shimizu regulator-name = "vreg_l8c_1p62"; 488*1cde54c5SRoger Shimizu regulator-min-microvolt = <1800000>; 489*1cde54c5SRoger Shimizu regulator-max-microvolt = <2000000>; 490*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 491*1cde54c5SRoger Shimizu }; 492*1cde54c5SRoger Shimizu 493*1cde54c5SRoger Shimizu vreg_l9c_2p96: ldo9 { 494*1cde54c5SRoger Shimizu regulator-name = "vreg_l9c_2p96"; 495*1cde54c5SRoger Shimizu regulator-min-microvolt = <2700000>; 496*1cde54c5SRoger Shimizu regulator-max-microvolt = <3544000>; 497*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 498*1cde54c5SRoger Shimizu }; 499*1cde54c5SRoger Shimizu 500*1cde54c5SRoger Shimizu vreg_l10c_0p88: ldo10 { 501*1cde54c5SRoger Shimizu regulator-name = "vreg_l10c_0p88"; 502*1cde54c5SRoger Shimizu regulator-min-microvolt = <720000>; 503*1cde54c5SRoger Shimizu regulator-max-microvolt = <1050000>; 504*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 505*1cde54c5SRoger Shimizu }; 506*1cde54c5SRoger Shimizu 507*1cde54c5SRoger Shimizu vreg_l11c_2p8: ldo11 { 508*1cde54c5SRoger Shimizu regulator-name = "vreg_l11c_2p8"; 509*1cde54c5SRoger Shimizu regulator-min-microvolt = <1650000>; 510*1cde54c5SRoger Shimizu regulator-max-microvolt = <3544000>; 511*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 512*1cde54c5SRoger Shimizu }; 513*1cde54c5SRoger Shimizu 514*1cde54c5SRoger Shimizu vreg_l12c_1p65: ldo12 { 515*1cde54c5SRoger Shimizu regulator-name = "vreg_l12c_1p65"; 516*1cde54c5SRoger Shimizu regulator-min-microvolt = <1620000>; 517*1cde54c5SRoger Shimizu regulator-max-microvolt = <2000000>; 518*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 519*1cde54c5SRoger Shimizu }; 520*1cde54c5SRoger Shimizu 521*1cde54c5SRoger Shimizu vreg_l13c_2p7: ldo13 { 522*1cde54c5SRoger Shimizu regulator-name = "vreg_l13c_2p7"; 523*1cde54c5SRoger Shimizu regulator-min-microvolt = <2700000>; 524*1cde54c5SRoger Shimizu regulator-max-microvolt = <3544000>; 525*1cde54c5SRoger Shimizu regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 526*1cde54c5SRoger Shimizu }; 527*1cde54c5SRoger Shimizu 528*1cde54c5SRoger Shimizu vreg_bob_3p296: bob { 529*1cde54c5SRoger Shimizu regulator-name = "vreg_bob_3p296"; 530*1cde54c5SRoger Shimizu regulator-min-microvolt = <3008000>; 531*1cde54c5SRoger Shimizu regulator-max-microvolt = <3960000>; 532*1cde54c5SRoger Shimizu }; 533*1cde54c5SRoger Shimizu }; 534*1cde54c5SRoger Shimizu}; 535*1cde54c5SRoger Shimizu 536*1cde54c5SRoger Shimizu&gcc { 537*1cde54c5SRoger Shimizu protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, 538*1cde54c5SRoger Shimizu <GCC_MSS_CFG_AHB_CLK>, 539*1cde54c5SRoger Shimizu <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, 540*1cde54c5SRoger Shimizu <GCC_MSS_OFFLINE_AXI_CLK>, 541*1cde54c5SRoger Shimizu <GCC_MSS_Q6SS_BOOT_CLK_SRC>, 542*1cde54c5SRoger Shimizu <GCC_MSS_Q6_MEMNOC_AXI_CLK>, 543*1cde54c5SRoger Shimizu <GCC_MSS_SNOC_AXI_CLK>, 544*1cde54c5SRoger Shimizu <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 545*1cde54c5SRoger Shimizu <GCC_QSPI_CORE_CLK>, 546*1cde54c5SRoger Shimizu <GCC_QSPI_CORE_CLK_SRC>, 547*1cde54c5SRoger Shimizu <GCC_SEC_CTRL_CLK_SRC>, 548*1cde54c5SRoger Shimizu <GCC_WPSS_AHB_BDG_MST_CLK>, 549*1cde54c5SRoger Shimizu <GCC_WPSS_AHB_CLK>, 550*1cde54c5SRoger Shimizu <GCC_WPSS_RSCP_CLK>; 551*1cde54c5SRoger Shimizu}; 552*1cde54c5SRoger Shimizu 553*1cde54c5SRoger Shimizu&gpi_dma0 { 554*1cde54c5SRoger Shimizu status = "okay"; 555*1cde54c5SRoger Shimizu}; 556*1cde54c5SRoger Shimizu 557*1cde54c5SRoger Shimizu&gpi_dma1 { 558*1cde54c5SRoger Shimizu status = "okay"; 559*1cde54c5SRoger Shimizu}; 560*1cde54c5SRoger Shimizu 561*1cde54c5SRoger Shimizu&gpu { 562*1cde54c5SRoger Shimizu status = "okay"; 563*1cde54c5SRoger Shimizu}; 564*1cde54c5SRoger Shimizu 565*1cde54c5SRoger Shimizu&gpu_zap_shader { 566*1cde54c5SRoger Shimizu firmware-name = "qcom/qcs6490/a660_zap.mbn"; 567*1cde54c5SRoger Shimizu}; 568*1cde54c5SRoger Shimizu 569*1cde54c5SRoger Shimizu&i2c0 { 570*1cde54c5SRoger Shimizu clock-frequency = <400000>; 571*1cde54c5SRoger Shimizu 572*1cde54c5SRoger Shimizu status = "okay"; 573*1cde54c5SRoger Shimizu 574*1cde54c5SRoger Shimizu lt9611_codec: hdmi-bridge@2b { 575*1cde54c5SRoger Shimizu compatible = "lontium,lt9611uxc"; 576*1cde54c5SRoger Shimizu reg = <0x2b>; 577*1cde54c5SRoger Shimizu 578*1cde54c5SRoger Shimizu interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>; 579*1cde54c5SRoger Shimizu reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; 580*1cde54c5SRoger Shimizu 581*1cde54c5SRoger Shimizu vdd-supply = <<9611_1v2>; 582*1cde54c5SRoger Shimizu vcc-supply = <&vreg_l11c_2p8>; 583*1cde54c5SRoger Shimizu 584*1cde54c5SRoger Shimizu pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; 585*1cde54c5SRoger Shimizu pinctrl-names = "default"; 586*1cde54c5SRoger Shimizu 587*1cde54c5SRoger Shimizu ports { 588*1cde54c5SRoger Shimizu #address-cells = <1>; 589*1cde54c5SRoger Shimizu #size-cells = <0>; 590*1cde54c5SRoger Shimizu 591*1cde54c5SRoger Shimizu port@0 { 592*1cde54c5SRoger Shimizu reg = <0>; 593*1cde54c5SRoger Shimizu 594*1cde54c5SRoger Shimizu lt9611_a: endpoint { 595*1cde54c5SRoger Shimizu remote-endpoint = <&mdss_dsi0_out>; 596*1cde54c5SRoger Shimizu }; 597*1cde54c5SRoger Shimizu }; 598*1cde54c5SRoger Shimizu 599*1cde54c5SRoger Shimizu port@2 { 600*1cde54c5SRoger Shimizu reg = <2>; 601*1cde54c5SRoger Shimizu 602*1cde54c5SRoger Shimizu lt9611_out: endpoint { 603*1cde54c5SRoger Shimizu remote-endpoint = <&hdmi_con>; 604*1cde54c5SRoger Shimizu }; 605*1cde54c5SRoger Shimizu }; 606*1cde54c5SRoger Shimizu }; 607*1cde54c5SRoger Shimizu }; 608*1cde54c5SRoger Shimizu}; 609*1cde54c5SRoger Shimizu 610*1cde54c5SRoger Shimizu&i2c1 { 611*1cde54c5SRoger Shimizu clock-frequency = <100000>; 612*1cde54c5SRoger Shimizu 613*1cde54c5SRoger Shimizu status = "okay"; 614*1cde54c5SRoger Shimizu 615*1cde54c5SRoger Shimizu typec-mux@1c { 616*1cde54c5SRoger Shimizu compatible = "onnn,nb7vpq904m"; 617*1cde54c5SRoger Shimizu reg = <0x1c>; 618*1cde54c5SRoger Shimizu 619*1cde54c5SRoger Shimizu vcc-supply = <&vreg_l18b_1p8>; 620*1cde54c5SRoger Shimizu 621*1cde54c5SRoger Shimizu retimer-switch; 622*1cde54c5SRoger Shimizu orientation-switch; 623*1cde54c5SRoger Shimizu 624*1cde54c5SRoger Shimizu ports { 625*1cde54c5SRoger Shimizu #address-cells = <1>; 626*1cde54c5SRoger Shimizu #size-cells = <0>; 627*1cde54c5SRoger Shimizu 628*1cde54c5SRoger Shimizu port@0 { 629*1cde54c5SRoger Shimizu reg = <0>; 630*1cde54c5SRoger Shimizu 631*1cde54c5SRoger Shimizu redriver_usb_con_ss: endpoint { 632*1cde54c5SRoger Shimizu remote-endpoint = <&pmic_glink_ss_in>; 633*1cde54c5SRoger Shimizu }; 634*1cde54c5SRoger Shimizu }; 635*1cde54c5SRoger Shimizu 636*1cde54c5SRoger Shimizu port@1 { 637*1cde54c5SRoger Shimizu reg = <1>; 638*1cde54c5SRoger Shimizu 639*1cde54c5SRoger Shimizu redriver_phy_con_ss: endpoint { 640*1cde54c5SRoger Shimizu remote-endpoint = <&usb_dp_qmpphy_out>; 641*1cde54c5SRoger Shimizu data-lanes = <0 1 2 3>; 642*1cde54c5SRoger Shimizu }; 643*1cde54c5SRoger Shimizu }; 644*1cde54c5SRoger Shimizu 645*1cde54c5SRoger Shimizu port@2 { 646*1cde54c5SRoger Shimizu reg = <2>; 647*1cde54c5SRoger Shimizu 648*1cde54c5SRoger Shimizu redriver_usb_con_sbu: endpoint { 649*1cde54c5SRoger Shimizu remote-endpoint = <&pmic_glink_sbu_in>; 650*1cde54c5SRoger Shimizu }; 651*1cde54c5SRoger Shimizu }; 652*1cde54c5SRoger Shimizu }; 653*1cde54c5SRoger Shimizu }; 654*1cde54c5SRoger Shimizu}; 655*1cde54c5SRoger Shimizu 656*1cde54c5SRoger Shimizu&mdss { 657*1cde54c5SRoger Shimizu status = "okay"; 658*1cde54c5SRoger Shimizu}; 659*1cde54c5SRoger Shimizu 660*1cde54c5SRoger Shimizu&mdss_dp { 661*1cde54c5SRoger Shimizu status = "okay"; 662*1cde54c5SRoger Shimizu}; 663*1cde54c5SRoger Shimizu 664*1cde54c5SRoger Shimizu&mdss_dp_out { 665*1cde54c5SRoger Shimizu data-lanes = <0 1>; 666*1cde54c5SRoger Shimizu link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; 667*1cde54c5SRoger Shimizu}; 668*1cde54c5SRoger Shimizu 669*1cde54c5SRoger Shimizu&mdss_dsi { 670*1cde54c5SRoger Shimizu vdda-supply = <&vreg_l6b_1p2>; 671*1cde54c5SRoger Shimizu 672*1cde54c5SRoger Shimizu status = "okay"; 673*1cde54c5SRoger Shimizu}; 674*1cde54c5SRoger Shimizu 675*1cde54c5SRoger Shimizu&mdss_dsi0_out { 676*1cde54c5SRoger Shimizu remote-endpoint = <<9611_a>; 677*1cde54c5SRoger Shimizu data-lanes = <0 1 2 3>; 678*1cde54c5SRoger Shimizu}; 679*1cde54c5SRoger Shimizu 680*1cde54c5SRoger Shimizu&mdss_dsi_phy { 681*1cde54c5SRoger Shimizu vdds-supply = <&vreg_l10c_0p88>; 682*1cde54c5SRoger Shimizu 683*1cde54c5SRoger Shimizu status = "okay"; 684*1cde54c5SRoger Shimizu}; 685*1cde54c5SRoger Shimizu 686*1cde54c5SRoger Shimizu&pcie0 { 687*1cde54c5SRoger Shimizu perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; 688*1cde54c5SRoger Shimizu wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; 689*1cde54c5SRoger Shimizu 690*1cde54c5SRoger Shimizu pinctrl-0 = <&pcie0_clkreq_n>, 691*1cde54c5SRoger Shimizu <&pcie0_reset_n>, 692*1cde54c5SRoger Shimizu <&pcie0_wake_n>; 693*1cde54c5SRoger Shimizu pinctrl-names = "default"; 694*1cde54c5SRoger Shimizu 695*1cde54c5SRoger Shimizu status = "okay"; 696*1cde54c5SRoger Shimizu}; 697*1cde54c5SRoger Shimizu 698*1cde54c5SRoger Shimizu&pcie0_phy { 699*1cde54c5SRoger Shimizu vdda-phy-supply = <&vreg_l10c_0p88>; 700*1cde54c5SRoger Shimizu vdda-pll-supply = <&vreg_l6b_1p2>; 701*1cde54c5SRoger Shimizu 702*1cde54c5SRoger Shimizu status = "okay"; 703*1cde54c5SRoger Shimizu}; 704*1cde54c5SRoger Shimizu 705*1cde54c5SRoger Shimizu&pcie1 { 706*1cde54c5SRoger Shimizu perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; 707*1cde54c5SRoger Shimizu wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; 708*1cde54c5SRoger Shimizu 709*1cde54c5SRoger Shimizu pinctrl-0 = <&pcie1_clkreq_n>, 710*1cde54c5SRoger Shimizu <&pcie1_reset_n>, 711*1cde54c5SRoger Shimizu <&pcie1_wake_n>; 712*1cde54c5SRoger Shimizu pinctrl-names = "default"; 713*1cde54c5SRoger Shimizu 714*1cde54c5SRoger Shimizu iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 715*1cde54c5SRoger Shimizu <0x100 &apps_smmu 0x1c81 0x1>, 716*1cde54c5SRoger Shimizu <0x208 &apps_smmu 0x1c84 0x1>, 717*1cde54c5SRoger Shimizu <0x210 &apps_smmu 0x1c85 0x1>, 718*1cde54c5SRoger Shimizu <0x218 &apps_smmu 0x1c86 0x1>, 719*1cde54c5SRoger Shimizu <0x300 &apps_smmu 0x1c87 0x1>, 720*1cde54c5SRoger Shimizu <0x400 &apps_smmu 0x1c88 0x1>, 721*1cde54c5SRoger Shimizu <0x500 &apps_smmu 0x1c89 0x1>, 722*1cde54c5SRoger Shimizu <0x501 &apps_smmu 0x1c90 0x1>; 723*1cde54c5SRoger Shimizu 724*1cde54c5SRoger Shimizu status = "okay"; 725*1cde54c5SRoger Shimizu}; 726*1cde54c5SRoger Shimizu 727*1cde54c5SRoger Shimizu&pcie1_phy { 728*1cde54c5SRoger Shimizu vdda-phy-supply = <&vreg_l10c_0p88>; 729*1cde54c5SRoger Shimizu vdda-pll-supply = <&vreg_l6b_1p2>; 730*1cde54c5SRoger Shimizu 731*1cde54c5SRoger Shimizu status = "okay"; 732*1cde54c5SRoger Shimizu}; 733*1cde54c5SRoger Shimizu 734*1cde54c5SRoger Shimizu&pcie1_port0 { 735*1cde54c5SRoger Shimizu pcie@0,0 { 736*1cde54c5SRoger Shimizu compatible = "pci1179,0623"; 737*1cde54c5SRoger Shimizu reg = <0x10000 0x0 0x0 0x0 0x0>; 738*1cde54c5SRoger Shimizu #address-cells = <3>; 739*1cde54c5SRoger Shimizu #size-cells = <2>; 740*1cde54c5SRoger Shimizu 741*1cde54c5SRoger Shimizu device_type = "pci"; 742*1cde54c5SRoger Shimizu ranges; 743*1cde54c5SRoger Shimizu bus-range = <0x2 0xff>; 744*1cde54c5SRoger Shimizu 745*1cde54c5SRoger Shimizu vddc-supply = <&vdd_ntn_0p9>; 746*1cde54c5SRoger Shimizu vdd18-supply = <&vdd_ntn_1p8>; 747*1cde54c5SRoger Shimizu vdd09-supply = <&vdd_ntn_0p9>; 748*1cde54c5SRoger Shimizu vddio1-supply = <&vdd_ntn_1p8>; 749*1cde54c5SRoger Shimizu vddio2-supply = <&vdd_ntn_1p8>; 750*1cde54c5SRoger Shimizu vddio18-supply = <&vdd_ntn_1p8>; 751*1cde54c5SRoger Shimizu 752*1cde54c5SRoger Shimizu i2c-parent = <&i2c0 0x77>; 753*1cde54c5SRoger Shimizu 754*1cde54c5SRoger Shimizu resx-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; 755*1cde54c5SRoger Shimizu 756*1cde54c5SRoger Shimizu pinctrl-0 = <&tc9563_resx_n>; 757*1cde54c5SRoger Shimizu pinctrl-names = "default"; 758*1cde54c5SRoger Shimizu 759*1cde54c5SRoger Shimizu pcie@1,0 { 760*1cde54c5SRoger Shimizu reg = <0x20800 0x0 0x0 0x0 0x0>; 761*1cde54c5SRoger Shimizu #address-cells = <3>; 762*1cde54c5SRoger Shimizu #size-cells = <2>; 763*1cde54c5SRoger Shimizu 764*1cde54c5SRoger Shimizu device_type = "pci"; 765*1cde54c5SRoger Shimizu ranges; 766*1cde54c5SRoger Shimizu bus-range = <0x3 0xff>; 767*1cde54c5SRoger Shimizu }; 768*1cde54c5SRoger Shimizu 769*1cde54c5SRoger Shimizu pcie@2,0 { 770*1cde54c5SRoger Shimizu reg = <0x21000 0x0 0x0 0x0 0x0>; 771*1cde54c5SRoger Shimizu #address-cells = <3>; 772*1cde54c5SRoger Shimizu #size-cells = <2>; 773*1cde54c5SRoger Shimizu 774*1cde54c5SRoger Shimizu device_type = "pci"; 775*1cde54c5SRoger Shimizu ranges; 776*1cde54c5SRoger Shimizu bus-range = <0x4 0xff>; 777*1cde54c5SRoger Shimizu }; 778*1cde54c5SRoger Shimizu 779*1cde54c5SRoger Shimizu pcie@3,0 { 780*1cde54c5SRoger Shimizu reg = <0x21800 0x0 0x0 0x0 0x0>; 781*1cde54c5SRoger Shimizu #address-cells = <3>; 782*1cde54c5SRoger Shimizu #size-cells = <2>; 783*1cde54c5SRoger Shimizu device_type = "pci"; 784*1cde54c5SRoger Shimizu ranges; 785*1cde54c5SRoger Shimizu bus-range = <0x5 0xff>; 786*1cde54c5SRoger Shimizu 787*1cde54c5SRoger Shimizu pci@0,0 { 788*1cde54c5SRoger Shimizu reg = <0x50000 0x0 0x0 0x0 0x0>; 789*1cde54c5SRoger Shimizu #address-cells = <3>; 790*1cde54c5SRoger Shimizu #size-cells = <2>; 791*1cde54c5SRoger Shimizu device_type = "pci"; 792*1cde54c5SRoger Shimizu ranges; 793*1cde54c5SRoger Shimizu }; 794*1cde54c5SRoger Shimizu 795*1cde54c5SRoger Shimizu pci@0,1 { 796*1cde54c5SRoger Shimizu reg = <0x50100 0x0 0x0 0x0 0x0>; 797*1cde54c5SRoger Shimizu #address-cells = <3>; 798*1cde54c5SRoger Shimizu #size-cells = <2>; 799*1cde54c5SRoger Shimizu device_type = "pci"; 800*1cde54c5SRoger Shimizu ranges; 801*1cde54c5SRoger Shimizu }; 802*1cde54c5SRoger Shimizu }; 803*1cde54c5SRoger Shimizu }; 804*1cde54c5SRoger Shimizu}; 805*1cde54c5SRoger Shimizu 806*1cde54c5SRoger Shimizu&pm7250b_gpios { 807*1cde54c5SRoger Shimizu lt9611_rst_pin: lt9611-rst-state { 808*1cde54c5SRoger Shimizu pins = "gpio2"; 809*1cde54c5SRoger Shimizu function = "normal"; 810*1cde54c5SRoger Shimizu 811*1cde54c5SRoger Shimizu output-high; 812*1cde54c5SRoger Shimizu input-disable; 813*1cde54c5SRoger Shimizu power-source = <0>; 814*1cde54c5SRoger Shimizu }; 815*1cde54c5SRoger Shimizu}; 816*1cde54c5SRoger Shimizu 817*1cde54c5SRoger Shimizu&pm7325_temp_alarm { 818*1cde54c5SRoger Shimizu io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; 819*1cde54c5SRoger Shimizu io-channel-names = "thermal"; 820*1cde54c5SRoger Shimizu}; 821*1cde54c5SRoger Shimizu 822*1cde54c5SRoger Shimizu&pmk8350_adc_tm { 823*1cde54c5SRoger Shimizu status = "okay"; 824*1cde54c5SRoger Shimizu 825*1cde54c5SRoger Shimizu xo-therm@0 { 826*1cde54c5SRoger Shimizu reg = <0>; 827*1cde54c5SRoger Shimizu io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; 828*1cde54c5SRoger Shimizu qcom,ratiometric; 829*1cde54c5SRoger Shimizu qcom,hw-settle-time-us = <200>; 830*1cde54c5SRoger Shimizu }; 831*1cde54c5SRoger Shimizu 832*1cde54c5SRoger Shimizu quiet-therm@1 { 833*1cde54c5SRoger Shimizu reg = <1>; 834*1cde54c5SRoger Shimizu io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; 835*1cde54c5SRoger Shimizu qcom,ratiometric; 836*1cde54c5SRoger Shimizu qcom,hw-settle-time-us = <200>; 837*1cde54c5SRoger Shimizu }; 838*1cde54c5SRoger Shimizu 839*1cde54c5SRoger Shimizu sdm-skin-therm@3 { 840*1cde54c5SRoger Shimizu reg = <3>; 841*1cde54c5SRoger Shimizu io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; 842*1cde54c5SRoger Shimizu qcom,ratiometric; 843*1cde54c5SRoger Shimizu qcom,hw-settle-time-us = <200>; 844*1cde54c5SRoger Shimizu }; 845*1cde54c5SRoger Shimizu}; 846*1cde54c5SRoger Shimizu 847*1cde54c5SRoger Shimizu&pm8350c_gpios { 848*1cde54c5SRoger Shimizu ntn_0p9_en: ntn-0p9-en-state { 849*1cde54c5SRoger Shimizu pins = "gpio2"; 850*1cde54c5SRoger Shimizu function = "normal"; 851*1cde54c5SRoger Shimizu 852*1cde54c5SRoger Shimizu bias-disable; 853*1cde54c5SRoger Shimizu input-disable; 854*1cde54c5SRoger Shimizu output-enable; 855*1cde54c5SRoger Shimizu power-source = <0>; 856*1cde54c5SRoger Shimizu }; 857*1cde54c5SRoger Shimizu 858*1cde54c5SRoger Shimizu ntn_1p8_en: ntn-1p8-en-state { 859*1cde54c5SRoger Shimizu pins = "gpio3"; 860*1cde54c5SRoger Shimizu function = "normal"; 861*1cde54c5SRoger Shimizu 862*1cde54c5SRoger Shimizu bias-disable; 863*1cde54c5SRoger Shimizu input-disable; 864*1cde54c5SRoger Shimizu output-enable; 865*1cde54c5SRoger Shimizu power-source = <0>; 866*1cde54c5SRoger Shimizu }; 867*1cde54c5SRoger Shimizu 868*1cde54c5SRoger Shimizu tc9563_resx_n: tc9563-resx-state { 869*1cde54c5SRoger Shimizu pins = "gpio1"; 870*1cde54c5SRoger Shimizu function = "normal"; 871*1cde54c5SRoger Shimizu 872*1cde54c5SRoger Shimizu bias-disable; 873*1cde54c5SRoger Shimizu input-disable; 874*1cde54c5SRoger Shimizu output-enable; 875*1cde54c5SRoger Shimizu power-source = <0>; 876*1cde54c5SRoger Shimizu }; 877*1cde54c5SRoger Shimizu}; 878*1cde54c5SRoger Shimizu 879*1cde54c5SRoger Shimizu&pm8350c_pwm { 880*1cde54c5SRoger Shimizu nvmem = <&pmk8350_sdam_21>, 881*1cde54c5SRoger Shimizu <&pmk8350_sdam_22>; 882*1cde54c5SRoger Shimizu nvmem-names = "lpg_chan_sdam", 883*1cde54c5SRoger Shimizu "lut_sdam"; 884*1cde54c5SRoger Shimizu 885*1cde54c5SRoger Shimizu #address-cells = <1>; 886*1cde54c5SRoger Shimizu #size-cells = <0>; 887*1cde54c5SRoger Shimizu 888*1cde54c5SRoger Shimizu status = "okay"; 889*1cde54c5SRoger Shimizu}; 890*1cde54c5SRoger Shimizu 891*1cde54c5SRoger Shimizu&pmk8350_rtc { 892*1cde54c5SRoger Shimizu status = "okay"; 893*1cde54c5SRoger Shimizu}; 894*1cde54c5SRoger Shimizu 895*1cde54c5SRoger Shimizu&pmk8350_vadc { 896*1cde54c5SRoger Shimizu channel@3 { 897*1cde54c5SRoger Shimizu reg = <PMK8350_ADC7_DIE_TEMP>; 898*1cde54c5SRoger Shimizu label = "pmk7325_die_temp"; 899*1cde54c5SRoger Shimizu qcom,pre-scaling = <1 1>; 900*1cde54c5SRoger Shimizu }; 901*1cde54c5SRoger Shimizu 902*1cde54c5SRoger Shimizu channel@44 { 903*1cde54c5SRoger Shimizu reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; 904*1cde54c5SRoger Shimizu label = "xo_therm"; 905*1cde54c5SRoger Shimizu qcom,hw-settle-time = <200>; 906*1cde54c5SRoger Shimizu qcom,pre-scaling = <1 1>; 907*1cde54c5SRoger Shimizu qcom,ratiometric; 908*1cde54c5SRoger Shimizu }; 909*1cde54c5SRoger Shimizu 910*1cde54c5SRoger Shimizu channel@103 { 911*1cde54c5SRoger Shimizu reg = <PM7325_ADC7_DIE_TEMP>; 912*1cde54c5SRoger Shimizu label = "pm7325_die_temp"; 913*1cde54c5SRoger Shimizu qcom,pre-scaling = <1 1>; 914*1cde54c5SRoger Shimizu }; 915*1cde54c5SRoger Shimizu 916*1cde54c5SRoger Shimizu channel@144 { 917*1cde54c5SRoger Shimizu reg = <PM7325_ADC7_AMUX_THM1_100K_PU>; 918*1cde54c5SRoger Shimizu qcom,ratiometric; 919*1cde54c5SRoger Shimizu qcom,hw-settle-time = <200>; 920*1cde54c5SRoger Shimizu qcom,pre-scaling = <1 1>; 921*1cde54c5SRoger Shimizu label = "pm7325_quiet_therm"; 922*1cde54c5SRoger Shimizu }; 923*1cde54c5SRoger Shimizu 924*1cde54c5SRoger Shimizu channel@146 { 925*1cde54c5SRoger Shimizu reg = <PM7325_ADC7_AMUX_THM3_100K_PU>; 926*1cde54c5SRoger Shimizu qcom,ratiometric; 927*1cde54c5SRoger Shimizu qcom,hw-settle-time = <200>; 928*1cde54c5SRoger Shimizu qcom,pre-scaling = <1 1>; 929*1cde54c5SRoger Shimizu label = "pm7325_sdm_skin_therm"; 930*1cde54c5SRoger Shimizu }; 931*1cde54c5SRoger Shimizu}; 932*1cde54c5SRoger Shimizu 933*1cde54c5SRoger Shimizu&pon_pwrkey { 934*1cde54c5SRoger Shimizu status = "okay"; 935*1cde54c5SRoger Shimizu}; 936*1cde54c5SRoger Shimizu 937*1cde54c5SRoger Shimizu&pon_resin { 938*1cde54c5SRoger Shimizu linux,code = <KEY_VOLUMEDOWN>; 939*1cde54c5SRoger Shimizu 940*1cde54c5SRoger Shimizu status = "okay"; 941*1cde54c5SRoger Shimizu}; 942*1cde54c5SRoger Shimizu 943*1cde54c5SRoger Shimizu&qupv3_id_0 { 944*1cde54c5SRoger Shimizu firmware-name = "qcom/qcs6490/qupv3fw.elf"; 945*1cde54c5SRoger Shimizu 946*1cde54c5SRoger Shimizu status = "okay"; 947*1cde54c5SRoger Shimizu}; 948*1cde54c5SRoger Shimizu 949*1cde54c5SRoger Shimizu&qupv3_id_1 { 950*1cde54c5SRoger Shimizu firmware-name = "qcom/qcs6490/qupv3fw.elf"; 951*1cde54c5SRoger Shimizu 952*1cde54c5SRoger Shimizu status = "okay"; 953*1cde54c5SRoger Shimizu}; 954*1cde54c5SRoger Shimizu 955*1cde54c5SRoger Shimizu&remoteproc_adsp { 956*1cde54c5SRoger Shimizu firmware-name = "qcom/qcs6490/adsp.mbn"; 957*1cde54c5SRoger Shimizu 958*1cde54c5SRoger Shimizu status = "okay"; 959*1cde54c5SRoger Shimizu}; 960*1cde54c5SRoger Shimizu 961*1cde54c5SRoger Shimizu&remoteproc_cdsp { 962*1cde54c5SRoger Shimizu firmware-name = "qcom/qcs6490/cdsp.mbn"; 963*1cde54c5SRoger Shimizu 964*1cde54c5SRoger Shimizu status = "okay"; 965*1cde54c5SRoger Shimizu}; 966*1cde54c5SRoger Shimizu 967*1cde54c5SRoger Shimizu&sdc2_clk { 968*1cde54c5SRoger Shimizu bias-disable; 969*1cde54c5SRoger Shimizu drive-strength = <16>; 970*1cde54c5SRoger Shimizu}; 971*1cde54c5SRoger Shimizu 972*1cde54c5SRoger Shimizu&sdc2_cmd { 973*1cde54c5SRoger Shimizu bias-pull-up; 974*1cde54c5SRoger Shimizu drive-strength = <10>; 975*1cde54c5SRoger Shimizu}; 976*1cde54c5SRoger Shimizu 977*1cde54c5SRoger Shimizu&sdc2_data { 978*1cde54c5SRoger Shimizu bias-pull-up; 979*1cde54c5SRoger Shimizu drive-strength = <10>; 980*1cde54c5SRoger Shimizu}; 981*1cde54c5SRoger Shimizu 982*1cde54c5SRoger Shimizu&sdhc_2 { 983*1cde54c5SRoger Shimizu pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; 984*1cde54c5SRoger Shimizu pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; 985*1cde54c5SRoger Shimizu 986*1cde54c5SRoger Shimizu vmmc-supply = <&vreg_l9c_2p96>; 987*1cde54c5SRoger Shimizu vqmmc-supply = <&vreg_l6c_2p96>; 988*1cde54c5SRoger Shimizu 989*1cde54c5SRoger Shimizu cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; 990*1cde54c5SRoger Shimizu 991*1cde54c5SRoger Shimizu status = "okay"; 992*1cde54c5SRoger Shimizu}; 993*1cde54c5SRoger Shimizu 994*1cde54c5SRoger Shimizu&tlmm { 995*1cde54c5SRoger Shimizu gpio-reserved-ranges = <32 2>, /* ADSP */ 996*1cde54c5SRoger Shimizu <48 4>; /* NFC */ 997*1cde54c5SRoger Shimizu 998*1cde54c5SRoger Shimizu lt9611_irq_pin: lt9611-irq-state { 999*1cde54c5SRoger Shimizu pins = "gpio24"; 1000*1cde54c5SRoger Shimizu function = "gpio"; 1001*1cde54c5SRoger Shimizu drive-strength = <2>; 1002*1cde54c5SRoger Shimizu bias-disable; 1003*1cde54c5SRoger Shimizu }; 1004*1cde54c5SRoger Shimizu 1005*1cde54c5SRoger Shimizu pcie0_reset_n: pcie0-reset-n-state { 1006*1cde54c5SRoger Shimizu pins = "gpio87"; 1007*1cde54c5SRoger Shimizu function = "gpio"; 1008*1cde54c5SRoger Shimizu drive-strength = <2>; 1009*1cde54c5SRoger Shimizu bias-disable; 1010*1cde54c5SRoger Shimizu }; 1011*1cde54c5SRoger Shimizu 1012*1cde54c5SRoger Shimizu pcie0_wake_n: pcie0-wake-n-state { 1013*1cde54c5SRoger Shimizu pins = "gpio89"; 1014*1cde54c5SRoger Shimizu function = "gpio"; 1015*1cde54c5SRoger Shimizu drive-strength = <2>; 1016*1cde54c5SRoger Shimizu bias-pull-up; 1017*1cde54c5SRoger Shimizu }; 1018*1cde54c5SRoger Shimizu 1019*1cde54c5SRoger Shimizu pcie1_reset_n: pcie1-reset-n-state { 1020*1cde54c5SRoger Shimizu pins = "gpio2"; 1021*1cde54c5SRoger Shimizu function = "gpio"; 1022*1cde54c5SRoger Shimizu drive-strength = <16>; 1023*1cde54c5SRoger Shimizu output-low; 1024*1cde54c5SRoger Shimizu bias-disable; 1025*1cde54c5SRoger Shimizu }; 1026*1cde54c5SRoger Shimizu 1027*1cde54c5SRoger Shimizu pcie1_wake_n: pcie1-wake-n-state { 1028*1cde54c5SRoger Shimizu pins = "gpio3"; 1029*1cde54c5SRoger Shimizu function = "gpio"; 1030*1cde54c5SRoger Shimizu drive-strength = <2>; 1031*1cde54c5SRoger Shimizu bias-pull-up; 1032*1cde54c5SRoger Shimizu }; 1033*1cde54c5SRoger Shimizu 1034*1cde54c5SRoger Shimizu sd_cd: sd-cd-state { 1035*1cde54c5SRoger Shimizu pins = "gpio91"; 1036*1cde54c5SRoger Shimizu function = "gpio"; 1037*1cde54c5SRoger Shimizu bias-pull-up; 1038*1cde54c5SRoger Shimizu }; 1039*1cde54c5SRoger Shimizu}; 1040*1cde54c5SRoger Shimizu 1041*1cde54c5SRoger Shimizu&uart5 { 1042*1cde54c5SRoger Shimizu status = "okay"; 1043*1cde54c5SRoger Shimizu}; 1044*1cde54c5SRoger Shimizu 1045*1cde54c5SRoger Shimizu&usb_1 { 1046*1cde54c5SRoger Shimizu status = "okay"; 1047*1cde54c5SRoger Shimizu}; 1048*1cde54c5SRoger Shimizu 1049*1cde54c5SRoger Shimizu&usb_1_dwc3_hs { 1050*1cde54c5SRoger Shimizu remote-endpoint = <&pmic_glink_hs_in>; 1051*1cde54c5SRoger Shimizu}; 1052*1cde54c5SRoger Shimizu 1053*1cde54c5SRoger Shimizu&usb_1_hsphy { 1054*1cde54c5SRoger Shimizu vdda-pll-supply = <&vreg_l10c_0p88>; 1055*1cde54c5SRoger Shimizu vdda33-supply = <&vreg_l2b_3p072>; 1056*1cde54c5SRoger Shimizu vdda18-supply = <&vreg_l1c_1p8>; 1057*1cde54c5SRoger Shimizu 1058*1cde54c5SRoger Shimizu status = "okay"; 1059*1cde54c5SRoger Shimizu}; 1060*1cde54c5SRoger Shimizu 1061*1cde54c5SRoger Shimizu&usb_1_qmpphy { 1062*1cde54c5SRoger Shimizu vdda-phy-supply = <&vreg_l6b_1p2>; 1063*1cde54c5SRoger Shimizu vdda-pll-supply = <&vreg_l1b_0p912>; 1064*1cde54c5SRoger Shimizu 1065*1cde54c5SRoger Shimizu status = "okay"; 1066*1cde54c5SRoger Shimizu}; 1067*1cde54c5SRoger Shimizu 1068*1cde54c5SRoger Shimizu&usb_dp_qmpphy_out { 1069*1cde54c5SRoger Shimizu remote-endpoint = <&redriver_phy_con_ss>; 1070*1cde54c5SRoger Shimizu}; 1071*1cde54c5SRoger Shimizu 1072*1cde54c5SRoger Shimizu&ufs_mem_hc { 1073*1cde54c5SRoger Shimizu reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; 1074*1cde54c5SRoger Shimizu vcc-supply = <&vreg_l7b_2p952>; 1075*1cde54c5SRoger Shimizu vcc-max-microamp = <800000>; 1076*1cde54c5SRoger Shimizu vccq-supply = <&vreg_l9b_1p2>; 1077*1cde54c5SRoger Shimizu vccq-max-microamp = <900000>; 1078*1cde54c5SRoger Shimizu vccq2-supply = <&vreg_l9b_1p2>; 1079*1cde54c5SRoger Shimizu vccq2-max-microamp = <900000>; 1080*1cde54c5SRoger Shimizu 1081*1cde54c5SRoger Shimizu status = "okay"; 1082*1cde54c5SRoger Shimizu}; 1083*1cde54c5SRoger Shimizu 1084*1cde54c5SRoger Shimizu&ufs_mem_phy { 1085*1cde54c5SRoger Shimizu vdda-phy-supply = <&vreg_l10c_0p88>; 1086*1cde54c5SRoger Shimizu vdda-pll-supply = <&vreg_l6b_1p2>; 1087*1cde54c5SRoger Shimizu 1088*1cde54c5SRoger Shimizu status = "okay"; 1089*1cde54c5SRoger Shimizu}; 1090*1cde54c5SRoger Shimizu 1091*1cde54c5SRoger Shimizu&venus { 1092*1cde54c5SRoger Shimizu status = "okay"; 1093*1cde54c5SRoger Shimizu}; 1094