xref: /linux/scripts/dtc/include-prefixes/arm64/qcom/lemans-ride-ethernet-aqr115c.dtsi (revision 4f38da1f027ea2c9f01bb71daa7a299c191b6940)

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2023, Linaro Limited
 */

/*
 * Ethernet card for Lemans based Ride r3 boards.
 * It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	aliases {
		ethernet0 = &ethernet0;
		ethernet1 = &ethernet1;
	};
};

&tlmm {
	ethernet0_default: ethernet0-default-state {
		ethernet0_mdc: ethernet0-mdc-pins {
			pins = "gpio8";
			function = "emac0_mdc";
			drive-strength = <16>;
			bias-pull-up;
		};

		ethernet0_mdio: ethernet0-mdio-pins {
			pins = "gpio9";
			function = "emac0_mdio";
			drive-strength = <16>;
			bias-pull-up;
		};
	};
};

&ethernet0 {
	phy-handle = <&hsgmii_phy0>;
	phy-mode = "2500base-x";

	pinctrl-0 = <&ethernet0_default>;
	pinctrl-names = "default";

	snps,mtl-rx-config = <&mtl_rx_setup>;
	snps,mtl-tx-config = <&mtl_tx_setup>;
	snps,ps-speed = <1000>;

	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		hsgmii_phy0: phy@8 {
			compatible = "ethernet-phy-id31c3.1c33";
			reg = <0x8>;
			device_type = "ethernet-phy";
			interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
			reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
			reset-assert-us = <11000>;
			reset-deassert-us = <70000>;
		};

		hsgmii_phy1: phy@0 {
			compatible = "ethernet-phy-id31c3.1c33";
			reg = <0x0>;
			device_type = "ethernet-phy";
			interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
			reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <11000>;
			reset-deassert-us = <70000>;
		};
	};

	mtl_rx_setup: rx-queues-config {
		snps,rx-queues-to-use = <4>;
		snps,rx-sched-sp;

		queue0 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x0>;
			snps,route-up;
			snps,priority = <0x1>;
		};

		queue1 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x1>;
			snps,route-ptp;
		};

		queue2 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x2>;
			snps,route-avcp;
		};

		queue3 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x3>;
			snps,priority = <0xc>;
		};
	};

	mtl_tx_setup: tx-queues-config {
		snps,tx-queues-to-use = <4>;

		queue0 {
			snps,dcb-algorithm;
		};

		queue1 {
			snps,dcb-algorithm;
		};

		queue2 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3e800>;
			snps,low_credit = <0xffc18000>;
		};

		queue3 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3e800>;
			snps,low_credit = <0xffc18000>;
		};
	};
};

&ethernet1 {
	phy-handle = <&hsgmii_phy1>;
	phy-mode = "2500base-x";

	snps,mtl-rx-config = <&mtl_rx_setup1>;
	snps,mtl-tx-config = <&mtl_tx_setup1>;
	snps,ps-speed = <1000>;

	status = "okay";

	mtl_rx_setup1: rx-queues-config {
		snps,rx-queues-to-use = <4>;
		snps,rx-sched-sp;

		queue0 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x0>;
			snps,route-up;
			snps,priority = <0x1>;
		};

		queue1 {
			snps,dcb-algorithm;
			snps,map-to-dma-channel = <0x1>;
			snps,route-ptp;
		};

		queue2 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x2>;
			snps,route-avcp;
		};

		queue3 {
			snps,avb-algorithm;
			snps,map-to-dma-channel = <0x3>;
			snps,priority = <0xc>;
		};
	};

	mtl_tx_setup1: tx-queues-config {
		snps,tx-queues-to-use = <4>;

		queue0 {
			snps,dcb-algorithm;
		};

		queue1 {
			snps,dcb-algorithm;
		};

		queue2 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3e800>;
			snps,low_credit = <0xffc18000>;
		};

		queue3 {
			snps,avb-algorithm;
			snps,send_slope = <0x1000>;
			snps,idle_slope = <0x1000>;
			snps,high_credit = <0x3e800>;
			snps,low_credit = <0xffc18000>;
		};
	};
};