xref: /linux/scripts/dtc/include-prefixes/arm64/qcom/ipq9574.dtsi (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1)

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * IPQ9574 SoC device tree source
 *
 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;
	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
		ref_48mhz_clk: ref-48mhz-clk {
			compatible = "fixed-factor-clock";
			clocks = <&xo_clk>;
			#clock-cells = <0>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		xo_board_clk: xo-board-clk {
			compatible = "fixed-factor-clock";
			clocks = <&ref_48mhz_clk>;
			#clock-cells = <0>;
		};

		xo_clk: xo-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq9574_s1>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq9574_s1>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x2>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq9574_s1>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x3>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq9574_s1>;
			#cooling-cells = <2>;
		};

		l2_0: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-ipq9574", "qcom,scm";
			qcom,dload-mode = <&tcsr 0x6100>;
		};
	};

	memory@40000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0x0 0x40000000 0x0 0x0>;
	};

	cpu_opp_table: opp-table-cpu {
		compatible = "operating-points-v2-kryo-cpu";
		opp-shared;
		nvmem-cells = <&cpu_speed_bin>;

		opp-936000000 {
			opp-hz = /bits/ 64 <936000000>;
			opp-microvolt = <725000>;
			opp-supported-hw = <0xf>;
			clock-latency-ns = <200000>;
		};

		opp-1104000000 {
			opp-hz = /bits/ 64 <1104000000>;
			opp-microvolt = <787500>;
			opp-supported-hw = <0xf>;
			clock-latency-ns = <200000>;
		};

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <862500>;
			opp-supported-hw = <0xf>;
			clock-latency-ns = <200000>;
		};

		opp-1416000000 {
			opp-hz = /bits/ 64 <1416000000>;
			opp-microvolt = <862500>;
			opp-supported-hw = <0x7>;
			clock-latency-ns = <200000>;
		};

		opp-1488000000 {
			opp-hz = /bits/ 64 <1488000000>;
			opp-microvolt = <925000>;
			opp-supported-hw = <0x7>;
			clock-latency-ns = <200000>;
		};

		opp-1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <987500>;
			opp-supported-hw = <0x5>;
			clock-latency-ns = <200000>;
		};

		opp-2208000000 {
			opp-hz = /bits/ 64 <2208000000>;
			opp-microvolt = <1062500>;
			opp-supported-hw = <0x1>;
			clock-latency-ns = <200000>;
		};
	};

	pmu {
		compatible = "arm,cortex-a73-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	rpm: remoteproc {
		compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";

		glink-edge {
			compatible = "qcom,glink-rpm";
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,rpm-msg-ram = <&rpm_msg_ram>;
			mboxes = <&apcs_glb 0>;

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm";
				qcom,glink-channels = "rpm_requests";
			};
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bootloader@4a100000 {
			reg = <0x0 0x4a100000 0x0 0x400000>;
			no-map;
		};

		sbl@4a500000 {
			reg = <0x0 0x4a500000 0x0 0x100000>;
			no-map;
		};

		tz_region: tz@4a600000 {
			reg = <0x0 0x4a600000 0x0 0x400000>;
			no-map;
		};

		smem@4aa00000 {
			compatible = "qcom,smem";
			reg = <0x0 0x4aa00000 0x0 0x100000>;
			hwlocks = <&tcsr_mutex 3>;
			no-map;
		};
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		rpm_msg_ram: sram@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x00060000 0x6000>;
		};

		pcie0_phy: phy@84000 {
			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
			reg = <0x00084000 0x1000>;

			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
				 <&gcc GCC_PCIE0_AHB_CLK>,
				 <&gcc GCC_PCIE0_PIPE_CLK>;
			clock-names = "aux", "cfg_ahb", "pipe";

			assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
			assigned-clock-rates = <20000000>;

			resets = <&gcc GCC_PCIE0_PHY_BCR>,
				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
			reset-names = "phy", "common";

			#clock-cells = <0>;
			clock-output-names = "gcc_pcie0_pipe_clk_src";

			#phy-cells = <0>;
			status = "disabled";
		};

		pcie2_phy: phy@8c000 {
			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
			reg = <0x0008c000 0x2000>;

			clocks = <&gcc GCC_PCIE2_AUX_CLK>,
				 <&gcc GCC_PCIE2_AHB_CLK>,
				 <&gcc GCC_PCIE2_PIPE_CLK>;
			clock-names = "aux", "cfg_ahb", "pipe";

			assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
			assigned-clock-rates = <20000000>;

			resets = <&gcc GCC_PCIE2_PHY_BCR>,
				 <&gcc GCC_PCIE2PHY_PHY_BCR>;
			reset-names = "phy", "common";

			#clock-cells = <0>;
			clock-output-names = "gcc_pcie2_pipe_clk_src";

			#phy-cells = <0>;
			status = "disabled";
		};

		rng: rng@e3000 {
			compatible = "qcom,ipq9574-trng", "qcom,trng";
			reg = <0x000e3000 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		mdio: mdio@90000 {
			compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
			reg = <0x00090000 0x64>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_MDIO_AHB_CLK>;
			clock-names = "gcc_mdio_ahb_clk";
			status = "disabled";
		};

		pcie3_phy: phy@f4000 {
			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
			reg = <0x000f4000 0x2000>;

			clocks = <&gcc GCC_PCIE3_AUX_CLK>,
				 <&gcc GCC_PCIE3_AHB_CLK>,
				 <&gcc GCC_PCIE3_PIPE_CLK>;
			clock-names = "aux", "cfg_ahb", "pipe";

			assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
			assigned-clock-rates = <20000000>;

			resets = <&gcc GCC_PCIE3_PHY_BCR>,
				 <&gcc GCC_PCIE3PHY_PHY_BCR>;
			reset-names = "phy", "common";

			#clock-cells = <0>;
			clock-output-names = "gcc_pcie3_pipe_clk_src";

			#phy-cells = <0>;
			status = "disabled";
		};

		pcie1_phy: phy@fc000 {
			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
			reg = <0x000fc000 0x1000>;

			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
				 <&gcc GCC_PCIE1_AHB_CLK>,
				 <&gcc GCC_PCIE1_PIPE_CLK>;
			clock-names = "aux", "cfg_ahb", "pipe";

			assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
			assigned-clock-rates = <20000000>;

			resets = <&gcc GCC_PCIE1_PHY_BCR>,
				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
			reset-names = "phy", "common";

			#clock-cells = <0>;
			clock-output-names = "gcc_pcie1_pipe_clk_src";

			#phy-cells = <0>;
			status = "disabled";
		};

		cmn_pll: clock-controller@9b000 {
			compatible = "qcom,ipq9574-cmn-pll";
			reg = <0x0009b000 0x800>;
			clocks = <&ref_48mhz_clk>,
				 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
				 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
			clock-names = "ref", "ahb", "sys";
			#clock-cells = <1>;
			assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
			assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
		};

		qfprom: efuse@a4000 {
			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
			reg = <0x000a4000 0x5a1>;
			#address-cells = <1>;
			#size-cells = <1>;

			cpu_speed_bin: cpu-speed-bin@15 {
				reg = <0x15 0x2>;
				bits = <7 2>;
			};
		};

		cryptobam: dma-controller@704000 {
			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
			reg = <0x00704000 0x20000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			qcom,ee = <1>;
			qcom,num-ees = <4>;
			num-channels = <16>;
			qcom,controlled-remotely;
		};

		crypto: crypto@73a000 {
			compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
			reg = <0x0073a000 0x6000>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_CLK>;
			clock-names = "iface", "bus", "core";
			dmas = <&cryptobam 2>, <&cryptobam 3>;
			dma-names = "rx", "tx";
		};

		tsens: thermal-sensor@4a9000 {
			compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
			reg = <0x004a9000 0x1000>,
			      <0x004a8000 0x1000>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "combined";
			#qcom,sensors = <16>;
			#thermal-sensor-cells = <1>;
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq9574-tlmm";
			reg = <0x01000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 0 65>;
			interrupt-controller;
			#interrupt-cells = <2>;

			uart2_pins: uart2-state {
				pins = "gpio34", "gpio35";
				function = "blsp2_uart";
				drive-strength = <8>;
				bias-disable;
			};
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,ipq9574-gcc";
			reg = <0x01800000 0x80000>;
			clocks = <&xo_board_clk>,
				 <&sleep_clk>,
				 <0>,
				 <&pcie0_phy>,
				 <&pcie1_phy>,
				 <&pcie2_phy>,
				 <&pcie3_phy>,
				 <0>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#interconnect-cells = <1>;
		};

		tcsr_mutex: hwlock@1905000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x01905000 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-ipq9574", "syscon";
			reg = <0x01937000 0x21000>;
		};

		sdhc_1: mmc@7804000 {
			compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
			reg = <0x07804000 0x1000>,
			      <0x07805000 0x1000>,
			      <0x07808000 0x2000>;
			reg-names = "hc", "cqhci", "ice";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&xo_board_clk>,
				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
			clock-names = "iface", "core", "xo", "ice";
			non-removable;
			supports-cqe;
			status = "disabled";
		};

		blsp_dma: dma-controller@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x2b000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		blsp1_uart0: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart1: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart2: serial@78b1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b1000 0x200>;
			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart3: serial@78b2000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b2000 0x200>;
			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart4: serial@78b3000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b3000 0x200>;
			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart5: serial@78b4000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b4000 0x200>;
			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_spi0: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_i2c1: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b6000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			assigned-clock-rates = <50000000>;
			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_spi1: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_i2c2: i2c@78b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b7000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
			assigned-clock-rates = <50000000>;
			dmas = <&blsp_dma 16>, <&blsp_dma 17>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_spi2: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 16>, <&blsp_dma 17>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_i2c3: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b8000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			assigned-clock-rates = <50000000>;
			dmas = <&blsp_dma 18>, <&blsp_dma 19>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_spi3: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			spi-max-frequency = <50000000>;
			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 18>, <&blsp_dma 19>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_i2c4: i2c@78b9000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b9000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
			assigned-clock-rates = <50000000>;
			dmas = <&blsp_dma 20>, <&blsp_dma 21>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_spi4: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 20>, <&blsp_dma 21>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		qpic_bam: dma-controller@7984000 {
			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
			reg = <0x07984000 0x1c000>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		qpic_nand: spi@79b0000 {
			compatible = "qcom,ipq9574-snand";
			reg = <0x079b0000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_QPIC_CLK>,
				 <&gcc GCC_QPIC_AHB_CLK>,
				 <&gcc GCC_QPIC_IO_MACRO_CLK>;
			clock-names = "core", "aon", "iom";
			dmas = <&qpic_bam 0>,
			       <&qpic_bam 1>,
			       <&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			status = "disabled";
		};

		usb_0_qusbphy: phy@7b000 {
			compatible = "qcom,ipq9574-qusb2-phy";
			reg = <0x0007b000 0x180>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				 <&xo_board_clk>;
			clock-names = "cfg_ahb",
				      "ref";

			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
			status = "disabled";
		};

		usb_0_qmpphy: phy@7d000 {
			compatible = "qcom,ipq9574-qmp-usb3-phy";
			reg = <0x0007d000 0xa00>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB0_AUX_CLK>,
				 <&xo_board_clk>,
				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
				 <&gcc GCC_USB0_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "cfg_ahb",
				      "pipe";

			resets = <&gcc GCC_USB0_PHY_BCR>,
				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
			reset-names = "phy",
				      "phy_phy";

			#clock-cells = <0>;
			clock-output-names = "usb0_pipe_clk";

			status = "disabled";
		};

		usb3: usb@8af8800 {
			compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
			reg = <0x08af8800 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_SNOC_USB_CLK>,
				 <&gcc GCC_USB0_MASTER_CLK>,
				 <&gcc GCC_ANOC_USB_AXI_CLK>,
				 <&gcc GCC_USB0_SLEEP_CLK>,
				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;

			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi";

			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
			assigned-clock-rates = <200000000>,
					       <24000000>;

			interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pwr_event";

			resets = <&gcc GCC_USB_BCR>;
			status = "disabled";

			usb_0_dwc3: usb@8a00000 {
				compatible = "snps,dwc3";
				reg = <0x8a00000 0xcd00>;
				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
				clock-names = "ref";
				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
				phy-names = "usb2-phy", "usb3-phy";
				tx-fifo-resize;
				snps,is-utmi-l1-suspend;
				snps,hird-threshold = /bits/ 8 <0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_u3_susphy_quirk;
			};
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			reg = <0x0b000000 0x1000>,  /* GICD */
			      <0x0b002000 0x2000>,  /* GICC */
			      <0x0b001000 0x1000>,  /* GICH */
			      <0x0b004000 0x2000>;  /* GICV */
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			ranges = <0 0x0b00c000 0x3000>;

			v2m0: v2m@0 {
				compatible = "arm,gic-v2m-frame";
				reg = <0x00000000 0xffd>;
				msi-controller;
			};

			v2m1: v2m@1000 {
				compatible = "arm,gic-v2m-frame";
				reg = <0x00001000 0xffd>;
				msi-controller;
			};

			v2m2: v2m@2000 {
				compatible = "arm,gic-v2m-frame";
				reg = <0x00002000 0xffd>;
				msi-controller;
			};
		};

		watchdog: watchdog@b017000 {
			compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
			reg = <0x0b017000 0x1000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sleep_clk>;
			timeout-sec = <30>;
		};

		apcs_glb: mailbox@b111000 {
			compatible = "qcom,ipq9574-apcs-apps-global",
				     "qcom,ipq6018-apcs-apps-global";
			reg = <0x0b111000 0x1000>;
			#clock-cells = <1>;
			clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
			clock-names = "pll", "xo", "gpll0";
			#mbox-cells = <1>;
		};

		a73pll: clock@b116000 {
			compatible = "qcom,ipq9574-a73pll";
			reg = <0x0b116000 0x40>;
			#clock-cells = <0>;
			clocks = <&xo_board_clk>;
			clock-names = "xo";
		};

		timer@b120000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x0b120000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			frame@b120000 {
				reg = <0x0b121000 0x1000>,
				      <0x0b122000 0x1000>;
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			};

			frame@b123000 {
				reg = <0x0b123000 0x1000>;
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@b124000 {
				reg = <0x0b124000 0x1000>;
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@b125000 {
				reg = <0x0b125000 0x1000>;
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@b126000 {
				reg = <0x0b126000 0x1000>;
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@b127000 {
				reg = <0x0b127000 0x1000>;
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			frame@b128000 {
				reg = <0x0b128000 0x1000>;
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
		};

		pcie1: pcie@10000000 {
			compatible = "qcom,pcie-ipq9574";
			reg = <0x10000000 0xf1d>,
			      <0x10000f20 0xa8>,
			      <0x10001000 0x1000>,
			      <0x000f8000 0x4000>,
			      <0x10100000 0x1000>,
			      <0x000fe000 0x1000>;
			reg-names = "dbi",
				    "elbi",
				    "atu",
				    "parf",
				    "config",
				    "mhi";
			device_type = "pci";
			linux,pci-domain = <1>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
				 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;

			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
				 <&gcc GCC_PCIE1_AXI_S_CLK>,
				 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
				 <&gcc GCC_PCIE1_RCHNG_CLK>,
				 <&gcc GCC_PCIE1_AHB_CLK>,
				 <&gcc GCC_PCIE1_AUX_CLK>;
			clock-names = "axi_m",
				      "axi_s",
				      "axi_bridge",
				      "rchng",
				      "ahb",
				      "aux";

			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
				 <&gcc GCC_PCIE1_AXI_S_ARES>,
				 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
				 <&gcc GCC_PCIE1_AXI_M_ARES>,
				 <&gcc GCC_PCIE1_AUX_ARES>,
				 <&gcc GCC_PCIE1_AHB_ARES>;
			reset-names = "pipe",
				      "sticky",
				      "axi_s_sticky",
				      "axi_s",
				      "axi_m_sticky",
				      "axi_m",
				      "aux",
				      "ahb";

			phys = <&pcie1_phy>;
			phy-names = "pciephy";
			interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
					<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
			interconnect-names = "pcie-mem", "cpu-pcie";
			status = "disabled";
		};

		pcie3: pcie@18000000 {
			compatible = "qcom,pcie-ipq9574";
			reg = <0x18000000 0xf1d>,
			      <0x18000f20 0xa8>,
			      <0x18001000 0x1000>,
			      <0x000f0000 0x4000>,
			      <0x18100000 0x1000>,
			      <0x000f6000 0x1000>;
			reg-names = "dbi",
				    "elbi",
				    "atu",
				    "parf",
				    "config",
				    "mhi";
			device_type = "pci";
			linux,pci-domain = <3>;
			bus-range = <0x00 0xff>;
			num-lanes = <2>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
				 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;

			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
				 <&gcc GCC_PCIE3_AXI_S_CLK>,
				 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
				 <&gcc GCC_PCIE3_RCHNG_CLK>,
				 <&gcc GCC_PCIE3_AHB_CLK>,
				 <&gcc GCC_PCIE3_AUX_CLK>;
			clock-names = "axi_m",
				      "axi_s",
				      "axi_bridge",
				      "rchng",
				      "ahb",
				      "aux";

			resets = <&gcc GCC_PCIE3_PIPE_ARES>,
				 <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
				 <&gcc GCC_PCIE3_AXI_S_ARES>,
				 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
				 <&gcc GCC_PCIE3_AXI_M_ARES>,
				 <&gcc GCC_PCIE3_AUX_ARES>,
				 <&gcc GCC_PCIE3_AHB_ARES>;
			reset-names = "pipe",
				      "sticky",
				      "axi_s_sticky",
				      "axi_s",
				      "axi_m_sticky",
				      "axi_m",
				      "aux",
				      "ahb";

			phys = <&pcie3_phy>;
			phy-names = "pciephy";
			interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
					<&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
			interconnect-names = "pcie-mem", "cpu-pcie";
			status = "disabled";
		};

		pcie2: pcie@20000000 {
			compatible = "qcom,pcie-ipq9574";
			reg = <0x20000000 0xf1d>,
			      <0x20000f20 0xa8>,
			      <0x20001000 0x1000>,
			      <0x00088000 0x4000>,
			      <0x20100000 0x1000>,
			      <0x0008e000 0x1000>;
			reg-names = "dbi",
				    "elbi",
				    "atu",
				    "parf",
				    "config",
				    "mhi";
			device_type = "pci";
			linux,pci-domain = <2>;
			bus-range = <0x00 0xff>;
			num-lanes = <2>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
				 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;

			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
				 <&gcc GCC_PCIE2_AXI_S_CLK>,
				 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
				 <&gcc GCC_PCIE2_RCHNG_CLK>,
				 <&gcc GCC_PCIE2_AHB_CLK>,
				 <&gcc GCC_PCIE2_AUX_CLK>;
			clock-names = "axi_m",
				      "axi_s",
				      "axi_bridge",
				      "rchng",
				      "ahb",
				      "aux";

			resets = <&gcc GCC_PCIE2_PIPE_ARES>,
				 <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
				 <&gcc GCC_PCIE2_AXI_S_ARES>,
				 <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
				 <&gcc GCC_PCIE2_AXI_M_ARES>,
				 <&gcc GCC_PCIE2_AUX_ARES>,
				 <&gcc GCC_PCIE2_AHB_ARES>;
			reset-names = "pipe",
				      "sticky",
				      "axi_s_sticky",
				      "axi_s",
				      "axi_m_sticky",
				      "axi_m",
				      "aux",
				      "ahb";

			phys = <&pcie2_phy>;
			phy-names = "pciephy";
			interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
					<&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
			interconnect-names = "pcie-mem", "cpu-pcie";
			status = "disabled";
		};

		pcie0: pci@28000000 {
			compatible = "qcom,pcie-ipq9574";
			reg = <0x28000000 0xf1d>,
			      <0x28000f20 0xa8>,
			      <0x28001000 0x1000>,
			      <0x00080000 0x4000>,
			      <0x28100000 0x1000>,
			      <0x00086000 0x1000>;
			reg-names = "dbi",
				    "elbi",
				    "atu",
				    "parf",
				    "config",
				    "mhi";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
				 <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
				 <&gcc GCC_PCIE0_AXI_S_CLK>,
				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
				 <&gcc GCC_PCIE0_RCHNG_CLK>,
				 <&gcc GCC_PCIE0_AHB_CLK>,
				 <&gcc GCC_PCIE0_AUX_CLK>;
			clock-names = "axi_m",
				      "axi_s",
				      "axi_bridge",
				      "rchng",
				      "ahb",
				      "aux";

			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
				 <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
				 <&gcc GCC_PCIE0_AXI_S_ARES>,
				 <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
				 <&gcc GCC_PCIE0_AXI_M_ARES>,
				 <&gcc GCC_PCIE0_AUX_ARES>,
				 <&gcc GCC_PCIE0_AHB_ARES>;
			reset-names = "pipe",
				      "sticky",
				      "axi_s_sticky",
				      "axi_s",
				      "axi_m_sticky",
				      "axi_m",
				      "aux",
				      "ahb";

			phys = <&pcie0_phy>;
			phy-names = "pciephy";
			interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
					<&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
			interconnect-names = "pcie-mem", "cpu-pcie";
			status = "disabled";
		};

		nsscc: clock-controller@39b00000 {
			compatible = "qcom,ipq9574-nsscc";
			reg = <0x39b00000 0x80000>;
			clocks = <&xo_board_clk>,
				 <&cmn_pll NSS_1200MHZ_CLK>,
				 <&cmn_pll PPE_353MHZ_CLK>,
				 <&gcc GPLL0_OUT_AUX>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <0>,
				 <&gcc GCC_NSSCC_CLK>;
			clock-names = "xo",
				      "nss_1200",
				      "ppe_353",
				      "gpll0_out",
				      "uniphy0_rx",
				      "uniphy0_tx",
				      "uniphy1_rx",
				      "uniphy1_tx",
				      "uniphy2_rx",
				      "uniphy2_tx",
				      "bus";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#interconnect-cells = <1>;
		};
	};

	thermal-zones {
		nss-top-thermal {
			thermal-sensors = <&tsens 3>;

			trips {
				nss-top-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		ubi-0-thermal {
			thermal-sensors = <&tsens 4>;

			trips {
				ubi_0-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		ubi-1-thermal {
			thermal-sensors = <&tsens 5>;

			trips {
				ubi_1-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		ubi-2-thermal {
			thermal-sensors = <&tsens 6>;

			trips {
				ubi_2-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		ubi-3-thermal {
			thermal-sensors = <&tsens 7>;

			trips {
				ubi_3-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss0-thermal {
			thermal-sensors = <&tsens 8>;

			trips {
				cpu-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss1-thermal {
			thermal-sensors = <&tsens 9>;

			trips {
				cpu-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu0-thermal {
			thermal-sensors = <&tsens 10>;

			trips {
				cpu0_crit: cpu-critical {
					temperature = <120000>;
					hysteresis = <10000>;
					type = "critical";
				};

				cpu0_alert: cpu-passive {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu0_alert>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu1-thermal {
			thermal-sensors = <&tsens 11>;

			trips {
				cpu1_crit: cpu-critical {
					temperature = <120000>;
					hysteresis = <10000>;
					type = "critical";
				};

				cpu1_alert: cpu-passive {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu1_alert>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu2-thermal {
			thermal-sensors = <&tsens 12>;

			trips {
				cpu2_crit: cpu-critical {
					temperature = <120000>;
					hysteresis = <10000>;
					type = "critical";
				};

				cpu2_alert: cpu-passive {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu2_alert>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu3-thermal {
			thermal-sensors = <&tsens 13>;

			trips {
				cpu3_crit: cpu-critical {
					temperature = <120000>;
					hysteresis = <10000>;
					type = "critical";
				};

				cpu3_alert: cpu-passive {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu3_alert>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		wcss-phyb-thermal {
			thermal-sensors = <&tsens 14>;

			trips {
				wcss_phyb-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		top-glue-thermal {
			thermal-sensors = <&tsens 15>;

			trips {
				top_glue-critical {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
};