1b59cd290SKathiravan T// SPDX-License-Identifier: BSD-3-Clause 2b59cd290SKathiravan T/* 3b59cd290SKathiravan T * IPQ5332 AP-MI01.2 board device tree source 4b59cd290SKathiravan T * 5b59cd290SKathiravan T * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6b59cd290SKathiravan T */ 7b59cd290SKathiravan T 8b59cd290SKathiravan T/dts-v1/; 9b59cd290SKathiravan T 106d5872f2SSridharan S N#include "ipq5332-rdp-common.dtsi" 11b59cd290SKathiravan T 12b59cd290SKathiravan T/ { 13b59cd290SKathiravan T model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; 14b59cd290SKathiravan T compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; 15b59cd290SKathiravan T}; 16b59cd290SKathiravan T 17b59cd290SKathiravan T&blsp1_i2c1 { 18b59cd290SKathiravan T clock-frequency = <400000>; 19b59cd290SKathiravan T pinctrl-0 = <&i2c_1_pins>; 20b59cd290SKathiravan T pinctrl-names = "default"; 21b59cd290SKathiravan T status = "okay"; 22b59cd290SKathiravan T}; 23b59cd290SKathiravan T 24b59cd290SKathiravan T&sdhc { 25b59cd290SKathiravan T bus-width = <4>; 26b59cd290SKathiravan T max-frequency = <192000000>; 27b59cd290SKathiravan T mmc-ddr-1_8v; 28b59cd290SKathiravan T mmc-hs200-1_8v; 29b59cd290SKathiravan T non-removable; 30b59cd290SKathiravan T pinctrl-0 = <&sdc_default_state>; 31b59cd290SKathiravan T pinctrl-names = "default"; 32b59cd290SKathiravan T status = "okay"; 33b59cd290SKathiravan T}; 34b59cd290SKathiravan T 35*1838d929SPraveenkumar I&pcie0 { 36*1838d929SPraveenkumar I pinctrl-0 = <&pcie0_default>; 37*1838d929SPraveenkumar I pinctrl-names = "default"; 38*1838d929SPraveenkumar I 39*1838d929SPraveenkumar I perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; 40*1838d929SPraveenkumar I wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; 41*1838d929SPraveenkumar I 42*1838d929SPraveenkumar I status = "okay"; 43*1838d929SPraveenkumar I}; 44*1838d929SPraveenkumar I 45*1838d929SPraveenkumar I&pcie0_phy { 46*1838d929SPraveenkumar I status = "okay"; 47*1838d929SPraveenkumar I}; 48*1838d929SPraveenkumar I 49*1838d929SPraveenkumar I&pcie1 { 50*1838d929SPraveenkumar I pinctrl-0 = <&pcie1_default>; 51*1838d929SPraveenkumar I pinctrl-names = "default"; 52*1838d929SPraveenkumar I 53*1838d929SPraveenkumar I perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; 54*1838d929SPraveenkumar I wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; 55*1838d929SPraveenkumar I 56*1838d929SPraveenkumar I status = "okay"; 57*1838d929SPraveenkumar I}; 58*1838d929SPraveenkumar I 59*1838d929SPraveenkumar I&pcie1_phy { 60*1838d929SPraveenkumar I status = "okay"; 61*1838d929SPraveenkumar I}; 62*1838d929SPraveenkumar I 63b59cd290SKathiravan T&tlmm { 64b59cd290SKathiravan T i2c_1_pins: i2c-1-state { 65b59cd290SKathiravan T pins = "gpio29", "gpio30"; 66b59cd290SKathiravan T function = "blsp1_i2c0"; 67b59cd290SKathiravan T drive-strength = <8>; 68b59cd290SKathiravan T bias-pull-up; 69b59cd290SKathiravan T }; 70b59cd290SKathiravan T 71*1838d929SPraveenkumar I pcie0_default: pcie0-default-state { 72*1838d929SPraveenkumar I clkreq-n-pins { 73*1838d929SPraveenkumar I pins = "gpio37"; 74*1838d929SPraveenkumar I function = "pcie0_clk"; 75*1838d929SPraveenkumar I drive-strength = <8>; 76*1838d929SPraveenkumar I bias-pull-up; 77*1838d929SPraveenkumar I }; 78*1838d929SPraveenkumar I 79*1838d929SPraveenkumar I perst-n-pins { 80*1838d929SPraveenkumar I pins = "gpio38"; 81*1838d929SPraveenkumar I function = "gpio"; 82*1838d929SPraveenkumar I drive-strength = <8>; 83*1838d929SPraveenkumar I bias-pull-up; 84*1838d929SPraveenkumar I output-low; 85*1838d929SPraveenkumar I }; 86*1838d929SPraveenkumar I 87*1838d929SPraveenkumar I wake-n-pins { 88*1838d929SPraveenkumar I pins = "gpio39"; 89*1838d929SPraveenkumar I function = "pcie0_wake"; 90*1838d929SPraveenkumar I drive-strength = <8>; 91*1838d929SPraveenkumar I bias-pull-up; 92*1838d929SPraveenkumar I }; 93*1838d929SPraveenkumar I }; 94*1838d929SPraveenkumar I 95*1838d929SPraveenkumar I pcie1_default: pcie1-default-state { 96*1838d929SPraveenkumar I clkreq-n-pins { 97*1838d929SPraveenkumar I pins = "gpio46"; 98*1838d929SPraveenkumar I function = "pcie1_clk"; 99*1838d929SPraveenkumar I drive-strength = <8>; 100*1838d929SPraveenkumar I bias-pull-up; 101*1838d929SPraveenkumar I }; 102*1838d929SPraveenkumar I 103*1838d929SPraveenkumar I perst-n-pins { 104*1838d929SPraveenkumar I pins = "gpio47"; 105*1838d929SPraveenkumar I function = "gpio"; 106*1838d929SPraveenkumar I drive-strength = <8>; 107*1838d929SPraveenkumar I bias-pull-up; 108*1838d929SPraveenkumar I output-low; 109*1838d929SPraveenkumar I }; 110*1838d929SPraveenkumar I 111*1838d929SPraveenkumar I wake-n-pins { 112*1838d929SPraveenkumar I pins = "gpio48"; 113*1838d929SPraveenkumar I function = "pcie1_wake"; 114*1838d929SPraveenkumar I drive-strength = <8>; 115*1838d929SPraveenkumar I bias-pull-up; 116*1838d929SPraveenkumar I }; 117*1838d929SPraveenkumar I }; 118*1838d929SPraveenkumar I 119b59cd290SKathiravan T sdc_default_state: sdc-default-state { 120b59cd290SKathiravan T clk-pins { 121b59cd290SKathiravan T pins = "gpio13"; 122b59cd290SKathiravan T function = "sdc_clk"; 123b59cd290SKathiravan T drive-strength = <8>; 124b59cd290SKathiravan T bias-disable; 125b59cd290SKathiravan T }; 126b59cd290SKathiravan T 127b59cd290SKathiravan T cmd-pins { 128b59cd290SKathiravan T pins = "gpio12"; 129b59cd290SKathiravan T function = "sdc_cmd"; 130b59cd290SKathiravan T drive-strength = <8>; 131b59cd290SKathiravan T bias-pull-up; 132b59cd290SKathiravan T }; 133b59cd290SKathiravan T 134b59cd290SKathiravan T data-pins { 135b59cd290SKathiravan T pins = "gpio8", "gpio9", "gpio10", "gpio11"; 136b59cd290SKathiravan T function = "sdc_data"; 137b59cd290SKathiravan T drive-strength = <8>; 138b59cd290SKathiravan T bias-pull-up; 139b59cd290SKathiravan T }; 140b59cd290SKathiravan T }; 141b59cd290SKathiravan T}; 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