1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-dispcc.h> 7#include <dt-bindings/clock/qcom,glymur-gcc.h> 8#include <dt-bindings/clock/qcom,glymur-gpucc.h> 9#include <dt-bindings/clock/qcom,glymur-tcsr.h> 10#include <dt-bindings/clock/qcom,glymur-videocc.h> 11#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/spmi/spmi.h> 25 26#include "glymur-ipcc.h" 27 28/ { 29 interrupt-parent = <&intc>; 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "qcom,oryon-2-2"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 43 power-domain-names = "psci", "perf"; 44 next-level-cache = <&l2_0>; 45 #cooling-cells = <2>; 46 47 l2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 cache-unified; 51 }; 52 }; 53 54 cpu1: cpu@100 { 55 device_type = "cpu"; 56 compatible = "qcom,oryon-2-2"; 57 reg = <0x0 0x100>; 58 enable-method = "psci"; 59 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 60 power-domain-names = "psci", "perf"; 61 next-level-cache = <&l2_0>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@200 { 66 device_type = "cpu"; 67 compatible = "qcom,oryon-2-2"; 68 reg = <0x0 0x200>; 69 enable-method = "psci"; 70 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 71 power-domain-names = "psci", "perf"; 72 next-level-cache = <&l2_0>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu3: cpu@300 { 77 device_type = "cpu"; 78 compatible = "qcom,oryon-2-2"; 79 reg = <0x0 0x300>; 80 enable-method = "psci"; 81 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 82 power-domain-names = "psci", "perf"; 83 next-level-cache = <&l2_0>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu4: cpu@400 { 88 device_type = "cpu"; 89 compatible = "qcom,oryon-2-2"; 90 reg = <0x0 0x400>; 91 enable-method = "psci"; 92 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 93 power-domain-names = "psci", "perf"; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu5: cpu@500 { 99 device_type = "cpu"; 100 compatible = "qcom,oryon-2-2"; 101 reg = <0x0 0x500>; 102 enable-method = "psci"; 103 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 104 power-domain-names = "psci", "perf"; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu6: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "qcom,oryon-2-1"; 112 reg = <0x0 0x10000>; 113 enable-method = "psci"; 114 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 115 power-domain-names = "psci", "perf"; 116 next-level-cache = <&l2_1>; 117 #cooling-cells = <2>; 118 119 l2_1: l2-cache { 120 compatible = "cache"; 121 cache-level = <2>; 122 cache-unified; 123 }; 124 }; 125 126 cpu7: cpu@10100 { 127 device_type = "cpu"; 128 compatible = "qcom,oryon-2-1"; 129 reg = <0x0 0x10100>; 130 enable-method = "psci"; 131 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 132 power-domain-names = "psci", "perf"; 133 next-level-cache = <&l2_1>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu8: cpu@10200 { 138 device_type = "cpu"; 139 compatible = "qcom,oryon-2-1"; 140 reg = <0x0 0x10200>; 141 enable-method = "psci"; 142 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 143 power-domain-names = "psci", "perf"; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu9: cpu@10300 { 149 device_type = "cpu"; 150 compatible = "qcom,oryon-2-1"; 151 reg = <0x0 0x10300>; 152 enable-method = "psci"; 153 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 154 power-domain-names = "psci", "perf"; 155 next-level-cache = <&l2_1>; 156 #cooling-cells = <2>; 157 }; 158 159 cpu10: cpu@10400 { 160 device_type = "cpu"; 161 compatible = "qcom,oryon-2-1"; 162 reg = <0x0 0x10400>; 163 enable-method = "psci"; 164 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 165 power-domain-names = "psci", "perf"; 166 next-level-cache = <&l2_1>; 167 #cooling-cells = <2>; 168 }; 169 170 cpu11: cpu@10500 { 171 device_type = "cpu"; 172 compatible = "qcom,oryon-2-1"; 173 reg = <0x0 0x10500>; 174 enable-method = "psci"; 175 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 176 power-domain-names = "psci", "perf"; 177 next-level-cache = <&l2_1>; 178 #cooling-cells = <2>; 179 }; 180 181 cpu12: cpu@20000 { 182 device_type = "cpu"; 183 compatible = "qcom,oryon-2-1"; 184 reg = <0x0 0x20000>; 185 enable-method = "psci"; 186 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 187 power-domain-names = "psci", "perf"; 188 next-level-cache = <&l2_2>; 189 #cooling-cells = <2>; 190 191 l2_2: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 }; 196 }; 197 198 cpu13: cpu@20100 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon-2-1"; 201 reg = <0x0 0x20100>; 202 enable-method = "psci"; 203 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 204 power-domain-names = "psci", "perf"; 205 next-level-cache = <&l2_2>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu14: cpu@20200 { 210 device_type = "cpu"; 211 compatible = "qcom,oryon-2-1"; 212 reg = <0x0 0x20200>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 215 power-domain-names = "psci", "perf"; 216 next-level-cache = <&l2_2>; 217 #cooling-cells = <2>; 218 }; 219 220 cpu15: cpu@20300 { 221 device_type = "cpu"; 222 compatible = "qcom,oryon-2-1"; 223 reg = <0x0 0x20300>; 224 enable-method = "psci"; 225 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 226 power-domain-names = "psci", "perf"; 227 next-level-cache = <&l2_2>; 228 #cooling-cells = <2>; 229 }; 230 231 cpu16: cpu@20400 { 232 device_type = "cpu"; 233 compatible = "qcom,oryon-2-1"; 234 reg = <0x0 0x20400>; 235 enable-method = "psci"; 236 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 237 power-domain-names = "psci", "perf"; 238 next-level-cache = <&l2_2>; 239 #cooling-cells = <2>; 240 }; 241 242 cpu17: cpu@20500 { 243 device_type = "cpu"; 244 compatible = "qcom,oryon-2-1"; 245 reg = <0x0 0x20500>; 246 enable-method = "psci"; 247 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 248 power-domain-names = "psci", "perf"; 249 next-level-cache = <&l2_2>; 250 #cooling-cells = <2>; 251 }; 252 253 cpu-map { 254 cluster0 { 255 core0 { 256 cpu = <&cpu0>; 257 }; 258 259 core1 { 260 cpu = <&cpu1>; 261 }; 262 263 core2 { 264 cpu = <&cpu2>; 265 }; 266 267 core3 { 268 cpu = <&cpu3>; 269 }; 270 271 core4 { 272 cpu = <&cpu4>; 273 }; 274 275 core5 { 276 cpu = <&cpu5>; 277 }; 278 }; 279 280 cluster1 { 281 core0 { 282 cpu = <&cpu6>; 283 }; 284 285 core1 { 286 cpu = <&cpu7>; 287 }; 288 289 core2 { 290 cpu = <&cpu8>; 291 }; 292 293 core3 { 294 cpu = <&cpu9>; 295 }; 296 297 core4 { 298 cpu = <&cpu10>; 299 }; 300 301 core5 { 302 cpu = <&cpu11>; 303 }; 304 }; 305 306 cpu_map_cluster2: cluster2 { 307 core0 { 308 cpu = <&cpu12>; 309 }; 310 311 core1 { 312 cpu = <&cpu13>; 313 }; 314 315 core2 { 316 cpu = <&cpu14>; 317 }; 318 319 core3 { 320 cpu = <&cpu15>; 321 }; 322 323 core4 { 324 cpu = <&cpu16>; 325 }; 326 327 core5 { 328 cpu = <&cpu17>; 329 }; 330 }; 331 }; 332 333 idle-states { 334 entry-method = "psci"; 335 336 cpu_c4: cpu-sleep-0 { 337 compatible = "arm,idle-state"; 338 idle-state-name = "ret"; 339 arm,psci-suspend-param = <0x00000004>; 340 entry-latency-us = <180>; 341 exit-latency-us = <320>; 342 min-residency-us = <1000>; 343 }; 344 }; 345 346 domain-idle-states { 347 cluster_cl5: cluster-sleep-0 { 348 compatible = "domain-idle-state"; 349 arm,psci-suspend-param = <0x01000054>; 350 entry-latency-us = <2000>; 351 exit-latency-us = <2000>; 352 min-residency-us = <9000>; 353 }; 354 355 domain_ss3: domain-sleep-0 { 356 compatible = "domain-idle-state"; 357 arm,psci-suspend-param = <0x0200c354>; 358 entry-latency-us = <2800>; 359 exit-latency-us = <4400>; 360 min-residency-us = <10150>; 361 }; 362 }; 363 }; 364 365 dummy-sink { 366 compatible = "arm,coresight-dummy-sink"; 367 368 in-ports { 369 port { 370 eud_in: endpoint { 371 remote-endpoint = <&swao_rep_out1>; 372 }; 373 }; 374 }; 375 }; 376 377 firmware { 378 scm: scm { 379 compatible = "qcom,scm-glymur", "qcom,scm"; 380 qcom,dload-mode = <&tcsr 0x4000>; 381 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 382 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 383 }; 384 385 scmi { 386 compatible = "arm,scmi"; 387 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 388 mbox-names = "tx", "rx"; 389 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 390 391 #address-cells = <1>; 392 #size-cells = <0>; 393 394 scmi_perf: protocol@13 { 395 reg = <0x13>; 396 #power-domain-cells = <1>; 397 }; 398 }; 399 }; 400 401 clk_virt: interconnect-0 { 402 compatible = "qcom,glymur-clk-virt"; 403 #interconnect-cells = <2>; 404 qcom,bcm-voters = <&apps_bcm_voter>; 405 }; 406 407 mc_virt: interconnect-1 { 408 compatible = "qcom,glymur-mc-virt"; 409 #interconnect-cells = <2>; 410 qcom,bcm-voters = <&apps_bcm_voter>; 411 }; 412 413 pmu { 414 compatible = "arm,armv8-pmuv3"; 415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 416 }; 417 418 psci { 419 compatible = "arm,psci-1.0"; 420 method = "smc"; 421 422 cpu_pd0: power-domain-cpu0 { 423 #power-domain-cells = <0>; 424 power-domains = <&cluster0_pd>; 425 domain-idle-states = <&cpu_c4>; 426 }; 427 428 cpu_pd1: power-domain-cpu1 { 429 #power-domain-cells = <0>; 430 power-domains = <&cluster0_pd>; 431 domain-idle-states = <&cpu_c4>; 432 }; 433 434 cpu_pd2: power-domain-cpu2 { 435 #power-domain-cells = <0>; 436 power-domains = <&cluster0_pd>; 437 domain-idle-states = <&cpu_c4>; 438 }; 439 440 cpu_pd3: power-domain-cpu3 { 441 #power-domain-cells = <0>; 442 power-domains = <&cluster0_pd>; 443 domain-idle-states = <&cpu_c4>; 444 }; 445 446 cpu_pd4: power-domain-cpu4 { 447 #power-domain-cells = <0>; 448 power-domains = <&cluster0_pd>; 449 domain-idle-states = <&cpu_c4>; 450 }; 451 452 cpu_pd5: power-domain-cpu5 { 453 #power-domain-cells = <0>; 454 power-domains = <&cluster0_pd>; 455 domain-idle-states = <&cpu_c4>; 456 }; 457 458 cpu_pd6: power-domain-cpu6 { 459 #power-domain-cells = <0>; 460 power-domains = <&cluster1_pd>; 461 domain-idle-states = <&cpu_c4>; 462 }; 463 464 cpu_pd7: power-domain-cpu7 { 465 #power-domain-cells = <0>; 466 power-domains = <&cluster1_pd>; 467 domain-idle-states = <&cpu_c4>; 468 }; 469 470 cpu_pd8: power-domain-cpu8 { 471 #power-domain-cells = <0>; 472 power-domains = <&cluster1_pd>; 473 domain-idle-states = <&cpu_c4>; 474 }; 475 476 cpu_pd9: power-domain-cpu9 { 477 #power-domain-cells = <0>; 478 power-domains = <&cluster1_pd>; 479 domain-idle-states = <&cpu_c4>; 480 }; 481 482 cpu_pd10: power-domain-cpu10 { 483 #power-domain-cells = <0>; 484 power-domains = <&cluster1_pd>; 485 domain-idle-states = <&cpu_c4>; 486 }; 487 488 cpu_pd11: power-domain-cpu11 { 489 #power-domain-cells = <0>; 490 power-domains = <&cluster1_pd>; 491 domain-idle-states = <&cpu_c4>; 492 }; 493 494 cpu_pd12: power-domain-cpu12 { 495 #power-domain-cells = <0>; 496 power-domains = <&cluster2_pd>; 497 domain-idle-states = <&cpu_c4>; 498 }; 499 500 cpu_pd13: power-domain-cpu13 { 501 #power-domain-cells = <0>; 502 power-domains = <&cluster2_pd>; 503 domain-idle-states = <&cpu_c4>; 504 }; 505 506 cpu_pd14: power-domain-cpu14 { 507 #power-domain-cells = <0>; 508 power-domains = <&cluster2_pd>; 509 domain-idle-states = <&cpu_c4>; 510 }; 511 512 cpu_pd15: power-domain-cpu15 { 513 #power-domain-cells = <0>; 514 power-domains = <&cluster2_pd>; 515 domain-idle-states = <&cpu_c4>; 516 }; 517 518 cpu_pd16: power-domain-cpu16 { 519 #power-domain-cells = <0>; 520 power-domains = <&cluster2_pd>; 521 domain-idle-states = <&cpu_c4>; 522 }; 523 524 cpu_pd17: power-domain-cpu17 { 525 #power-domain-cells = <0>; 526 power-domains = <&cluster2_pd>; 527 domain-idle-states = <&cpu_c4>; 528 }; 529 530 cluster0_pd: power-domain-cpu-cluster0 { 531 #power-domain-cells = <0>; 532 power-domains = <&system_pd>; 533 domain-idle-states = <&cluster_cl5>; 534 }; 535 536 cluster1_pd: power-domain-cpu-cluster1 { 537 #power-domain-cells = <0>; 538 power-domains = <&system_pd>; 539 domain-idle-states = <&cluster_cl5>; 540 }; 541 542 cluster2_pd: power-domain-cpu-cluster2 { 543 #power-domain-cells = <0>; 544 power-domains = <&system_pd>; 545 domain-idle-states = <&cluster_cl5>; 546 }; 547 548 system_pd: power-domain-system { 549 #power-domain-cells = <0>; 550 domain-idle-states = <&domain_ss3>; 551 }; 552 }; 553 554 reserved-memory { 555 #address-cells = <2>; 556 #size-cells = <2>; 557 ranges; 558 559 pdp_mem: pdp@81400000 { 560 reg = <0x0 0x81400000 0x0 0x100000>; 561 no-map; 562 }; 563 564 aop_cmd_db_mem: aop-cmd-db@81c60000 { 565 compatible = "qcom,cmd-db"; 566 reg = <0x0 0x81c60000 0x0 0x20000>; 567 no-map; 568 }; 569 570 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 571 reg = <0x0 0x81e00000 0x0 0x200000>; 572 no-map; 573 }; 574 575 oobdaretag_mem: oobdaretag@86e10000 { 576 reg = <0x0 0x86e10000 0x0 0x360000>; 577 no-map; 578 }; 579 580 oob_secure_mem: oob-secure@87170000 { 581 reg = <0x0 0x87170000 0x0 0xbc0000>; 582 no-map; 583 }; 584 585 oobdtbqc_mem: oobdtbqc@87d30000 { 586 reg = <0x0 0x87d30000 0x0 0x20000>; 587 no-map; 588 }; 589 590 oobdtboem_mem: oobdtboem@87d50000 { 591 reg = <0x0 0x87d50000 0x0 0x20000>; 592 no-map; 593 }; 594 595 oob_nonsecure_mem: oob-nonsecure@87e00000 { 596 reg = <0x0 0x87e00000 0x0 0xc00000>; 597 no-map; 598 }; 599 600 spss_region_mem: spss@88a00000 { 601 reg = <0x0 0x88a00000 0x0 0x400000>; 602 no-map; 603 }; 604 605 soccpdtb_mem: soccpdtb@892e0000 { 606 reg = <0x0 0x892e0000 0x0 0x20000>; 607 no-map; 608 }; 609 610 soccp_mem: soccp@89300000 { 611 reg = <0x0 0x89300000 0x0 0x400000>; 612 no-map; 613 }; 614 615 cvp_mem: cvp@89700000 { 616 reg = <0x0 0x89700000 0x0 0x700000>; 617 no-map; 618 }; 619 620 adspslpi_mem: adspslpi@89e00000 { 621 reg = <0x0 0x89e00000 0x0 0x3a00000>; 622 no-map; 623 }; 624 625 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 626 reg = <0x0 0x8d800000 0x0 0x80000>; 627 no-map; 628 }; 629 630 cdsp_mem: cdsp@8d900000 { 631 reg = <0x0 0x8d900000 0x0 0x4000000>; 632 no-map; 633 }; 634 635 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 636 reg = <0x0 0x91900000 0x0 0x80000>; 637 no-map; 638 }; 639 640 gpu_microcode_mem: gpu-microcode@919fe000 { 641 reg = <0x0 0x919fe000 0x0 0x2000>; 642 no-map; 643 }; 644 645 camera_mem: camera@91a00000 { 646 reg = <0x0 0x91a00000 0x0 0x800000>; 647 no-map; 648 }; 649 650 av1_encoder_mem: av1-encoder@92200000 { 651 reg = <0x0 0x92200000 0x0 0x700000>; 652 no-map; 653 }; 654 655 video_mem: video@92900000 { 656 reg = <0x0 0x92900000 0x0 0xc00000>; 657 no-map; 658 }; 659 660 smem_mem: smem@ffe00000 { 661 compatible = "qcom,smem"; 662 reg = <0x0 0xffe00000 0x0 0x200000>; 663 hwlocks = <&tcsr_mutex 3>; 664 no-map; 665 }; 666 }; 667 668 smp2p-adsp { 669 compatible = "qcom,smp2p"; 670 671 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 672 IPCC_MPROC_SIGNAL_SMP2P 673 IRQ_TYPE_EDGE_RISING>; 674 675 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 676 677 qcom,smem = <443>, <429>; 678 qcom,local-pid = <0>; 679 qcom,remote-pid = <2>; 680 681 smp2p_adsp_out: master-kernel { 682 qcom,entry-name = "master-kernel"; 683 #qcom,smem-state-cells = <1>; 684 }; 685 686 smp2p_adsp_in: slave-kernel { 687 qcom,entry-name = "slave-kernel"; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 }; 691 }; 692 693 smp2p-cdsp { 694 compatible = "qcom,smp2p"; 695 696 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 697 IPCC_MPROC_SIGNAL_SMP2P 698 IRQ_TYPE_EDGE_RISING>; 699 700 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 701 702 qcom,smem = <94>, <432>; 703 qcom,local-pid = <0>; 704 qcom,remote-pid = <5>; 705 706 smp2p_cdsp_out: master-kernel { 707 qcom,entry-name = "master-kernel"; 708 #qcom,smem-state-cells = <1>; 709 }; 710 711 smp2p_cdsp_in: slave-kernel { 712 qcom,entry-name = "slave-kernel"; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 }; 717 718 smp2p-soccp { 719 compatible = "qcom,smp2p"; 720 721 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 722 IPCC_MPROC_SIGNAL_SMP2P 723 IRQ_TYPE_EDGE_RISING>; 724 725 mboxes = <&ipcc IPCC_MPROC_SOCCP 726 IPCC_MPROC_SIGNAL_SMP2P>; 727 728 qcom,smem = <617>, <616>; 729 qcom,local-pid = <0>; 730 qcom,remote-pid = <19>; 731 732 soccp_smp2p_out: master-kernel { 733 qcom,entry-name = "master-kernel"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 soccp_smp2p_in: slave-kernel { 738 qcom,entry-name = "slave-kernel"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 }; 743 744 soc: soc@0 { 745 compatible = "simple-bus"; 746 #address-cells = <2>; 747 #size-cells = <2>; 748 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 749 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 750 751 gcc: clock-controller@100000 { 752 compatible = "qcom,glymur-gcc"; 753 reg = <0x0 0x00100000 0x0 0x1f9000>; 754 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 755 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 756 <&sleep_clk>, /* Sleep */ 757 <0>, /* USB 0 Phy DP0 GMUX */ 758 <0>, /* USB 0 Phy DP1 GMUX */ 759 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 760 <0>, /* USB 0 Phy PIPEGMUX */ 761 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 762 <0>, /* USB 1 Phy DP0 GMUX 2 */ 763 <0>, /* USB 1 Phy DP1 GMUX 2 */ 764 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 765 <0>, /* USB 1 Phy PIPEGMUX */ 766 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 767 <0>, /* USB 2 Phy DP0 GMUX 2 */ 768 <0>, /* USB 2 Phy DP1 GMUX 2 */ 769 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 770 <0>, /* USB 2 Phy PIPEGMUX */ 771 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 772 <0>, /* PCIe 3a */ 773 <&pcie3b_phy>, /* PCIe 3b */ 774 <&pcie4_phy>, /* PCIe 4 */ 775 <&pcie5_phy>, /* PCIe 5 */ 776 <&pcie6_phy>, /* PCIe 6 */ 777 <0>, /* QUSB4 0 PHY RX 0 */ 778 <0>, /* QUSB4 0 PHY RX 1 */ 779 <0>, /* QUSB4 1 PHY RX 0 */ 780 <0>, /* QUSB4 1 PHY RX 1 */ 781 <0>, /* QUSB4 2 PHY RX 0 */ 782 <0>, /* QUSB4 2 PHY RX 1 */ 783 <0>, /* UFS PHY RX Symbol 0 */ 784 <0>, /* UFS PHY RX Symbol 1 */ 785 <0>, /* UFS PHY TX Symbol 0 */ 786 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 787 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 788 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 789 <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, 790 <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, 791 <0>, /* USB4 PHY 0 pcie pipe */ 792 <0>, /* USB4 PHY 0 Max pipe */ 793 <0>, /* USB4 PHY 1 pcie pipe */ 794 <0>, /* USB4 PHY 1 Max pipe */ 795 <0>, /* USB4 PHY 2 pcie */ 796 <0>; /* USB4 PHY 2 Max */ 797 #clock-cells = <1>; 798 #reset-cells = <1>; 799 #power-domain-cells = <1>; 800 }; 801 802 gpi_dma2: dma-controller@800000 { 803 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 804 reg = <0x0 0x00800000 0x0 0x60000>; 805 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 821 dma-channels = <16>; 822 dma-channel-mask = <0x3f>; 823 #dma-cells = <3>; 824 iommus = <&apps_smmu 0xd76 0x0>; 825 }; 826 827 qupv3_2: geniqup@8c0000 { 828 compatible = "qcom,geni-se-qup"; 829 reg = <0x0 0x008c0000 0x0 0x3000>; 830 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 831 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 832 clock-names = "m-ahb", 833 "s-ahb"; 834 iommus = <&apps_smmu 0xd63 0x0>; 835 #address-cells = <2>; 836 #size-cells = <2>; 837 ranges; 838 839 i2c16: i2c@880000 { 840 compatible = "qcom,geni-i2c"; 841 reg = <0x0 0x00880000 0x0 0x4000>; 842 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 844 clock-names = "se"; 845 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 846 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 847 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 848 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 849 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 850 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 851 interconnect-names = "qup-core", 852 "qup-config", 853 "qup-memory"; 854 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 855 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 856 dma-names = "tx", 857 "rx"; 858 pinctrl-0 = <&qup_i2c16_data_clk>; 859 pinctrl-names = "default"; 860 #address-cells = <1>; 861 #size-cells = <0>; 862 863 status = "disabled"; 864 }; 865 866 spi16: spi@880000 { 867 compatible = "qcom,geni-spi"; 868 reg = <0x0 0x00880000 0x0 0x4000>; 869 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 871 clock-names = "se"; 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 873 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 874 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 875 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 876 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 877 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 878 interconnect-names = "qup-core", 879 "qup-config", 880 "qup-memory"; 881 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 882 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 883 dma-names = "tx", 884 "rx"; 885 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 886 pinctrl-names = "default"; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 890 status = "disabled"; 891 }; 892 893 i2c17: i2c@884000 { 894 compatible = "qcom,geni-i2c"; 895 reg = <0x0 0x00884000 0x0 0x4000>; 896 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 898 clock-names = "se"; 899 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 900 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 901 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 902 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 903 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 904 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 905 interconnect-names = "qup-core", 906 "qup-config", 907 "qup-memory"; 908 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 909 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 910 dma-names = "tx", 911 "rx"; 912 pinctrl-0 = <&qup_i2c17_data_clk>; 913 pinctrl-names = "default"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 917 status = "disabled"; 918 }; 919 920 spi17: spi@884000 { 921 compatible = "qcom,geni-spi"; 922 reg = <0x0 0x00884000 0x0 0x4000>; 923 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 925 clock-names = "se"; 926 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 927 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 928 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 929 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 930 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 931 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 932 interconnect-names = "qup-core", 933 "qup-config", 934 "qup-memory"; 935 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 936 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 937 dma-names = "tx", 938 "rx"; 939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 940 pinctrl-names = "default"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 944 status = "disabled"; 945 }; 946 947 i2c18: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0x0 0x00888000 0x0 0x4000>; 950 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 952 clock-names = "se"; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 954 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 955 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 956 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 957 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 958 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 959 interconnect-names = "qup-core", 960 "qup-config", 961 "qup-memory"; 962 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 963 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 964 dma-names = "tx", 965 "rx"; 966 pinctrl-0 = <&qup_i2c18_data_clk>; 967 pinctrl-names = "default"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 971 status = "disabled"; 972 }; 973 974 spi18: spi@888000 { 975 compatible = "qcom,geni-spi"; 976 reg = <0x0 0x00888000 0x0 0x4000>; 977 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 979 clock-names = "se"; 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 981 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 982 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 983 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 984 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 986 interconnect-names = "qup-core", 987 "qup-config", 988 "qup-memory"; 989 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 990 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 991 dma-names = "tx", 992 "rx"; 993 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 994 pinctrl-names = "default"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 status = "disabled"; 999 }; 1000 1001 i2c19: i2c@88c000 { 1002 compatible = "qcom,geni-i2c"; 1003 reg = <0x0 0x0088c000 0x0 0x4000>; 1004 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1006 clock-names = "se"; 1007 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1008 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1009 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1010 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1011 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1012 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1013 interconnect-names = "qup-core", 1014 "qup-config", 1015 "qup-memory"; 1016 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1017 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1018 dma-names = "tx", 1019 "rx"; 1020 pinctrl-0 = <&qup_i2c19_data_clk>; 1021 pinctrl-names = "default"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 1025 status = "disabled"; 1026 }; 1027 1028 spi19: spi@88c000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0x0 0x0088c000 0x0 0x4000>; 1031 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1033 clock-names = "se"; 1034 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1035 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1036 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1037 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1038 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1039 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1040 interconnect-names = "qup-core", 1041 "qup-config", 1042 "qup-memory"; 1043 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1044 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1045 dma-names = "tx", 1046 "rx"; 1047 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1048 pinctrl-names = "default"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 1052 status = "disabled"; 1053 }; 1054 1055 uart19: serial@88c000 { 1056 compatible = "qcom,geni-uart"; 1057 reg = <0x0 0x0088c000 0x0 0x4000>; 1058 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1060 clock-names = "se"; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1062 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1063 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1064 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1065 interconnect-names = "qup-core", 1066 "qup-config"; 1067 pinctrl-0 = <&qup_uart19_default>; 1068 pinctrl-names = "default"; 1069 1070 status = "disabled"; 1071 }; 1072 1073 i2c20: i2c@890000 { 1074 compatible = "qcom,geni-i2c"; 1075 reg = <0x0 0x00890000 0x0 0x4000>; 1076 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1078 clock-names = "se"; 1079 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1080 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1081 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1082 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1083 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1084 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1085 interconnect-names = "qup-core", 1086 "qup-config", 1087 "qup-memory"; 1088 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1089 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1090 dma-names = "tx", 1091 "rx"; 1092 pinctrl-0 = <&qup_i2c20_data_clk>; 1093 pinctrl-names = "default"; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 status = "disabled"; 1098 }; 1099 1100 spi20: spi@890000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0x0 0x00890000 0x0 0x4000>; 1103 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1105 clock-names = "se"; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1107 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1108 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1109 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1110 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1111 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1112 interconnect-names = "qup-core", 1113 "qup-config", 1114 "qup-memory"; 1115 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1116 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1117 dma-names = "tx", 1118 "rx"; 1119 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1120 pinctrl-names = "default"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 1124 status = "disabled"; 1125 }; 1126 1127 i2c21: i2c@894000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0x0 0x00894000 0x0 0x4000>; 1130 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1132 clock-names = "se"; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1134 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1135 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1136 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1137 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1138 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1139 interconnect-names = "qup-core", 1140 "qup-config", 1141 "qup-memory"; 1142 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1143 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1144 dma-names = "tx", 1145 "rx"; 1146 pinctrl-0 = <&qup_i2c21_data_clk>; 1147 pinctrl-names = "default"; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 1151 status = "disabled"; 1152 }; 1153 1154 spi21: spi@894000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0x0 0x00894000 0x0 0x4000>; 1157 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1159 clock-names = "se"; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1161 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1162 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1163 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1164 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1166 interconnect-names = "qup-core", 1167 "qup-config", 1168 "qup-memory"; 1169 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1170 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1171 dma-names = "tx", 1172 "rx"; 1173 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1174 pinctrl-names = "default"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 1178 status = "disabled"; 1179 }; 1180 1181 uart21: serial@894000 { 1182 compatible = "qcom,geni-debug-uart"; 1183 reg = <0x0 0x00894000 0x0 0x4000>; 1184 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1186 clock-names = "se"; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1188 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1189 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1190 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1191 interconnect-names = "qup-core", 1192 "qup-config"; 1193 pinctrl-0 = <&qup_uart21_default>; 1194 pinctrl-names = "default"; 1195 }; 1196 1197 i2c22: i2c@898000 { 1198 compatible = "qcom,geni-i2c"; 1199 reg = <0x0 0x00898000 0x0 0x4000>; 1200 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1202 clock-names = "se"; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1204 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1205 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1206 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1207 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1208 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1209 interconnect-names = "qup-core", 1210 "qup-config", 1211 "qup-memory"; 1212 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1213 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1214 dma-names = "tx", 1215 "rx"; 1216 pinctrl-0 = <&qup_i2c22_data_clk>; 1217 pinctrl-names = "default"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 1221 status = "disabled"; 1222 }; 1223 1224 spi22: spi@898000 { 1225 compatible = "qcom,geni-spi"; 1226 reg = <0x0 0x00898000 0x0 0x4000>; 1227 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1229 clock-names = "se"; 1230 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1231 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1232 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1233 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1234 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1235 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1236 interconnect-names = "qup-core", 1237 "qup-config", 1238 "qup-memory"; 1239 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1240 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1241 dma-names = "tx", 1242 "rx"; 1243 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1244 pinctrl-names = "default"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 1248 status = "disabled"; 1249 }; 1250 1251 uart22: serial@898000 { 1252 compatible = "qcom,geni-uart"; 1253 reg = <0x0 0x00898000 0x0 0x4000>; 1254 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1256 clock-names = "se"; 1257 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1258 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1259 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1260 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1261 interconnect-names = "qup-core", 1262 "qup-config"; 1263 pinctrl-0 = <&qup_uart22_default>; 1264 pinctrl-names = "default"; 1265 1266 status = "disabled"; 1267 }; 1268 1269 i2c23: i2c@89c000 { 1270 compatible = "qcom,geni-i2c"; 1271 reg = <0x0 0x0089c000 0x0 0x4000>; 1272 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1274 clock-names = "se"; 1275 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1276 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1277 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1278 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1279 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1280 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1281 interconnect-names = "qup-core", 1282 "qup-config", 1283 "qup-memory"; 1284 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1285 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1286 dma-names = "tx", 1287 "rx"; 1288 pinctrl-0 = <&qup_i2c23_data_clk>; 1289 pinctrl-names = "default"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 1293 status = "disabled"; 1294 }; 1295 1296 spi23: spi@89c000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0x0 0x0089c000 0x0 0x4000>; 1299 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1301 clock-names = "se"; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1303 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1304 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1305 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1306 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1307 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1308 interconnect-names = "qup-core", 1309 "qup-config", 1310 "qup-memory"; 1311 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1312 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1313 dma-names = "tx", 1314 "rx"; 1315 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1316 pinctrl-names = "default"; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 1320 status = "disabled"; 1321 }; 1322 }; 1323 1324 gpi_dma1: dma-controller@a00000 { 1325 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1326 reg = <0x0 0x00a00000 0x0 0x60000>; 1327 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1343 dma-channels = <16>; 1344 dma-channel-mask = <0x3f>; 1345 #dma-cells = <3>; 1346 iommus = <&apps_smmu 0xcb6 0x0>; 1347 }; 1348 1349 qupv3_1: geniqup@ac0000 { 1350 compatible = "qcom,geni-se-qup"; 1351 reg = <0x0 0x00ac0000 0x0 0x3000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1353 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1354 clock-names = "m-ahb", 1355 "s-ahb"; 1356 iommus = <&apps_smmu 0xca3 0x0>; 1357 #address-cells = <2>; 1358 #size-cells = <2>; 1359 ranges; 1360 1361 i2c8: i2c@a80000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0x0 0x00a80000 0x0 0x4000>; 1364 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1366 clock-names = "se"; 1367 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1368 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1369 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1370 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1371 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1372 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1373 interconnect-names = "qup-core", 1374 "qup-config", 1375 "qup-memory"; 1376 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1377 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1378 dma-names = "tx", 1379 "rx"; 1380 pinctrl-0 = <&qup_i2c8_data_clk>; 1381 pinctrl-names = "default"; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 1385 status = "disabled"; 1386 }; 1387 1388 spi8: spi@a80000 { 1389 compatible = "qcom,geni-spi"; 1390 reg = <0x0 0x00a80000 0x0 0x4000>; 1391 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1393 clock-names = "se"; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1395 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1396 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1397 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1398 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1399 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1400 interconnect-names = "qup-core", 1401 "qup-config", 1402 "qup-memory"; 1403 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1404 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1405 dma-names = "tx", 1406 "rx"; 1407 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1408 pinctrl-names = "default"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 1412 status = "disabled"; 1413 }; 1414 1415 i2c9: i2c@a84000 { 1416 compatible = "qcom,geni-i2c"; 1417 reg = <0x0 0x00a84000 0x0 0x4000>; 1418 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1420 clock-names = "se"; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1422 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1423 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1424 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1425 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1426 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1427 interconnect-names = "qup-core", 1428 "qup-config", 1429 "qup-memory"; 1430 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1431 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1432 dma-names = "tx", 1433 "rx"; 1434 pinctrl-0 = <&qup_i2c9_data_clk>; 1435 pinctrl-names = "default"; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 status = "disabled"; 1440 }; 1441 1442 spi9: spi@a84000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0x0 0x00a84000 0x0 0x4000>; 1445 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1447 clock-names = "se"; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1449 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1450 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1451 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1452 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1453 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1454 interconnect-names = "qup-core", 1455 "qup-config", 1456 "qup-memory"; 1457 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1458 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1459 dma-names = "tx", 1460 "rx"; 1461 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1462 pinctrl-names = "default"; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 1466 status = "disabled"; 1467 }; 1468 1469 i2c10: i2c@a88000 { 1470 compatible = "qcom,geni-i2c"; 1471 reg = <0x0 0x00a88000 0x0 0x4000>; 1472 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1474 clock-names = "se"; 1475 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1476 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1477 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1478 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1479 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1480 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1481 interconnect-names = "qup-core", 1482 "qup-config", 1483 "qup-memory"; 1484 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1485 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1486 dma-names = "tx", 1487 "rx"; 1488 pinctrl-0 = <&qup_i2c10_data_clk>; 1489 pinctrl-names = "default"; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 1493 status = "disabled"; 1494 }; 1495 1496 spi10: spi@a88000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0x0 0x00a88000 0x0 0x4000>; 1499 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1501 clock-names = "se"; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1503 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1504 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1505 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1506 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1507 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1508 interconnect-names = "qup-core", 1509 "qup-config", 1510 "qup-memory"; 1511 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1512 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1513 dma-names = "tx", 1514 "rx"; 1515 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1516 pinctrl-names = "default"; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 1520 status = "disabled"; 1521 }; 1522 1523 i2c11: i2c@a8c000 { 1524 compatible = "qcom,geni-i2c"; 1525 reg = <0x0 0x00a8c000 0x0 0x4000>; 1526 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1527 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1528 clock-names = "se"; 1529 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1530 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1531 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1532 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1533 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1534 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1535 interconnect-names = "qup-core", 1536 "qup-config", 1537 "qup-memory"; 1538 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1539 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1540 dma-names = "tx", 1541 "rx"; 1542 pinctrl-0 = <&qup_i2c11_data_clk>; 1543 pinctrl-names = "default"; 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 1547 status = "disabled"; 1548 }; 1549 1550 spi11: spi@a8c000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0x0 0x00a8c000 0x0 0x4000>; 1553 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1555 clock-names = "se"; 1556 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1557 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1558 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1559 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1560 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1561 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1562 interconnect-names = "qup-core", 1563 "qup-config", 1564 "qup-memory"; 1565 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1566 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1567 dma-names = "tx", 1568 "rx"; 1569 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1570 pinctrl-names = "default"; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 status = "disabled"; 1575 }; 1576 1577 i2c12: i2c@a90000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0x0 0x00a90000 0x0 0x4000>; 1580 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1582 clock-names = "se"; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1584 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1585 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1586 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1587 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1588 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1589 interconnect-names = "qup-core", 1590 "qup-config", 1591 "qup-memory"; 1592 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1593 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1594 dma-names = "tx", 1595 "rx"; 1596 pinctrl-0 = <&qup_i2c12_data_clk>; 1597 pinctrl-names = "default"; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 1601 status = "disabled"; 1602 }; 1603 1604 spi12: spi@a90000 { 1605 compatible = "qcom,geni-spi"; 1606 reg = <0x0 0x00a90000 0x0 0x4000>; 1607 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1608 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1609 clock-names = "se"; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1611 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1612 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1613 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1614 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1616 interconnect-names = "qup-core", 1617 "qup-config", 1618 "qup-memory"; 1619 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1620 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1621 dma-names = "tx", 1622 "rx"; 1623 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1624 pinctrl-names = "default"; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 status = "disabled"; 1629 }; 1630 1631 i2c13: i2c@a94000 { 1632 compatible = "qcom,geni-i2c"; 1633 reg = <0x0 0x00a94000 0x0 0x4000>; 1634 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1636 clock-names = "se"; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1638 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1639 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1640 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1641 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1643 interconnect-names = "qup-core", 1644 "qup-config", 1645 "qup-memory"; 1646 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1647 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1648 dma-names = "tx", 1649 "rx"; 1650 pinctrl-0 = <&qup_i2c13_data_clk>; 1651 pinctrl-names = "default"; 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 1655 status = "disabled"; 1656 }; 1657 1658 spi13: spi@a94000 { 1659 compatible = "qcom,geni-spi"; 1660 reg = <0x0 0x00a94000 0x0 0x4000>; 1661 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1663 clock-names = "se"; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1665 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1666 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1667 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1668 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1669 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1670 interconnect-names = "qup-core", 1671 "qup-config", 1672 "qup-memory"; 1673 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1674 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1675 dma-names = "tx", 1676 "rx"; 1677 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1678 pinctrl-names = "default"; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 1682 status = "disabled"; 1683 }; 1684 1685 i2c14: i2c@a98000 { 1686 compatible = "qcom,geni-i2c"; 1687 reg = <0x0 0x00a98000 0x0 0x4000>; 1688 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1689 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1690 clock-names = "se"; 1691 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1692 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1693 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1694 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1695 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1696 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1697 interconnect-names = "qup-core", 1698 "qup-config", 1699 "qup-memory"; 1700 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1701 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1702 dma-names = "tx", 1703 "rx"; 1704 pinctrl-0 = <&qup_i2c14_data_clk>; 1705 pinctrl-names = "default"; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 1709 status = "disabled"; 1710 }; 1711 1712 spi14: spi@a98000 { 1713 compatible = "qcom,geni-spi"; 1714 reg = <0x0 0x00a98000 0x0 0x4000>; 1715 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1717 clock-names = "se"; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1719 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1720 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1721 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1722 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1723 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1724 interconnect-names = "qup-core", 1725 "qup-config", 1726 "qup-memory"; 1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1728 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1729 dma-names = "tx", 1730 "rx"; 1731 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1732 pinctrl-names = "default"; 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 status = "disabled"; 1737 }; 1738 1739 uart14: serial@a98000 { 1740 compatible = "qcom,geni-uart"; 1741 reg = <0x0 0x00a98000 0x0 0x4000>; 1742 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1743 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1744 clock-names = "se"; 1745 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1746 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1747 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1748 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1749 interconnect-names = "qup-core", 1750 "qup-config"; 1751 pinctrl-0 = <&qup_uart14_default>; 1752 pinctrl-names = "default"; 1753 1754 status = "disabled"; 1755 }; 1756 1757 i2c15: i2c@a9c000 { 1758 compatible = "qcom,geni-i2c"; 1759 reg = <0x0 0x00a9c000 0x0 0x4000>; 1760 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1762 clock-names = "se"; 1763 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1764 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1765 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1766 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1767 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1768 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1769 interconnect-names = "qup-core", 1770 "qup-config", 1771 "qup-memory"; 1772 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1773 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1774 dma-names = "tx", 1775 "rx"; 1776 pinctrl-0 = <&qup_i2c15_data_clk>; 1777 pinctrl-names = "default"; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 1781 status = "disabled"; 1782 }; 1783 1784 spi15: spi@a9c000 { 1785 compatible = "qcom,geni-spi"; 1786 reg = <0x0 0x00a9c000 0x0 0x4000>; 1787 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1789 clock-names = "se"; 1790 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1791 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1792 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1793 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1794 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1795 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1796 interconnect-names = "qup-core", 1797 "qup-config", 1798 "qup-memory"; 1799 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1800 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1801 dma-names = "tx", 1802 "rx"; 1803 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1804 pinctrl-names = "default"; 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 1808 status = "disabled"; 1809 }; 1810 }; 1811 1812 gpi_dma0: dma-controller@b00000 { 1813 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1814 reg = <0x0 0x00b00000 0x0 0x60000>; 1815 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1831 dma-channels = <16>; 1832 dma-channel-mask = <0x3f>; 1833 #dma-cells = <3>; 1834 iommus = <&apps_smmu 0xd36 0x0>; 1835 }; 1836 1837 qupv3_0: geniqup@bc0000 { 1838 compatible = "qcom,geni-se-qup"; 1839 reg = <0x0 0x00bc0000 0x0 0x3000>; 1840 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1841 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1842 clock-names = "m-ahb", 1843 "s-ahb"; 1844 iommus = <&apps_smmu 0xd23 0x0>; 1845 #address-cells = <2>; 1846 #size-cells = <2>; 1847 ranges; 1848 1849 i2c0: i2c@b80000 { 1850 compatible = "qcom,geni-i2c"; 1851 reg = <0x0 0x00b80000 0x0 0x4000>; 1852 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1854 clock-names = "se"; 1855 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1856 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1857 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1858 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1859 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1860 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1861 interconnect-names = "qup-core", 1862 "qup-config", 1863 "qup-memory"; 1864 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1865 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1866 dma-names = "tx", 1867 "rx"; 1868 pinctrl-0 = <&qup_i2c0_data_clk>; 1869 pinctrl-names = "default"; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 1873 status = "disabled"; 1874 }; 1875 1876 spi0: spi@b80000 { 1877 compatible = "qcom,geni-spi"; 1878 reg = <0x0 0x00b80000 0x0 0x4000>; 1879 interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>; 1880 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1881 clock-names = "se"; 1882 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1883 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1884 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1885 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1886 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1888 interconnect-names = "qup-core", 1889 "qup-config", 1890 "qup-memory"; 1891 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1892 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1893 dma-names = "tx", 1894 "rx"; 1895 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1896 pinctrl-names = "default"; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 1900 status = "disabled"; 1901 }; 1902 1903 i2c1: i2c@b84000 { 1904 compatible = "qcom,geni-i2c"; 1905 reg = <0x0 0x00b84000 0x0 0x4000>; 1906 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1908 clock-names = "se"; 1909 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1910 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1911 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1912 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1913 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1914 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1915 interconnect-names = "qup-core", 1916 "qup-config", 1917 "qup-memory"; 1918 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1919 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1920 dma-names = "tx", 1921 "rx"; 1922 pinctrl-0 = <&qup_i2c1_data_clk>; 1923 pinctrl-names = "default"; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 1927 status = "disabled"; 1928 }; 1929 1930 spi1: spi@b84000 { 1931 compatible = "qcom,geni-spi"; 1932 reg = <0x0 0x00b84000 0x0 0x4000>; 1933 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1934 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1935 clock-names = "se"; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1937 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1938 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1939 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1940 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1941 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1942 interconnect-names = "qup-core", 1943 "qup-config", 1944 "qup-memory"; 1945 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1946 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1947 dma-names = "tx", 1948 "rx"; 1949 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1950 pinctrl-names = "default"; 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 1954 status = "disabled"; 1955 }; 1956 1957 i2c2: i2c@b88000 { 1958 compatible = "qcom,geni-i2c"; 1959 reg = <0x0 0x00b88000 0x0 0x4000>; 1960 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1961 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1962 clock-names = "se"; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1964 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1965 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1966 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1967 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1968 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1969 interconnect-names = "qup-core", 1970 "qup-config", 1971 "qup-memory"; 1972 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1973 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1974 dma-names = "tx", 1975 "rx"; 1976 pinctrl-0 = <&qup_i2c2_data_clk>; 1977 pinctrl-names = "default"; 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 1981 status = "disabled"; 1982 }; 1983 1984 spi2: spi@b88000 { 1985 compatible = "qcom,geni-spi"; 1986 reg = <0x0 0x00b88000 0x0 0x4000>; 1987 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1988 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1989 clock-names = "se"; 1990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1992 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1994 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1996 interconnect-names = "qup-core", 1997 "qup-config", 1998 "qup-memory"; 1999 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2000 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2001 dma-names = "tx", 2002 "rx"; 2003 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2004 pinctrl-names = "default"; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 2008 status = "disabled"; 2009 }; 2010 2011 uart2: serial@b88000 { 2012 compatible = "qcom,geni-uart"; 2013 reg = <0x0 0x00b88000 0x0 0x4000>; 2014 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 2015 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2016 clock-names = "se"; 2017 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2018 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2019 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2020 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2021 interconnect-names = "qup-core", 2022 "qup-config"; 2023 pinctrl-0 = <&qup_uart2_default>; 2024 pinctrl-names = "default"; 2025 2026 status = "disabled"; 2027 }; 2028 2029 i2c3: i2c@b8c000 { 2030 compatible = "qcom,geni-i2c"; 2031 reg = <0x0 0x00b8c000 0x0 0x4000>; 2032 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2033 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2034 clock-names = "se"; 2035 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2036 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2037 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2038 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2039 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2040 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2041 interconnect-names = "qup-core", 2042 "qup-config", 2043 "qup-memory"; 2044 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2045 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2046 dma-names = "tx", 2047 "rx"; 2048 pinctrl-0 = <&qup_i2c3_data_clk>; 2049 pinctrl-names = "default"; 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 2053 status = "disabled"; 2054 }; 2055 2056 spi3: spi@b8c000 { 2057 compatible = "qcom,geni-spi"; 2058 reg = <0x0 0x00b8c000 0x0 0x4000>; 2059 interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>; 2060 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2061 clock-names = "se"; 2062 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2063 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2064 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2065 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2066 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2067 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2068 interconnect-names = "qup-core", 2069 "qup-config", 2070 "qup-memory"; 2071 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2072 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2073 dma-names = "tx", 2074 "rx"; 2075 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2076 pinctrl-names = "default"; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 2080 status = "disabled"; 2081 }; 2082 2083 i2c4: i2c@b90000 { 2084 compatible = "qcom,geni-i2c"; 2085 reg = <0x0 0x00b90000 0x0 0x4000>; 2086 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2087 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2088 clock-names = "se"; 2089 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2090 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2091 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2092 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2093 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2095 interconnect-names = "qup-core", 2096 "qup-config", 2097 "qup-memory"; 2098 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2099 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2100 dma-names = "tx", 2101 "rx"; 2102 pinctrl-0 = <&qup_i2c4_data_clk>; 2103 pinctrl-names = "default"; 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 status = "disabled"; 2108 }; 2109 2110 spi4: spi@b90000 { 2111 compatible = "qcom,geni-spi"; 2112 reg = <0x0 0x00b90000 0x0 0x4000>; 2113 interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>; 2114 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2115 clock-names = "se"; 2116 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2117 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2118 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2119 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2120 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2122 interconnect-names = "qup-core", 2123 "qup-config", 2124 "qup-memory"; 2125 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2126 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2127 dma-names = "tx", 2128 "rx"; 2129 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2130 pinctrl-names = "default"; 2131 #address-cells = <1>; 2132 #size-cells = <0>; 2133 2134 status = "disabled"; 2135 }; 2136 2137 i2c5: i2c@b94000 { 2138 compatible = "qcom,geni-i2c"; 2139 reg = <0x0 0x00b94000 0x0 0x4000>; 2140 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2141 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2142 clock-names = "se"; 2143 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2144 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2145 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2146 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2147 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2148 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2149 interconnect-names = "qup-core", 2150 "qup-config", 2151 "qup-memory"; 2152 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2153 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2154 dma-names = "tx", 2155 "rx"; 2156 pinctrl-0 = <&qup_i2c5_data_clk>; 2157 pinctrl-names = "default"; 2158 #address-cells = <1>; 2159 #size-cells = <0>; 2160 2161 status = "disabled"; 2162 }; 2163 2164 spi5: spi@b94000 { 2165 compatible = "qcom,geni-spi"; 2166 reg = <0x0 0x00b94000 0x0 0x4000>; 2167 interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>; 2168 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2169 clock-names = "se"; 2170 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2171 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2172 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2173 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2174 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2176 interconnect-names = "qup-core", 2177 "qup-config", 2178 "qup-memory"; 2179 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2180 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2181 dma-names = "tx", 2182 "rx"; 2183 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2184 pinctrl-names = "default"; 2185 #address-cells = <1>; 2186 #size-cells = <0>; 2187 2188 status = "disabled"; 2189 }; 2190 2191 i2c6: i2c@b98000 { 2192 compatible = "qcom,geni-i2c"; 2193 reg = <0x0 0x00b98000 0x0 0x4000>; 2194 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2195 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2196 clock-names = "se"; 2197 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2198 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2199 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2200 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2201 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2203 interconnect-names = "qup-core", 2204 "qup-config", 2205 "qup-memory"; 2206 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2207 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2208 dma-names = "tx", 2209 "rx"; 2210 pinctrl-0 = <&qup_i2c6_data_clk>; 2211 pinctrl-names = "default"; 2212 #address-cells = <1>; 2213 #size-cells = <0>; 2214 2215 status = "disabled"; 2216 }; 2217 2218 spi6: spi@b98000 { 2219 compatible = "qcom,geni-spi"; 2220 reg = <0x0 0x00b98000 0x0 0x4000>; 2221 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2222 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2223 clock-names = "se"; 2224 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2225 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2226 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2227 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2228 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2230 interconnect-names = "qup-core", 2231 "qup-config", 2232 "qup-memory"; 2233 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2234 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2235 dma-names = "tx", 2236 "rx"; 2237 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2238 pinctrl-names = "default"; 2239 #address-cells = <1>; 2240 #size-cells = <0>; 2241 2242 status = "disabled"; 2243 }; 2244 2245 i2c7: i2c@b9c000 { 2246 compatible = "qcom,geni-i2c"; 2247 reg = <0x0 0x00b9c000 0x0 0x4000>; 2248 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2249 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2250 clock-names = "se"; 2251 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2252 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2253 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2254 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2255 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2256 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2257 interconnect-names = "qup-core", 2258 "qup-config", 2259 "qup-memory"; 2260 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2261 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2262 dma-names = "tx", 2263 "rx"; 2264 pinctrl-0 = <&qup_i2c7_data_clk>; 2265 pinctrl-names = "default"; 2266 #address-cells = <1>; 2267 #size-cells = <0>; 2268 2269 status = "disabled"; 2270 }; 2271 2272 spi7: spi@b9c000 { 2273 compatible = "qcom,geni-spi"; 2274 reg = <0x0 0x00b9c000 0x0 0x4000>; 2275 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2276 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2277 clock-names = "se"; 2278 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2279 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2280 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2281 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2282 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2283 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2284 interconnect-names = "qup-core", 2285 "qup-config", 2286 "qup-memory"; 2287 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2288 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2289 dma-names = "tx", 2290 "rx"; 2291 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2292 pinctrl-names = "default"; 2293 #address-cells = <1>; 2294 #size-cells = <0>; 2295 2296 status = "disabled"; 2297 }; 2298 }; 2299 2300 usb_hs_phy: phy@fa0000 { 2301 compatible = "qcom,glymur-m31-eusb2-phy", 2302 "qcom,sm8750-m31-eusb2-phy"; 2303 reg = <0x0 0x00fa0000 0x0 0x154>; 2304 #phy-cells = <0>; 2305 2306 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2307 clock-names = "ref"; 2308 2309 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2310 2311 status = "disabled"; 2312 }; 2313 2314 usb_mp_hsphy0: phy@fa1000 { 2315 compatible = "qcom,glymur-m31-eusb2-phy", 2316 "qcom,sm8750-m31-eusb2-phy"; 2317 2318 reg = <0x0 0x00fa1000 0x0 0x29c>; 2319 #phy-cells = <0>; 2320 2321 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2322 clock-names = "ref"; 2323 2324 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2325 2326 status = "disabled"; 2327 }; 2328 2329 usb_mp_hsphy1: phy@fa2000 { 2330 compatible = "qcom,glymur-m31-eusb2-phy", 2331 "qcom,sm8750-m31-eusb2-phy"; 2332 2333 reg = <0x0 0x00fa2000 0x0 0x29c>; 2334 #phy-cells = <0>; 2335 2336 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2337 clock-names = "ref"; 2338 2339 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2340 2341 status = "disabled"; 2342 }; 2343 2344 usb_mp_qmpphy0: phy@fa3000 { 2345 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2346 reg = <0x0 0x00fa3000 0x0 0x2000>; 2347 2348 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2349 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2350 <&rpmhcc RPMH_CXO_CLK>, 2351 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2352 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2353 clock-names = "aux", 2354 "clkref", 2355 "ref", 2356 "com_aux", 2357 "pipe"; 2358 2359 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2360 2361 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2362 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2363 reset-names = "phy", 2364 "phy_phy"; 2365 2366 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2367 #clock-cells = <0>; 2368 #phy-cells = <0>; 2369 2370 status = "disabled"; 2371 }; 2372 2373 usb_mp_qmpphy1: phy@fa5000 { 2374 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2375 reg = <0x0 0x00fa5000 0x0 0x2000>; 2376 2377 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2378 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2379 <&rpmhcc RPMH_CXO_CLK>, 2380 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2381 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2382 clock-names = "aux", 2383 "clkref", 2384 "ref", 2385 "com_aux", 2386 "pipe"; 2387 2388 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2389 2390 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2391 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2392 reset-names = "phy", 2393 "phy_phy"; 2394 2395 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2396 2397 #clock-cells = <0>; 2398 #phy-cells = <0>; 2399 2400 status = "disabled"; 2401 }; 2402 2403 mdss_dp3_phy: phy@faac00 { 2404 compatible = "qcom,glymur-dp-phy"; 2405 reg = <0x0 0x00faac00 0x0 0x1d0>, 2406 <0x0 0x00faa400 0x0 0x128>, 2407 <0x0 0x00faa800 0x0 0x128>, 2408 <0x0 0x00faa000 0x0 0x358>; 2409 2410 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 2411 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2412 <&tcsr TCSR_EDP_CLKREF_EN>; 2413 clock-names = "aux", 2414 "cfg_ahb", 2415 "ref"; 2416 2417 power-domains = <&rpmhpd RPMHPD_MX>; 2418 2419 #clock-cells = <1>; 2420 #phy-cells = <0>; 2421 2422 status = "disabled"; 2423 }; 2424 2425 usb_0_hsphy: phy@fd3000 { 2426 compatible = "qcom,glymur-m31-eusb2-phy", 2427 "qcom,sm8750-m31-eusb2-phy"; 2428 2429 reg = <0x0 0x00fd3000 0x0 0x29c>; 2430 #phy-cells = <0>; 2431 2432 clocks = <&rpmhcc RPMH_CXO_CLK>; 2433 clock-names = "ref"; 2434 2435 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2436 2437 status = "disabled"; 2438 }; 2439 2440 usb_0_qmpphy: phy@fd5000 { 2441 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2442 reg = <0x0 0x00fd5000 0x0 0x8000>; 2443 2444 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2445 <&rpmhcc RPMH_CXO_CLK>, 2446 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2447 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2448 clock-names = "aux", 2449 "ref", 2450 "com_aux", 2451 "usb3_pipe"; 2452 2453 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2454 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2455 2456 reset-names = "phy", 2457 "common"; 2458 2459 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2460 2461 #clock-cells = <1>; 2462 #phy-cells = <1>; 2463 2464 mode-switch; 2465 orientation-switch; 2466 2467 status = "disabled"; 2468 2469 ports { 2470 #address-cells = <1>; 2471 #size-cells = <0>; 2472 2473 port@0 { 2474 reg = <0>; 2475 2476 usb_0_qmpphy_out: endpoint { 2477 }; 2478 }; 2479 2480 port@1 { 2481 reg = <1>; 2482 2483 usb_0_qmpphy_usb_ss_in: endpoint { 2484 remote-endpoint = <&usb_0_dwc3_ss>; 2485 }; 2486 }; 2487 2488 port@2 { 2489 reg = <2>; 2490 2491 usb_dp_qmpphy_dp_in: endpoint { 2492 remote-endpoint = <&mdss_dp0_out>; 2493 }; 2494 }; 2495 }; 2496 }; 2497 2498 usb_1_hsphy: phy@fdd000 { 2499 compatible = "qcom,glymur-m31-eusb2-phy", 2500 "qcom,sm8750-m31-eusb2-phy"; 2501 2502 reg = <0x0 0x00fdd000 0x0 0x29c>; 2503 #phy-cells = <0>; 2504 2505 clocks = <&rpmhcc RPMH_CXO_CLK>; 2506 clock-names = "ref"; 2507 2508 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2509 2510 status = "disabled"; 2511 }; 2512 2513 usb_1_qmpphy: phy@fde000 { 2514 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2515 reg = <0x0 0x00fde000 0x0 0x8000>; 2516 2517 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2518 <&rpmhcc RPMH_CXO_CLK>, 2519 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2520 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, 2521 <&tcsr TCSR_USB4_1_CLKREF_EN>; 2522 clock-names = "aux", 2523 "ref", 2524 "com_aux", 2525 "usb3_pipe", 2526 "clkref"; 2527 2528 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2529 2530 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2531 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2532 reset-names = "phy", 2533 "common"; 2534 2535 #clock-cells = <1>; 2536 #phy-cells = <1>; 2537 2538 mode-switch; 2539 orientation-switch; 2540 2541 status = "disabled"; 2542 2543 ports { 2544 #address-cells = <1>; 2545 #size-cells = <0>; 2546 2547 port@0 { 2548 reg = <0>; 2549 2550 usb_1_qmpphy_out: endpoint { 2551 }; 2552 }; 2553 2554 port@1 { 2555 reg = <1>; 2556 2557 usb_1_qmpphy_usb_ss_in: endpoint { 2558 remote-endpoint = <&usb_1_dwc3_ss>; 2559 }; 2560 }; 2561 2562 port@2 { 2563 reg = <2>; 2564 2565 usb_1_qmpphy_dp_in: endpoint { 2566 remote-endpoint = <&mdss_dp1_out>; 2567 }; 2568 }; 2569 }; 2570 }; 2571 2572 2573 /* cluster0 */ 2574 bwmon_cluster0: pmu@100c400 { 2575 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2576 reg = <0x0 0x0100c400 0x0 0x600>; 2577 2578 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2579 2580 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2582 2583 operating-points-v2 = <&cpu_bwmon_opp_table>; 2584 2585 cpu_bwmon_opp_table: opp-table { 2586 compatible = "operating-points-v2"; 2587 2588 opp-0 { 2589 opp-peak-kBps = <800000>; 2590 }; 2591 2592 opp-1 { 2593 opp-peak-kBps = <2188800>; 2594 }; 2595 2596 opp-2 { 2597 opp-peak-kBps = <5414400>; 2598 }; 2599 2600 opp-3 { 2601 opp-peak-kBps = <6220800>; 2602 }; 2603 2604 opp-4 { 2605 opp-peak-kBps = <6835200>; 2606 }; 2607 2608 opp-5 { 2609 opp-peak-kBps = <8371200>; 2610 }; 2611 2612 opp-6 { 2613 opp-peak-kBps = <10944000>; 2614 }; 2615 2616 opp-7 { 2617 opp-peak-kBps = <12748800>; 2618 }; 2619 2620 opp-8 { 2621 opp-peak-kBps = <14745600>; 2622 }; 2623 2624 opp-9 { 2625 opp-peak-kBps = <16896000>; 2626 }; 2627 2628 opp-10 { 2629 opp-peak-kBps = <19046400>; 2630 }; 2631 2632 opp-11 { 2633 opp-peak-kBps = <21332000>; 2634 }; 2635 }; 2636 }; 2637 2638 /* cluster1 */ 2639 bwmon_cluster1: pmu@100d400 { 2640 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2641 reg = <0x0 0x0100d400 0x0 0x600>; 2642 2643 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2644 2645 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2646 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2647 2648 operating-points-v2 = <&cpu_bwmon_opp_table>; 2649 }; 2650 2651 /* cluster2 */ 2652 bwmon_cluster2: pmu@100e400 { 2653 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2654 reg = <0x0 0x0100e400 0x0 0x600>; 2655 2656 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2657 2658 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2660 2661 operating-points-v2 = <&cpu_bwmon_opp_table>; 2662 }; 2663 cnoc_main: interconnect@1500000 { 2664 compatible = "qcom,glymur-cnoc-main"; 2665 reg = <0x0 0x01500000 0x0 0x17080>; 2666 qcom,bcm-voters = <&apps_bcm_voter>; 2667 #interconnect-cells = <2>; 2668 }; 2669 2670 config_noc: interconnect@1600000 { 2671 compatible = "qcom,glymur-cnoc-cfg"; 2672 reg = <0x0 0x01600000 0x0 0x6600>; 2673 qcom,bcm-voters = <&apps_bcm_voter>; 2674 #interconnect-cells = <2>; 2675 }; 2676 2677 system_noc: interconnect@1680000 { 2678 compatible = "qcom,glymur-system-noc"; 2679 reg = <0x0 0x01680000 0x0 0x1c080>; 2680 qcom,bcm-voters = <&apps_bcm_voter>; 2681 #interconnect-cells = <2>; 2682 }; 2683 2684 pcie_west_anoc: interconnect@16c0000 { 2685 compatible = "qcom,glymur-pcie-west-anoc"; 2686 reg = <0x0 0x016c0000 0x0 0xf580>; 2687 qcom,bcm-voters = <&apps_bcm_voter>; 2688 #interconnect-cells = <2>; 2689 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2690 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2691 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2692 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2693 }; 2694 2695 pcie_east_anoc: interconnect@16d0000 { 2696 compatible = "qcom,glymur-pcie-east-anoc"; 2697 reg = <0x0 0x016d0000 0x0 0xf300>; 2698 qcom,bcm-voters = <&apps_bcm_voter>; 2699 #interconnect-cells = <2>; 2700 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2701 }; 2702 2703 aggre1_noc: interconnect@16e0000 { 2704 compatible = "qcom,glymur-aggre1-noc"; 2705 reg = <0x0 0x016e0000 0x0 0x14400>; 2706 qcom,bcm-voters = <&apps_bcm_voter>; 2707 #interconnect-cells = <2>; 2708 }; 2709 2710 aggre2_noc: interconnect@1720000 { 2711 compatible = "qcom,glymur-aggre2-noc"; 2712 reg = <0x0 0x01720000 0x0 0x14400>; 2713 qcom,bcm-voters = <&apps_bcm_voter>; 2714 #interconnect-cells = <2>; 2715 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2716 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2717 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2718 }; 2719 2720 aggre3_noc: interconnect@1700000 { 2721 compatible = "qcom,glymur-aggre3-noc"; 2722 reg = <0x0 0x01700000 0x0 0x1d400>; 2723 qcom,bcm-voters = <&apps_bcm_voter>; 2724 #interconnect-cells = <2>; 2725 }; 2726 2727 aggre4_noc: interconnect@1740000 { 2728 compatible = "qcom,glymur-aggre4-noc"; 2729 reg = <0x0 0x01740000 0x0 0x14400>; 2730 qcom,bcm-voters = <&apps_bcm_voter>; 2731 #interconnect-cells = <2>; 2732 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2733 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2734 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2735 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2736 }; 2737 2738 mmss_noc: interconnect@1780000 { 2739 compatible = "qcom,glymur-mmss-noc"; 2740 reg = <0x0 0x01780000 0x0 0x5b800>; 2741 qcom,bcm-voters = <&apps_bcm_voter>; 2742 #interconnect-cells = <2>; 2743 }; 2744 2745 pcie_east_slv_noc: interconnect@1900000 { 2746 compatible = "qcom,glymur-pcie-east-slv-noc"; 2747 reg = <0x0 0x01900000 0x0 0xe080>; 2748 qcom,bcm-voters = <&apps_bcm_voter>; 2749 #interconnect-cells = <2>; 2750 }; 2751 2752 pcie_west_slv_noc: interconnect@1920000 { 2753 compatible = "qcom,glymur-pcie-west-slv-noc"; 2754 reg = <0x0 0x01920000 0x0 0xf180>; 2755 qcom,bcm-voters = <&apps_bcm_voter>; 2756 #interconnect-cells = <2>; 2757 }; 2758 2759 pcie4: pci@1bf0000 { 2760 device_type = "pci"; 2761 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2762 reg = <0x0 0x01bf0000 0x0 0x3000>, 2763 <0x0 0x78000000 0x0 0xf20>, 2764 <0x0 0x78000f40 0x0 0xa8>, 2765 <0x0 0x78001000 0x0 0x4000>, 2766 <0x0 0x78005000 0x0 0x100000>, 2767 <0x0 0x01bf3000 0x0 0x1000>; 2768 reg-names = "parf", 2769 "dbi", 2770 "elbi", 2771 "atu", 2772 "config", 2773 "mhi"; 2774 #address-cells = <3>; 2775 #size-cells = <2>; 2776 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2777 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2778 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2779 bus-range = <0x00 0xff>; 2780 2781 dma-coherent; 2782 2783 linux,pci-domain = <4>; 2784 num-lanes = <2>; 2785 2786 operating-points-v2 = <&pcie4_opp_table>; 2787 2788 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2789 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2790 2791 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2799 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2800 interrupt-names = "msi0", 2801 "msi1", 2802 "msi2", 2803 "msi3", 2804 "msi4", 2805 "msi5", 2806 "msi6", 2807 "msi7", 2808 "global"; 2809 2810 #interrupt-cells = <1>; 2811 interrupt-map-mask = <0 0 0 0x7>; 2812 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 2813 <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 2814 <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 2815 <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; 2816 2817 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2818 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2819 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2820 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2821 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2822 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2823 clock-names = "aux", 2824 "cfg", 2825 "bus_master", 2826 "bus_slave", 2827 "slave_q2a", 2828 "noc_aggr"; 2829 2830 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2831 assigned-clock-rates = <19200000>; 2832 2833 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2834 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2835 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2836 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2837 interconnect-names = "pcie-mem", 2838 "cpu-pcie"; 2839 2840 resets = <&gcc GCC_PCIE_4_BCR>, 2841 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2842 reset-names = "pci", 2843 "link_down"; 2844 2845 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2846 2847 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2848 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2849 2850 status = "disabled"; 2851 2852 pcie4_opp_table: opp-table { 2853 compatible = "operating-points-v2"; 2854 2855 /* GEN 1 x1 */ 2856 opp-2500000-1 { 2857 opp-hz = /bits/ 64 <2500000>; 2858 required-opps = <&rpmhpd_opp_low_svs>; 2859 opp-peak-kBps = <250000 1>; 2860 opp-level = <1>; 2861 }; 2862 2863 /* GEN 1 x2 */ 2864 opp-5000000-1 { 2865 opp-hz = /bits/ 64 <5000000>; 2866 required-opps = <&rpmhpd_opp_low_svs>; 2867 opp-peak-kBps = <500000 1>; 2868 opp-level = <1>; 2869 }; 2870 2871 /* GEN 2 x1 */ 2872 opp-5000000-2 { 2873 opp-hz = /bits/ 64 <5000000>; 2874 required-opps = <&rpmhpd_opp_low_svs>; 2875 opp-peak-kBps = <500000 1>; 2876 opp-level = <2>; 2877 }; 2878 2879 /* GEN 2 x2 */ 2880 opp-10000000-2 { 2881 opp-hz = /bits/ 64 <10000000>; 2882 required-opps = <&rpmhpd_opp_low_svs>; 2883 opp-peak-kBps = <1000000 1>; 2884 opp-level = <2>; 2885 }; 2886 2887 /* GEN 3 x1 */ 2888 opp-8000000-3 { 2889 opp-hz = /bits/ 64 <8000000>; 2890 required-opps = <&rpmhpd_opp_low_svs>; 2891 opp-peak-kBps = <984500 1>; 2892 opp-level = <3>; 2893 }; 2894 2895 /* GEN 3 x2 */ 2896 opp-16000000-3 { 2897 opp-hz = /bits/ 64 <16000000>; 2898 required-opps = <&rpmhpd_opp_low_svs>; 2899 opp-peak-kBps = <1969000 1>; 2900 opp-level = <3>; 2901 }; 2902 2903 /* GEN 4 x1 */ 2904 opp-16000000-4 { 2905 opp-hz = /bits/ 64 <16000000>; 2906 required-opps = <&rpmhpd_opp_low_svs>; 2907 opp-peak-kBps = <1969000 1>; 2908 opp-level = <4>; 2909 }; 2910 2911 /* GEN 4 x2 */ 2912 opp-32000000-4 { 2913 opp-hz = /bits/ 64 <32000000>; 2914 required-opps = <&rpmhpd_opp_low_svs>; 2915 opp-peak-kBps = <3938000 1>; 2916 opp-level = <4>; 2917 }; 2918 2919 }; 2920 2921 pcie4_port0: pcie@0 { 2922 device_type = "pci"; 2923 reg = <0x0 0x0 0x0 0x0 0x0>; 2924 bus-range = <0x01 0xff>; 2925 2926 phys = <&pcie4_phy>; 2927 2928 #address-cells = <3>; 2929 #size-cells = <2>; 2930 ranges; 2931 }; 2932 }; 2933 2934 pcie4_phy: phy@1bf6000 { 2935 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 2936 reg = <0x0 0x01bf6000 0x0 0x2000>; 2937 2938 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 2939 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2940 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 2941 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2942 <&gcc GCC_PCIE_4_PIPE_CLK>, 2943 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 2944 clock-names = "aux", 2945 "cfg_ahb", 2946 "ref", 2947 "rchng", 2948 "pipe", 2949 "pipediv2"; 2950 2951 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 2952 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 2953 reset-names = "phy", 2954 "phy_nocsr"; 2955 2956 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2957 assigned-clock-rates = <100000000>; 2958 2959 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2960 2961 #clock-cells = <0>; 2962 clock-output-names = "pcie4_pipe_clk"; 2963 2964 #phy-cells = <0>; 2965 2966 status = "disabled"; 2967 }; 2968 2969 pcie5: pci@1b40000 { 2970 device_type = "pci"; 2971 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2972 reg = <0x0 0x01b40000 0x0 0x3000>, 2973 <0x0 0x7a000000 0x0 0xf20>, 2974 <0x0 0x7a000f40 0x0 0xa8>, 2975 <0x0 0x7a001000 0x0 0x4000>, 2976 <0x0 0x7a100000 0x0 0x100000>, 2977 <0x0 0x01b43000 0x0 0x1000>; 2978 reg-names = "parf", 2979 "dbi", 2980 "elbi", 2981 "atu", 2982 "config", 2983 "mhi"; 2984 #address-cells = <3>; 2985 #size-cells = <2>; 2986 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 2987 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 2988 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 2989 bus-range = <0x00 0xff>; 2990 2991 dma-coherent; 2992 2993 linux,pci-domain = <5>; 2994 num-lanes = <4>; 2995 2996 operating-points-v2 = <&pcie5_opp_table>; 2997 2998 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 2999 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 3000 3001 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 3002 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 3003 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 3004 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 3005 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 3006 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 3008 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 3009 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 3010 interrupt-names = "msi0", 3011 "msi1", 3012 "msi2", 3013 "msi3", 3014 "msi4", 3015 "msi5", 3016 "msi6", 3017 "msi7", 3018 "global"; 3019 3020 #interrupt-cells = <1>; 3021 interrupt-map-mask = <0 0 0 0x7>; 3022 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 3023 <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 3024 <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 3025 <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; 3026 3027 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3028 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3029 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3030 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3031 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3032 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 3033 clock-names = "aux", 3034 "cfg", 3035 "bus_master", 3036 "bus_slave", 3037 "slave_q2a", 3038 "noc_aggr"; 3039 3040 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3041 assigned-clock-rates = <19200000>; 3042 3043 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3044 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3045 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3046 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3047 interconnect-names = "pcie-mem", 3048 "cpu-pcie"; 3049 3050 resets = <&gcc GCC_PCIE_5_BCR>, 3051 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3052 reset-names = "pci", 3053 "link_down"; 3054 3055 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3056 3057 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3058 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3059 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3060 3061 status = "disabled"; 3062 3063 pcie5_opp_table: opp-table { 3064 compatible = "operating-points-v2"; 3065 3066 /* GEN 1 x1 */ 3067 opp-2500000-1 { 3068 opp-hz = /bits/ 64 <2500000>; 3069 required-opps = <&rpmhpd_opp_low_svs>; 3070 opp-peak-kBps = <250000 1>; 3071 opp-level = <1>; 3072 }; 3073 3074 /* GEN 1 x2 */ 3075 opp-5000000-1 { 3076 opp-hz = /bits/ 64 <5000000>; 3077 required-opps = <&rpmhpd_opp_low_svs>; 3078 opp-peak-kBps = <500000 1>; 3079 opp-level = <1>; 3080 }; 3081 3082 /* GEN 1 x4 */ 3083 opp-10000000-1 { 3084 opp-hz = /bits/ 64 <10000000>; 3085 required-opps = <&rpmhpd_opp_low_svs>; 3086 opp-peak-kBps = <1000000 1>; 3087 opp-level = <1>; 3088 }; 3089 3090 /* GEN 2 x1 */ 3091 opp-5000000-2 { 3092 opp-hz = /bits/ 64 <5000000>; 3093 required-opps = <&rpmhpd_opp_low_svs>; 3094 opp-peak-kBps = <500000 1>; 3095 opp-level = <2>; 3096 }; 3097 3098 /* GEN 2 x2 */ 3099 opp-10000000-2 { 3100 opp-hz = /bits/ 64 <10000000>; 3101 required-opps = <&rpmhpd_opp_low_svs>; 3102 opp-peak-kBps = <1000000 1>; 3103 opp-level = <2>; 3104 }; 3105 3106 /* GEN 2 x4 */ 3107 opp-20000000-2 { 3108 opp-hz = /bits/ 64 <20000000>; 3109 required-opps = <&rpmhpd_opp_low_svs>; 3110 opp-peak-kBps = <2000000 1>; 3111 opp-level = <2>; 3112 }; 3113 3114 /* GEN 3 x1 */ 3115 opp-8000000-3 { 3116 opp-hz = /bits/ 64 <8000000>; 3117 required-opps = <&rpmhpd_opp_low_svs>; 3118 opp-peak-kBps = <984500 1>; 3119 opp-level = <3>; 3120 }; 3121 3122 /* GEN 3 x2 */ 3123 opp-16000000-3 { 3124 opp-hz = /bits/ 64 <16000000>; 3125 required-opps = <&rpmhpd_opp_low_svs>; 3126 opp-peak-kBps = <1969000 1>; 3127 opp-level = <3>; 3128 }; 3129 3130 /* GEN 3 x4 */ 3131 opp-32000000-3 { 3132 opp-hz = /bits/ 64 <32000000>; 3133 required-opps = <&rpmhpd_opp_low_svs>; 3134 opp-peak-kBps = <3938000 1>; 3135 opp-level = <3>; 3136 }; 3137 3138 /* GEN 4 x1 */ 3139 opp-16000000-4 { 3140 opp-hz = /bits/ 64 <16000000>; 3141 required-opps = <&rpmhpd_opp_svs>; 3142 opp-peak-kBps = <1969000 1>; 3143 opp-level = <4>; 3144 }; 3145 3146 /* GEN 4 x2 */ 3147 opp-32000000-4 { 3148 opp-hz = /bits/ 64 <32000000>; 3149 required-opps = <&rpmhpd_opp_svs>; 3150 opp-peak-kBps = <3938000 1>; 3151 opp-level = <4>; 3152 }; 3153 3154 /* GEN 4 x4 */ 3155 opp-64000000-4 { 3156 opp-hz = /bits/ 64 <64000000>; 3157 required-opps = <&rpmhpd_opp_svs>; 3158 opp-peak-kBps = <7876000 1>; 3159 opp-level = <4>; 3160 }; 3161 3162 /* GEN 5 x1 */ 3163 opp-32000000-5 { 3164 opp-hz = /bits/ 64 <32000000>; 3165 required-opps = <&rpmhpd_opp_nom>; 3166 opp-peak-kBps = <3938000 1>; 3167 opp-level = <5>; 3168 }; 3169 3170 /* GEN 5 x2 */ 3171 opp-64000000-5 { 3172 opp-hz = /bits/ 64 <64000000>; 3173 required-opps = <&rpmhpd_opp_nom>; 3174 opp-peak-kBps = <7876000 1>; 3175 opp-level = <5>; 3176 }; 3177 3178 /* GEN 5 x4 */ 3179 opp-128000000-5 { 3180 opp-hz = /bits/ 64 <128000000>; 3181 required-opps = <&rpmhpd_opp_nom>; 3182 opp-peak-kBps = <15753000 1>; 3183 opp-level = <5>; 3184 }; 3185 }; 3186 3187 pcie5_port0: pcie@0 { 3188 device_type = "pci"; 3189 reg = <0x0 0x0 0x0 0x0 0x0>; 3190 bus-range = <0x01 0xff>; 3191 3192 phys = <&pcie5_phy>; 3193 3194 #address-cells = <3>; 3195 #size-cells = <2>; 3196 ranges; 3197 }; 3198 }; 3199 3200 pcie5_phy: phy@1b50000 { 3201 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3202 reg = <0x0 0x01b50000 0x0 0x10000>; 3203 3204 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3205 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3206 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3207 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3208 <&gcc GCC_PCIE_5_PIPE_CLK>, 3209 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3210 clock-names = "aux", 3211 "cfg_ahb", 3212 "ref", 3213 "rchng", 3214 "pipe", 3215 "pipediv2"; 3216 3217 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3218 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3219 reset-names = "phy", 3220 "phy_nocsr"; 3221 3222 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3223 assigned-clock-rates = <100000000>; 3224 3225 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3226 3227 #clock-cells = <0>; 3228 clock-output-names = "pcie5_pipe_clk"; 3229 3230 #phy-cells = <0>; 3231 3232 status = "disabled"; 3233 }; 3234 3235 pcie6: pci@1c00000 { 3236 device_type = "pci"; 3237 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3238 reg = <0x0 0x01c00000 0x0 0x3000>, 3239 <0x0 0x7e000000 0x0 0xf20>, 3240 <0x0 0x7e000f40 0x0 0xa8>, 3241 <0x0 0x7e001000 0x0 0x4000>, 3242 <0x0 0x7e100000 0x0 0x100000>, 3243 <0x0 0x01c03000 0x0 0x1000>; 3244 reg-names = "parf", 3245 "dbi", 3246 "elbi", 3247 "atu", 3248 "config", 3249 "mhi"; 3250 #address-cells = <3>; 3251 #size-cells = <2>; 3252 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3253 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3254 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3255 bus-range = <0x00 0xff>; 3256 3257 dma-coherent; 3258 3259 linux,pci-domain = <6>; 3260 num-lanes = <2>; 3261 3262 operating-points-v2 = <&pcie6_opp_table>; 3263 3264 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3265 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3266 3267 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3276 interrupt-names = "msi0", 3277 "msi1", 3278 "msi2", 3279 "msi3", 3280 "msi4", 3281 "msi5", 3282 "msi6", 3283 "msi7", 3284 "global"; 3285 3286 #interrupt-cells = <1>; 3287 interrupt-map-mask = <0 0 0 0x7>; 3288 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 3289 <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 3290 <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 3291 <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 3292 3293 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3294 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3295 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3296 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3297 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3298 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3299 clock-names = "aux", 3300 "cfg", 3301 "bus_master", 3302 "bus_slave", 3303 "slave_q2a", 3304 "noc_aggr"; 3305 3306 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3307 assigned-clock-rates = <19200000>; 3308 3309 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3311 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3312 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3313 interconnect-names = "pcie-mem", 3314 "cpu-pcie"; 3315 3316 resets = <&gcc GCC_PCIE_6_BCR>, 3317 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3318 reset-names = "pci", 3319 "link_down"; 3320 3321 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3322 3323 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3324 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3325 3326 status = "disabled"; 3327 3328 pcie6_opp_table: opp-table { 3329 compatible = "operating-points-v2"; 3330 3331 /* GEN 1 x1 */ 3332 opp-2500000-1 { 3333 opp-hz = /bits/ 64 <2500000>; 3334 required-opps = <&rpmhpd_opp_low_svs>; 3335 opp-peak-kBps = <250000 1>; 3336 opp-level = <1>; 3337 }; 3338 3339 /* GEN 1 x2 */ 3340 opp-5000000-1 { 3341 opp-hz = /bits/ 64 <5000000>; 3342 required-opps = <&rpmhpd_opp_low_svs>; 3343 opp-peak-kBps = <500000 1>; 3344 opp-level = <1>; 3345 }; 3346 3347 /* GEN 2 x1 */ 3348 opp-5000000-2 { 3349 opp-hz = /bits/ 64 <5000000>; 3350 required-opps = <&rpmhpd_opp_low_svs>; 3351 opp-peak-kBps = <500000 1>; 3352 opp-level = <2>; 3353 }; 3354 3355 /* GEN 2 x2 */ 3356 opp-10000000-2 { 3357 opp-hz = /bits/ 64 <10000000>; 3358 required-opps = <&rpmhpd_opp_low_svs>; 3359 opp-peak-kBps = <1000000 1>; 3360 opp-level = <2>; 3361 }; 3362 3363 /* GEN 3 x1 */ 3364 opp-8000000-3 { 3365 opp-hz = /bits/ 64 <8000000>; 3366 required-opps = <&rpmhpd_opp_low_svs>; 3367 opp-peak-kBps = <984500 1>; 3368 opp-level = <3>; 3369 }; 3370 3371 /* GEN 3 x2 */ 3372 opp-16000000-3 { 3373 opp-hz = /bits/ 64 <16000000>; 3374 required-opps = <&rpmhpd_opp_low_svs>; 3375 opp-peak-kBps = <1969000 1>; 3376 opp-level = <3>; 3377 }; 3378 3379 /* GEN 4 x1 */ 3380 opp-16000000-4 { 3381 opp-hz = /bits/ 64 <16000000>; 3382 required-opps = <&rpmhpd_opp_low_svs>; 3383 opp-peak-kBps = <1969000 1>; 3384 opp-level = <4>; 3385 }; 3386 3387 /* GEN 4 x2 */ 3388 opp-32000000-4 { 3389 opp-hz = /bits/ 64 <32000000>; 3390 required-opps = <&rpmhpd_opp_low_svs>; 3391 opp-peak-kBps = <3938000 1>; 3392 opp-level = <4>; 3393 }; 3394 3395 }; 3396 3397 pcie6_port0: pcie@0 { 3398 device_type = "pci"; 3399 reg = <0x0 0x0 0x0 0x0 0x0>; 3400 bus-range = <0x01 0xff>; 3401 3402 phys = <&pcie6_phy>; 3403 3404 #address-cells = <3>; 3405 #size-cells = <2>; 3406 ranges; 3407 }; 3408 }; 3409 3410 pcie6_phy: phy@1c06000 { 3411 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3412 reg = <0x0 0x01c06000 0x0 0x2000>; 3413 3414 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3415 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3416 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3417 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3418 <&gcc GCC_PCIE_6_PIPE_CLK>, 3419 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3420 clock-names = "aux", 3421 "cfg_ahb", 3422 "ref", 3423 "rchng", 3424 "pipe", 3425 "pipediv2"; 3426 3427 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3428 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3429 reset-names = "phy", 3430 "phy_nocsr"; 3431 3432 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3433 assigned-clock-rates = <100000000>; 3434 3435 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3436 3437 #clock-cells = <0>; 3438 clock-output-names = "pcie6_pipe_clk"; 3439 3440 #phy-cells = <0>; 3441 3442 status = "disabled"; 3443 }; 3444 3445 pcie3b: pci@1b80000 { 3446 device_type = "pci"; 3447 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3448 reg = <0x0 0x01b80000 0x0 0x3000>, 3449 <0x0 0x74000000 0x0 0xf20>, 3450 <0x0 0x74000f40 0x0 0xa8>, 3451 <0x0 0x74001000 0x0 0x4000>, 3452 <0x0 0x74100000 0x0 0x100000>, 3453 <0x0 0x01b83000 0x0 0x1000>; 3454 reg-names = "parf", 3455 "dbi", 3456 "elbi", 3457 "atu", 3458 "config", 3459 "mhi"; 3460 #address-cells = <3>; 3461 #size-cells = <2>; 3462 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3463 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3464 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3465 bus-range = <0x00 0xff>; 3466 3467 dma-coherent; 3468 3469 linux,pci-domain = <7>; 3470 num-lanes = <4>; 3471 3472 operating-points-v2 = <&pcie3b_opp_table>; 3473 3474 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3475 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3476 3477 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3486 interrupt-names = "msi0", 3487 "msi1", 3488 "msi2", 3489 "msi3", 3490 "msi4", 3491 "msi5", 3492 "msi6", 3493 "msi7", 3494 "global"; 3495 3496 #interrupt-cells = <1>; 3497 interrupt-map-mask = <0 0 0 0x7>; 3498 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, 3499 <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 3500 <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, 3501 <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 3502 3503 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3504 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3505 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3506 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3507 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3508 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3509 clock-names = "aux", 3510 "cfg", 3511 "bus_master", 3512 "bus_slave", 3513 "slave_q2a", 3514 "noc_aggr"; 3515 3516 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3517 assigned-clock-rates = <19200000>; 3518 3519 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3520 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3521 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3522 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3523 interconnect-names = "pcie-mem", 3524 "cpu-pcie"; 3525 3526 resets = <&gcc GCC_PCIE_3B_BCR>, 3527 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3528 reset-names = "pci", 3529 "link_down"; 3530 3531 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3532 3533 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3534 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3535 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3536 3537 status = "disabled"; 3538 3539 pcie3b_opp_table: opp-table { 3540 compatible = "operating-points-v2"; 3541 3542 /* GEN 1 x1 */ 3543 opp-2500000-1 { 3544 opp-hz = /bits/ 64 <2500000>; 3545 required-opps = <&rpmhpd_opp_low_svs>; 3546 opp-peak-kBps = <250000 1>; 3547 opp-level = <1>; 3548 }; 3549 3550 /* GEN 1 x2 */ 3551 opp-5000000-1 { 3552 opp-hz = /bits/ 64 <5000000>; 3553 required-opps = <&rpmhpd_opp_low_svs>; 3554 opp-peak-kBps = <500000 1>; 3555 opp-level = <1>; 3556 }; 3557 3558 /* GEN 1 x4 */ 3559 opp-10000000-1 { 3560 opp-hz = /bits/ 64 <10000000>; 3561 required-opps = <&rpmhpd_opp_low_svs>; 3562 opp-peak-kBps = <1000000 1>; 3563 opp-level = <1>; 3564 }; 3565 3566 /* GEN 2 x1 */ 3567 opp-5000000-2 { 3568 opp-hz = /bits/ 64 <5000000>; 3569 required-opps = <&rpmhpd_opp_low_svs>; 3570 opp-peak-kBps = <500000 1>; 3571 opp-level = <2>; 3572 }; 3573 3574 /* GEN 2 x2 */ 3575 opp-10000000-2 { 3576 opp-hz = /bits/ 64 <10000000>; 3577 required-opps = <&rpmhpd_opp_low_svs>; 3578 opp-peak-kBps = <1000000 1>; 3579 opp-level = <2>; 3580 }; 3581 3582 /* GEN 2 x4 */ 3583 opp-20000000-2 { 3584 opp-hz = /bits/ 64 <20000000>; 3585 required-opps = <&rpmhpd_opp_low_svs>; 3586 opp-peak-kBps = <2000000 1>; 3587 opp-level = <2>; 3588 }; 3589 3590 /* GEN 3 x1 */ 3591 opp-8000000-3 { 3592 opp-hz = /bits/ 64 <8000000>; 3593 required-opps = <&rpmhpd_opp_low_svs>; 3594 opp-peak-kBps = <984500 1>; 3595 opp-level = <3>; 3596 }; 3597 3598 /* GEN 3 x2 */ 3599 opp-16000000-3 { 3600 opp-hz = /bits/ 64 <16000000>; 3601 required-opps = <&rpmhpd_opp_low_svs>; 3602 opp-peak-kBps = <1969000 1>; 3603 opp-level = <3>; 3604 }; 3605 3606 /* GEN 3 x4 */ 3607 opp-32000000-3 { 3608 opp-hz = /bits/ 64 <32000000>; 3609 required-opps = <&rpmhpd_opp_low_svs>; 3610 opp-peak-kBps = <3938000 1>; 3611 opp-level = <3>; 3612 }; 3613 3614 /* GEN 4 x1 */ 3615 opp-16000000-4 { 3616 opp-hz = /bits/ 64 <16000000>; 3617 required-opps = <&rpmhpd_opp_svs>; 3618 opp-peak-kBps = <1969000 1>; 3619 opp-level = <4>; 3620 }; 3621 3622 /* GEN 4 x2 */ 3623 opp-32000000-4 { 3624 opp-hz = /bits/ 64 <32000000>; 3625 required-opps = <&rpmhpd_opp_svs>; 3626 opp-peak-kBps = <3938000 1>; 3627 opp-level = <4>; 3628 }; 3629 3630 /* GEN 4 x4 */ 3631 opp-64000000-4 { 3632 opp-hz = /bits/ 64 <64000000>; 3633 required-opps = <&rpmhpd_opp_svs>; 3634 opp-peak-kBps = <7876000 1>; 3635 opp-level = <4>; 3636 }; 3637 3638 /* GEN 5 x1 */ 3639 opp-32000000-5 { 3640 opp-hz = /bits/ 64 <32000000>; 3641 required-opps = <&rpmhpd_opp_nom>; 3642 opp-peak-kBps = <3938000 1>; 3643 opp-level = <5>; 3644 }; 3645 3646 /* GEN 5 x2 */ 3647 opp-64000000-5 { 3648 opp-hz = /bits/ 64 <64000000>; 3649 required-opps = <&rpmhpd_opp_nom>; 3650 opp-peak-kBps = <7876000 1>; 3651 opp-level = <5>; 3652 }; 3653 3654 /* GEN 5 x4 */ 3655 opp-128000000-5 { 3656 opp-hz = /bits/ 64 <128000000>; 3657 required-opps = <&rpmhpd_opp_nom>; 3658 opp-peak-kBps = <15753000 1>; 3659 opp-level = <5>; 3660 }; 3661 }; 3662 3663 pcie3b_port0: pcie@0 { 3664 device_type = "pci"; 3665 reg = <0x0 0x0 0x0 0x0 0x0>; 3666 bus-range = <0x01 0xff>; 3667 3668 phys = <&pcie3b_phy>; 3669 3670 #address-cells = <3>; 3671 #size-cells = <2>; 3672 ranges; 3673 }; 3674 }; 3675 3676 pcie3b_phy: phy@f10000 { 3677 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3678 reg = <0x0 0x00f10000 0x0 0x10000>; 3679 3680 clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 3681 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3682 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 3683 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 3684 <&gcc GCC_PCIE_3B_PIPE_CLK>, 3685 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 3686 clock-names = "aux", 3687 "cfg_ahb", 3688 "ref", 3689 "rchng", 3690 "pipe", 3691 "pipediv2"; 3692 3693 resets = <&gcc GCC_PCIE_3B_PHY_BCR>, 3694 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 3695 reset-names = "phy", 3696 "phy_nocsr"; 3697 3698 assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 3699 assigned-clock-rates = <100000000>; 3700 3701 power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; 3702 3703 #clock-cells = <0>; 3704 clock-output-names = "pcie3b_pipe_clk"; 3705 3706 #phy-cells = <0>; 3707 3708 status = "disabled"; 3709 }; 3710 3711 cryptobam: dma-controller@1dc4000 { 3712 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3713 reg = <0x0 0x01dc4000 0x0 0x28000>; 3714 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3715 #dma-cells = <1>; 3716 iommus = <&apps_smmu 0x80 0x0>, 3717 <&apps_smmu 0x81 0x0>; 3718 qcom,ee = <0>; 3719 qcom,controlled-remotely; 3720 num-channels = <20>; 3721 qcom,num-ees = <4>; 3722 }; 3723 3724 crypto: crypto@1dfa000 { 3725 compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; 3726 reg = <0x0 0x01dfa000 0x0 0x6000>; 3727 dmas = <&cryptobam 4>, <&cryptobam 5>; 3728 dma-names = "rx", 3729 "tx"; 3730 iommus = <&apps_smmu 0x80 0x0>, 3731 <&apps_smmu 0x81 0x0>; 3732 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 3733 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3734 interconnect-names = "memory"; 3735 }; 3736 3737 tcsr_mutex: hwlock@1f40000 { 3738 compatible = "qcom,tcsr-mutex"; 3739 reg = <0x0 0x01f40000 0x0 0x20000>; 3740 3741 #hwlock-cells = <1>; 3742 }; 3743 3744 tcsr: clock-controller@1fd5000 { 3745 compatible = "qcom,glymur-tcsr", 3746 "syscon"; 3747 reg = <0x0 0x1fd5000 0x0 0x21000>; 3748 clocks = <&rpmhcc RPMH_CXO_CLK>; 3749 #clock-cells = <1>; 3750 #reset-cells = <1>; 3751 }; 3752 3753 hsc_noc: interconnect@2000000 { 3754 compatible = "qcom,glymur-hscnoc"; 3755 reg = <0x0 0x02000000 0x0 0x93a080>; 3756 qcom,bcm-voters = <&apps_bcm_voter>; 3757 #interconnect-cells = <2>; 3758 }; 3759 3760 gxclkctl: clock-controller@3d64000 { 3761 compatible = "qcom,glymur-gxclkctl"; 3762 reg = <0x0 0x03d64000 0x0 0x6000>; 3763 3764 power-domains = <&rpmhpd RPMHPD_GFX>, 3765 <&rpmhpd RPMHPD_GMXC>, 3766 <&gpucc GPU_CC_CX_GDSC>; 3767 3768 #power-domain-cells = <1>; 3769 }; 3770 3771 gpucc: clock-controller@3d90000 { 3772 compatible = "qcom,glymur-gpucc"; 3773 reg = <0x0 0x03d90000 0x0 0x9800>; 3774 clocks = <&rpmhcc RPMH_CXO_CLK>, 3775 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3776 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3777 3778 power-domains = <&rpmhpd RPMHPD_MX>, 3779 <&rpmhpd RPMHPD_CX>; 3780 required-opps = <&rpmhpd_opp_low_svs>, 3781 <&rpmhpd_opp_low_svs>; 3782 3783 #clock-cells = <1>; 3784 #reset-cells = <1>; 3785 #power-domain-cells = <1>; 3786 }; 3787 3788 ipcc: mailbox@3e04000 { 3789 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 3790 reg = <0x0 0x03e04000 0x0 0x1000>; 3791 3792 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3793 interrupt-controller; 3794 #interrupt-cells = <3>; 3795 3796 #mbox-cells = <2>; 3797 }; 3798 3799 remoteproc_adsp: remoteproc@6800000 { 3800 compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; 3801 reg = <0x0 0x06800000 0x0 0x10000>; 3802 3803 iommus = <&apps_smmu 0x1000 0x0>; 3804 3805 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3806 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3807 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3808 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3809 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 3810 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 3811 interrupt-names = "wdog", 3812 "fatal", 3813 "ready", 3814 "handover", 3815 "stop-ack", 3816 "shutdown-ack"; 3817 3818 clocks = <&rpmhcc RPMH_CXO_CLK>; 3819 clock-names = "xo"; 3820 3821 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 3822 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3823 3824 power-domains = <&rpmhpd RPMHPD_LCX>, 3825 <&rpmhpd RPMHPD_LMX>; 3826 power-domain-names = "lcx", 3827 "lmx"; 3828 3829 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3830 3831 qcom,qmp = <&aoss_qmp>; 3832 3833 qcom,smem-states = <&smp2p_adsp_out 0>; 3834 qcom,smem-state-names = "stop"; 3835 3836 status = "disabled"; 3837 3838 remoteproc_adsp_glink: glink-edge { 3839 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 3840 IPCC_MPROC_SIGNAL_GLINK_QMP 3841 IRQ_TYPE_EDGE_RISING>; 3842 3843 mboxes = <&ipcc IPCC_MPROC_LPASS 3844 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3845 3846 qcom,remote-pid = <2>; 3847 3848 label = "lpass"; 3849 3850 fastrpc { 3851 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 3852 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3853 label = "adsp"; 3854 #address-cells = <1>; 3855 #size-cells = <0>; 3856 3857 compute-cb@3 { 3858 compatible = "qcom,fastrpc-compute-cb"; 3859 reg = <3>; 3860 3861 iommus = <&apps_smmu 0x1003 0x80>, 3862 <&apps_smmu 0x1063 0x20>; 3863 dma-coherent; 3864 }; 3865 3866 compute-cb@4 { 3867 compatible = "qcom,fastrpc-compute-cb"; 3868 reg = <4>; 3869 3870 iommus = <&apps_smmu 0x1004 0x80>, 3871 <&apps_smmu 0x1064 0x20>; 3872 dma-coherent; 3873 }; 3874 3875 compute-cb@5 { 3876 compatible = "qcom,fastrpc-compute-cb"; 3877 reg = <5>; 3878 3879 iommus = <&apps_smmu 0x1005 0x80>, 3880 <&apps_smmu 0x1065 0x20>; 3881 dma-coherent; 3882 }; 3883 3884 compute-cb@6 { 3885 compatible = "qcom,fastrpc-compute-cb"; 3886 reg = <6>; 3887 3888 iommus = <&apps_smmu 0x1006 0x80>, 3889 <&apps_smmu 0x1066 0x20>; 3890 dma-coherent; 3891 }; 3892 3893 compute-cb@7 { 3894 compatible = "qcom,fastrpc-compute-cb"; 3895 reg = <7>; 3896 3897 iommus = <&apps_smmu 0x1007 0x40>, 3898 <&apps_smmu 0x1067 0x0>, 3899 <&apps_smmu 0x1087 0x0>; 3900 dma-coherent; 3901 }; 3902 3903 compute-cb@8 { 3904 compatible = "qcom,fastrpc-compute-cb"; 3905 reg = <8>; 3906 3907 iommus = <&apps_smmu 0x1008 0x80>, 3908 <&apps_smmu 0x1068 0x20>; 3909 dma-coherent; 3910 }; 3911 }; 3912 }; 3913 }; 3914 3915 lpass_lpiaon_noc: interconnect@7400000 { 3916 compatible = "qcom,glymur-lpass-lpiaon-noc"; 3917 reg = <0x0 0x07400000 0x0 0x19080>; 3918 qcom,bcm-voters = <&apps_bcm_voter>; 3919 #interconnect-cells = <2>; 3920 }; 3921 3922 lpass_lpicx_noc: interconnect@7420000 { 3923 compatible = "qcom,glymur-lpass-lpicx-noc"; 3924 reg = <0x0 0x07420000 0x0 0x44080>; 3925 qcom,bcm-voters = <&apps_bcm_voter>; 3926 #interconnect-cells = <2>; 3927 }; 3928 3929 lpass_ag_noc: interconnect@7e40000 { 3930 compatible = "qcom,glymur-lpass-ag-noc"; 3931 reg = <0x0 0x07e40000 0x0 0xe080>; 3932 qcom,bcm-voters = <&apps_bcm_voter>; 3933 #interconnect-cells = <2>; 3934 }; 3935 3936 usb_2_hsphy: phy@88e0000 { 3937 compatible = "qcom,glymur-m31-eusb2-phy", 3938 "qcom,sm8750-m31-eusb2-phy"; 3939 3940 reg = <0x0 0x088e0000 0x0 0x29c>; 3941 #phy-cells = <0>; 3942 3943 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 3944 clock-names = "ref"; 3945 3946 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3947 3948 status = "disabled"; 3949 }; 3950 3951 usb_2_qmpphy: phy@88e1000 { 3952 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 3953 reg = <0x0 0x088e1000 0x0 0x8000>; 3954 3955 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3956 <&rpmhcc RPMH_CXO_CLK>, 3957 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3958 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, 3959 <&tcsr TCSR_USB4_2_CLKREF_EN>; 3960 clock-names = "aux", 3961 "ref", 3962 "com_aux", 3963 "usb3_pipe", 3964 "clkref"; 3965 3966 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3967 3968 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3969 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 3970 reset-names = "phy", 3971 "common"; 3972 3973 #clock-cells = <1>; 3974 #phy-cells = <1>; 3975 3976 mode-switch; 3977 orientation-switch; 3978 3979 status = "disabled"; 3980 3981 ports { 3982 #address-cells = <1>; 3983 #size-cells = <0>; 3984 3985 port@0 { 3986 reg = <0>; 3987 3988 usb_2_qmpphy_out: endpoint { 3989 }; 3990 }; 3991 3992 port@1 { 3993 reg = <1>; 3994 3995 usb_2_qmpphy_usb_ss_in: endpoint { 3996 remote-endpoint = <&usb_2_dwc3_ss>; 3997 }; 3998 }; 3999 4000 port@2 { 4001 reg = <2>; 4002 4003 usb_2_qmpphy_dp_in: endpoint { 4004 remote-endpoint = <&mdss_dp2_out>; 4005 }; 4006 }; 4007 }; 4008 }; 4009 4010 usb_0: usb@a600000 { 4011 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4012 reg = <0x0 0x0a600000 0x0 0xfc100>; 4013 4014 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4015 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4016 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4017 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4018 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4019 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4020 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4021 clock-names = "cfg_noc", 4022 "core", 4023 "iface", 4024 "sleep", 4025 "mock_utmi", 4026 "noc_aggr_north", 4027 "noc_aggr_south"; 4028 4029 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 4030 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4031 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 4032 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4033 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 4034 interrupt-names = "dwc_usb3", 4035 "pwr_event", 4036 "dp_hs_phy_irq", 4037 "dm_hs_phy_irq", 4038 "ss_phy_irq"; 4039 4040 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4041 resets = <&gcc GCC_USB30_PRIM_BCR>; 4042 4043 iommus = <&apps_smmu 0x1420 0x0>; 4044 phys = <&usb_0_hsphy>, 4045 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4046 phy-names = "usb2-phy", 4047 "usb3-phy"; 4048 4049 snps,hird-threshold = /bits/ 8 <0x0>; 4050 snps,dis-u1-entry-quirk; 4051 snps,dis-u2-entry-quirk; 4052 snps,is-utmi-l1-suspend; 4053 snps,usb3_lpm_capable; 4054 snps,has-lpm-erratum; 4055 tx-fifo-resize; 4056 snps,dis_u2_susphy_quirk; 4057 snps,dis_enblslpm_quirk; 4058 4059 usb-role-switch; 4060 4061 status = "disabled"; 4062 4063 ports { 4064 #address-cells = <1>; 4065 #size-cells = <0>; 4066 4067 port@0 { 4068 reg = <0>; 4069 4070 usb_0_dwc3_hs: endpoint { 4071 }; 4072 }; 4073 4074 port@1 { 4075 reg = <1>; 4076 4077 usb_0_dwc3_ss: endpoint { 4078 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4079 }; 4080 }; 4081 }; 4082 }; 4083 4084 usb_1: usb@a800000 { 4085 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4086 reg = <0x0 0x0a800000 0x0 0xfc100>; 4087 4088 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4089 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4090 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4091 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4092 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4093 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4094 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4095 clock-names = "cfg_noc", 4096 "core", 4097 "iface", 4098 "sleep", 4099 "mock_utmi", 4100 "noc_aggr_north", 4101 "noc_aggr_south"; 4102 4103 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 4104 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 4105 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 4106 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 4107 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 4108 interrupt-names = "dwc_usb3", 4109 "pwr_event", 4110 "dp_hs_phy_irq", 4111 "dm_hs_phy_irq", 4112 "ss_phy_irq"; 4113 4114 resets = <&gcc GCC_USB30_SEC_BCR>; 4115 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4116 4117 iommus = <&apps_smmu 0x1460 0x0>; 4118 4119 phys = <&usb_1_hsphy>, 4120 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4121 phy-names = "usb2-phy", 4122 "usb3-phy"; 4123 4124 snps,hird-threshold = /bits/ 8 <0x0>; 4125 snps,dis-u1-entry-quirk; 4126 snps,dis-u2-entry-quirk; 4127 snps,is-utmi-l1-suspend; 4128 snps,usb3_lpm_capable; 4129 snps,has-lpm-erratum; 4130 tx-fifo-resize; 4131 snps,dis_u2_susphy_quirk; 4132 snps,dis_enblslpm_quirk; 4133 4134 usb-role-switch; 4135 4136 status = "disabled"; 4137 4138 ports { 4139 #address-cells = <1>; 4140 #size-cells = <0>; 4141 4142 port@0 { 4143 reg = <0>; 4144 4145 usb_1_dwc3_hs: endpoint { 4146 }; 4147 }; 4148 4149 port@1 { 4150 reg = <1>; 4151 4152 usb_1_dwc3_ss: endpoint { 4153 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4154 }; 4155 }; 4156 }; 4157 }; 4158 4159 usb_2: usb@a000000 { 4160 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4161 reg = <0x0 0x0a000000 0x0 0xfc100>; 4162 4163 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4164 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4165 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4166 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4167 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4168 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4169 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4170 clock-names = "cfg_noc", 4171 "core", 4172 "iface", 4173 "sleep", 4174 "mock_utmi", 4175 "noc_aggr_north", 4176 "noc_aggr_south"; 4177 4178 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 4179 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4180 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 4181 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 4182 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 4183 interrupt-names = "dwc_usb3", 4184 "pwr_event", 4185 "dp_hs_phy_irq", 4186 "dm_hs_phy_irq", 4187 "ss_phy_irq"; 4188 4189 resets = <&gcc GCC_USB30_TERT_BCR>; 4190 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4191 4192 iommus = <&apps_smmu 0x420 0x0>; 4193 4194 phys = <&usb_2_hsphy>, 4195 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 4196 phy-names = "usb2-phy", 4197 "usb3-phy"; 4198 4199 snps,hird-threshold = /bits/ 8 <0x0>; 4200 snps,dis-u1-entry-quirk; 4201 snps,dis-u2-entry-quirk; 4202 snps,is-utmi-l1-suspend; 4203 snps,usb3_lpm_capable; 4204 snps,has-lpm-erratum; 4205 tx-fifo-resize; 4206 snps,dis_u2_susphy_quirk; 4207 snps,dis_enblslpm_quirk; 4208 4209 usb-role-switch; 4210 4211 status = "disabled"; 4212 4213 ports { 4214 #address-cells = <1>; 4215 #size-cells = <0>; 4216 4217 port@0 { 4218 reg = <0>; 4219 4220 usb_2_dwc3_hs: endpoint { 4221 }; 4222 }; 4223 4224 port@1 { 4225 reg = <1>; 4226 4227 usb_2_dwc3_ss: endpoint { 4228 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 4229 }; 4230 }; 4231 }; 4232 }; 4233 4234 usb_hs: usb@a200000 { 4235 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4236 reg = <0x0 0x0a200000 0x0 0xfc100>; 4237 4238 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4239 <&gcc GCC_USB20_MASTER_CLK>, 4240 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4241 <&gcc GCC_USB20_SLEEP_CLK>, 4242 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4243 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4244 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4245 clock-names = "cfg_noc", 4246 "core", 4247 "iface", 4248 "sleep", 4249 "mock_utmi", 4250 "noc_aggr_north", 4251 "noc_aggr_south"; 4252 4253 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4254 <&gcc GCC_USB20_MASTER_CLK>; 4255 assigned-clock-rates = <19200000>, <200000000>; 4256 4257 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4258 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 4259 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 4260 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4261 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 4262 interrupt-names = "dwc_usb3", 4263 "pwr_event", 4264 "dp_hs_phy_irq", 4265 "dm_hs_phy_irq", 4266 "hs_phy_irq"; 4267 4268 resets = <&gcc GCC_USB20_PRIM_BCR>; 4269 4270 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4271 required-opps = <&rpmhpd_opp_nom>; 4272 4273 iommus = <&apps_smmu 0x0ce0 0x0>; 4274 4275 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4276 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4277 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4278 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4279 interconnect-names = "usb-ddr", 4280 "apps-usb"; 4281 4282 phys = <&usb_hs_phy>; 4283 phy-names = "usb2-phy"; 4284 4285 snps,hird-threshold = /bits/ 8 <0x0>; 4286 snps,dis-u1-entry-quirk; 4287 snps,dis-u2-entry-quirk; 4288 snps,is-utmi-l1-suspend; 4289 snps,usb3_lpm_capable; 4290 snps,has-lpm-erratum; 4291 tx-fifo-resize; 4292 snps,dis_u2_susphy_quirk; 4293 snps,dis_enblslpm_quirk; 4294 4295 dr_mode = "host"; 4296 4297 maximum-speed = "high-speed"; 4298 4299 status = "disabled"; 4300 }; 4301 4302 usb_mp: usb@a400000 { 4303 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 4304 reg = <0x0 0x0a400000 0x0 0xfc100>; 4305 4306 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4307 <&gcc GCC_USB30_MP_MASTER_CLK>, 4308 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4309 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4310 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4311 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4312 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4313 clock-names = "cfg_noc", 4314 "core", 4315 "iface", 4316 "sleep", 4317 "mock_utmi", 4318 "noc_aggr_north", 4319 "noc_aggr_south"; 4320 4321 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4322 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4323 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4324 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 4325 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4326 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 4327 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 4328 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 4329 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 4330 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 4331 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 4332 interrupt-names = "dwc_usb3", 4333 "pwr_event_1", 4334 "pwr_event_2", 4335 "hs_phy_1", 4336 "hs_phy_2", 4337 "dp_hs_phy_1", 4338 "dm_hs_phy_1", 4339 "dp_hs_phy_2", 4340 "dm_hs_phy_2", 4341 "ss_phy_1", 4342 "ss_phy_2"; 4343 4344 resets = <&gcc GCC_USB30_MP_BCR>; 4345 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4346 4347 iommus = <&apps_smmu 0xda0 0x0>; 4348 4349 phys = <&usb_mp_hsphy0>, 4350 <&usb_mp_qmpphy0>, 4351 <&usb_mp_hsphy1>, 4352 <&usb_mp_qmpphy1>; 4353 phy-names = "usb2-0", 4354 "usb3-0", 4355 "usb2-1", 4356 "usb3-1"; 4357 4358 snps,hird-threshold = /bits/ 8 <0x0>; 4359 snps,dis-u1-entry-quirk; 4360 snps,dis-u2-entry-quirk; 4361 snps,is-utmi-l1-suspend; 4362 snps,usb3_lpm_capable; 4363 snps,has-lpm-erratum; 4364 tx-fifo-resize; 4365 snps,dis_u2_susphy_quirk; 4366 snps,dis_enblslpm_quirk; 4367 4368 dr_mode = "host"; 4369 4370 status = "disabled"; 4371 }; 4372 4373 mdss: display-subsystem@ae00000 { 4374 compatible = "qcom,glymur-mdss"; 4375 reg = <0x0 0x0ae00000 0x0 0x1000>; 4376 reg-names = "mdss"; 4377 4378 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4379 4380 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4381 <&gcc GCC_DISP_HF_AXI_CLK>, 4382 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4383 4384 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4385 4386 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4387 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4388 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4389 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4390 interconnect-names = "mdp0-mem", 4391 "cpu-cfg"; 4392 4393 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4394 4395 iommus = <&apps_smmu 0x1de0 0x2>; 4396 4397 interrupt-controller; 4398 #interrupt-cells = <1>; 4399 4400 #address-cells = <2>; 4401 #size-cells = <2>; 4402 ranges; 4403 4404 status = "disabled"; 4405 4406 mdss_mdp: display-controller@ae01000 { 4407 compatible = "qcom,glymur-dpu"; 4408 reg = <0x0 0x0ae01000 0x0 0x93000>, 4409 <0x0 0x0aeb0000 0x0 0x3000>; 4410 reg-names = "mdp", 4411 "vbif"; 4412 4413 interrupts-extended = <&mdss 0>; 4414 4415 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4416 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4417 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4418 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4419 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4420 clock-names = "nrt_bus", 4421 "iface", 4422 "lut", 4423 "core", 4424 "vsync"; 4425 4426 operating-points-v2 = <&mdp_opp_table>; 4427 4428 power-domains = <&rpmhpd RPMHPD_MMCX>; 4429 4430 ports { 4431 #address-cells = <1>; 4432 #size-cells = <0>; 4433 4434 port@0 { 4435 reg = <0>; 4436 4437 dpu_intf0_out: endpoint { 4438 remote-endpoint = <&mdss_dp0_in>; 4439 }; 4440 }; 4441 4442 port@4 { 4443 reg = <4>; 4444 4445 mdss_intf4_out: endpoint { 4446 remote-endpoint = <&mdss_dp1_in>; 4447 }; 4448 }; 4449 4450 port@5 { 4451 reg = <5>; 4452 4453 mdss_intf5_out: endpoint { 4454 remote-endpoint = <&mdss_dp3_in>; 4455 }; 4456 }; 4457 4458 port@6 { 4459 reg = <6>; 4460 4461 mdss_intf6_out: endpoint { 4462 remote-endpoint = <&mdss_dp2_in>; 4463 }; 4464 }; 4465 }; 4466 4467 mdp_opp_table: opp-table { 4468 compatible = "operating-points-v2"; 4469 4470 opp-156000000 { 4471 opp-hz = /bits/ 64 <156000000>; 4472 required-opps = <&rpmhpd_opp_low_svs_d1>; 4473 }; 4474 4475 opp-205000000 { 4476 opp-hz = /bits/ 64 <205000000>; 4477 required-opps = <&rpmhpd_opp_low_svs>; 4478 }; 4479 4480 opp-337000000 { 4481 opp-hz = /bits/ 64 <337000000>; 4482 required-opps = <&rpmhpd_opp_svs>; 4483 }; 4484 4485 opp-417000000 { 4486 opp-hz = /bits/ 64 <417000000>; 4487 required-opps = <&rpmhpd_opp_svs_l1>; 4488 }; 4489 4490 opp-532000000 { 4491 opp-hz = /bits/ 64 <532000000>; 4492 required-opps = <&rpmhpd_opp_nom>; 4493 }; 4494 4495 opp-600000000 { 4496 opp-hz = /bits/ 64 <600000000>; 4497 required-opps = <&rpmhpd_opp_nom_l1>; 4498 }; 4499 4500 opp-660000000 { 4501 opp-hz = /bits/ 64 <660000000>; 4502 required-opps = <&rpmhpd_opp_turbo>; 4503 }; 4504 4505 opp-717000000 { 4506 opp-hz = /bits/ 64 <717000000>; 4507 required-opps = <&rpmhpd_opp_turbo_l1>; 4508 }; 4509 }; 4510 }; 4511 4512 mdss_dp0: displayport-controller@af54000 { 4513 compatible = "qcom,glymur-dp"; 4514 reg = <0x0 0xaf54000 0x0 0x200>, 4515 <0x0 0xaf54200 0x0 0x200>, 4516 <0x0 0xaf55000 0x0 0xc00>, 4517 <0x0 0xaf56000 0x0 0x400>, 4518 <0x0 0xaf57000 0x0 0x400>, 4519 <0x0 0xaf58000 0x0 0x400>, 4520 <0x0 0xaf59000 0x0 0x400>, 4521 <0x0 0xaf5a000 0x0 0x600>, 4522 <0x0 0xaf5b000 0x0 0x600>; 4523 4524 interrupts-extended = <&mdss 12>; 4525 4526 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4527 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4528 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4529 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4530 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4531 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4532 clock-names = "core_iface", 4533 "core_aux", 4534 "ctrl_link", 4535 "ctrl_link_iface", 4536 "stream_pixel", 4537 "stream_1_pixel"; 4538 4539 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4540 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4541 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4542 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4543 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4544 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4545 4546 operating-points-v2 = <&mdss_dp0_opp_table>; 4547 4548 power-domains = <&rpmhpd RPMHPD_MMCX>; 4549 4550 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4551 phy-names = "dp"; 4552 4553 #sound-dai-cells = <0>; 4554 4555 status = "disabled"; 4556 4557 ports { 4558 #address-cells = <1>; 4559 #size-cells = <0>; 4560 4561 port@0 { 4562 reg = <0>; 4563 4564 mdss_dp0_in: endpoint { 4565 remote-endpoint = <&dpu_intf0_out>; 4566 }; 4567 }; 4568 4569 port@1 { 4570 reg = <1>; 4571 4572 mdss_dp0_out: endpoint { 4573 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 4574 }; 4575 }; 4576 }; 4577 4578 mdss_dp0_opp_table: opp-table { 4579 compatible = "operating-points-v2"; 4580 4581 opp-270000000 { 4582 opp-hz = /bits/ 64 <270000000>; 4583 required-opps = <&rpmhpd_opp_low_svs>; 4584 }; 4585 4586 opp-540000000 { 4587 opp-hz = /bits/ 64 <540000000>; 4588 required-opps = <&rpmhpd_opp_svs>; 4589 }; 4590 4591 opp-675000000 { 4592 opp-hz = /bits/ 64 <675000000>; 4593 required-opps = <&rpmhpd_opp_svs_l1>; 4594 }; 4595 4596 opp-810000000 { 4597 opp-hz = /bits/ 64 <810000000>; 4598 required-opps = <&rpmhpd_opp_nom>; 4599 }; 4600 }; 4601 }; 4602 4603 mdss_dp1: displayport-controller@af5c000 { 4604 compatible = "qcom,glymur-dp"; 4605 reg = <0x0 0xaf5c000 0x0 0x200>, 4606 <0x0 0xaf5c200 0x0 0x200>, 4607 <0x0 0xaf5d000 0x0 0xc00>, 4608 <0x0 0xaf5e000 0x0 0x400>, 4609 <0x0 0xaf5f000 0x0 0x400>, 4610 <0x0 0xaf60000 0x0 0x400>, 4611 <0x0 0xaf61000 0x0 0x400>, 4612 <0x0 0xaf62000 0x0 0x600>, 4613 <0x0 0xaf63000 0x0 0x600>; 4614 4615 interrupts-extended = <&mdss 13>; 4616 4617 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4618 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4619 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4620 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4621 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 4622 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 4623 clock-names = "core_iface", 4624 "core_aux", 4625 "ctrl_link", 4626 "ctrl_link_iface", 4627 "stream_pixel", 4628 "stream_1_pixel"; 4629 4630 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4631 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 4632 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 4633 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4634 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4635 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4636 4637 operating-points-v2 = <&mdss_dp0_opp_table>; 4638 4639 power-domains = <&rpmhpd RPMHPD_MMCX>; 4640 4641 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4642 phy-names = "dp"; 4643 4644 #sound-dai-cells = <0>; 4645 4646 status = "disabled"; 4647 4648 ports { 4649 #address-cells = <1>; 4650 #size-cells = <0>; 4651 4652 port@0 { 4653 reg = <0>; 4654 4655 mdss_dp1_in: endpoint { 4656 remote-endpoint = <&mdss_intf4_out>; 4657 }; 4658 }; 4659 4660 port@1 { 4661 reg = <1>; 4662 4663 mdss_dp1_out: endpoint { 4664 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4665 }; 4666 }; 4667 }; 4668 }; 4669 4670 mdss_dp2: displayport-controller@af64000 { 4671 compatible = "qcom,glymur-dp"; 4672 reg = <0x0 0x0af64000 0x0 0x200>, 4673 <0x0 0x0af64200 0x0 0x200>, 4674 <0x0 0x0af65000 0x0 0xc00>, 4675 <0x0 0x0af66000 0x0 0x400>, 4676 <0x0 0x0af67000 0x0 0x400>, 4677 <0x0 0x0af68000 0x0 0x400>, 4678 <0x0 0x0af69000 0x0 0x400>, 4679 <0x0 0x0af6a000 0x0 0x600>, 4680 <0x0 0x0af6b000 0x0 0x600>; 4681 4682 interrupts-extended = <&mdss 14>; 4683 4684 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4685 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4686 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4687 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4688 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 4689 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 4690 clock-names = "core_iface", 4691 "core_aux", 4692 "ctrl_link", 4693 "ctrl_link_iface", 4694 "stream_pixel", 4695 "stream_1_pixel"; 4696 4697 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4698 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 4699 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 4700 assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4701 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4702 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4703 4704 operating-points-v2 = <&mdss_dp0_opp_table>; 4705 4706 power-domains = <&rpmhpd RPMHPD_MMCX>; 4707 4708 phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; 4709 phy-names = "dp"; 4710 4711 #sound-dai-cells = <0>; 4712 4713 status = "disabled"; 4714 4715 ports { 4716 #address-cells = <1>; 4717 #size-cells = <0>; 4718 4719 port@0 { 4720 reg = <0>; 4721 mdss_dp2_in: endpoint { 4722 remote-endpoint = <&mdss_intf6_out>; 4723 }; 4724 }; 4725 4726 port@1 { 4727 reg = <1>; 4728 4729 mdss_dp2_out: endpoint { 4730 remote-endpoint = <&usb_2_qmpphy_dp_in>; 4731 }; 4732 }; 4733 }; 4734 }; 4735 4736 mdss_dp3: displayport-controller@af6c000 { 4737 compatible = "qcom,glymur-dp"; 4738 reg = <0x0 0x0af6c000 0x0 0x200>, 4739 <0x0 0x0af6c200 0x0 0x200>, 4740 <0x0 0x0af6d000 0x0 0xc00>, 4741 <0x0 0x0af6e000 0x0 0x400>, 4742 <0x0 0x0af6f000 0x0 0x400>, 4743 <0x0 0x0af70000 0x0 0x400>, 4744 <0x0 0x0af71000 0x0 0x400>, 4745 <0x0 0x0af72000 0x0 0x600>, 4746 <0x0 0x0af73000 0x0 0x600>; 4747 4748 interrupts-extended = <&mdss 15>; 4749 4750 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4751 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4752 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4753 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4754 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4755 clock-names = "core_iface", 4756 "core_aux", 4757 "ctrl_link", 4758 "ctrl_link_iface", 4759 "stream_pixel"; 4760 4761 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4762 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4763 assigned-clock-parents = <&mdss_dp3_phy 0>, 4764 <&mdss_dp3_phy 1>; 4765 4766 operating-points-v2 = <&mdss_dp0_opp_table>; 4767 4768 power-domains = <&rpmhpd RPMHPD_MMCX>; 4769 4770 phys = <&mdss_dp3_phy>; 4771 phy-names = "dp"; 4772 4773 #sound-dai-cells = <0>; 4774 4775 status = "disabled"; 4776 4777 ports { 4778 #address-cells = <1>; 4779 #size-cells = <0>; 4780 4781 port@0 { 4782 reg = <0>; 4783 4784 mdss_dp3_in: endpoint { 4785 remote-endpoint = <&mdss_intf5_out>; 4786 }; 4787 }; 4788 4789 port@1 { 4790 reg = <1>; 4791 4792 mdss_dp3_out: endpoint { 4793 }; 4794 }; 4795 }; 4796 }; 4797 }; 4798 4799 videocc: clock-controller@aaf0000 { 4800 compatible = "qcom,glymur-videocc"; 4801 reg = <0x0 0x0aaf0000 0x0 0x10000>; 4802 clocks = <&rpmhcc RPMH_CXO_CLK>, 4803 <&rpmhcc RPMH_CXO_CLK_A>; 4804 4805 power-domains = <&rpmhpd RPMHPD_MMCX>, 4806 <&rpmhpd RPMHPD_MXC>; 4807 required-opps = <&rpmhpd_opp_low_svs>, 4808 <&rpmhpd_opp_low_svs>; 4809 4810 #clock-cells = <1>; 4811 #reset-cells = <1>; 4812 #power-domain-cells = <1>; 4813 }; 4814 4815 dispcc: clock-controller@af00000 { 4816 compatible = "qcom,glymur-dispcc"; 4817 reg = <0x0 0x0af00000 0x0 0x20000>; 4818 clocks = <&rpmhcc RPMH_CXO_CLK>, 4819 <&sleep_clk>, 4820 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4821 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4822 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4823 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4824 <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 4825 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4826 <&mdss_dp3_phy 0>, /* dp3 */ 4827 <&mdss_dp3_phy 1>, 4828 <0>, /* dsi0 */ 4829 <0>, 4830 <0>, /* dsi1 */ 4831 <0>, 4832 <0>, 4833 <0>, 4834 <0>, 4835 <0>; 4836 power-domains = <&rpmhpd RPMHPD_MMCX>; 4837 required-opps = <&rpmhpd_opp_low_svs>; 4838 #clock-cells = <1>; 4839 #reset-cells = <1>; 4840 #power-domain-cells = <1>; 4841 }; 4842 4843 pdc: interrupt-controller@b220000 { 4844 compatible = "qcom,glymur-pdc", "qcom,pdc"; 4845 reg = <0x0 0x0b220000 0x0 0x10000>; 4846 qcom,pdc-ranges = <0 745 51>, 4847 <51 527 47>, 4848 <98 609 32>, 4849 <130 717 12>, 4850 <142 251 5>, 4851 <147 796 16>, 4852 <171 4104 36>; 4853 #interrupt-cells = <2>; 4854 interrupt-parent = <&intc>; 4855 interrupt-controller; 4856 }; 4857 4858 tsens0: thermal-sensor@c22c000 { 4859 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4860 reg = <0x0 0x0c22c000 0x0 0x1000>, 4861 <0x0 0x0c222000 0x0 0x1000>; 4862 4863 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 4864 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 4865 interrupt-names = "uplow", 4866 "critical"; 4867 4868 #qcom,sensors = <13>; 4869 4870 #thermal-sensor-cells = <1>; 4871 }; 4872 4873 tsens1: thermal-sensor@c22d000 { 4874 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4875 reg = <0x0 0x0c22d000 0x0 0x1000>, 4876 <0x0 0x0c223000 0x0 0x1000>; 4877 4878 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 4879 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 4880 interrupt-names = "uplow", 4881 "critical"; 4882 4883 #qcom,sensors = <9>; 4884 4885 #thermal-sensor-cells = <1>; 4886 }; 4887 4888 tsens2: thermal-sensor@c22e000 { 4889 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4890 reg = <0x0 0x0c22e000 0x0 0x1000>, 4891 <0x0 0x0c224000 0x0 0x1000>; 4892 4893 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 4894 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 4895 interrupt-names = "uplow", 4896 "critical"; 4897 4898 #qcom,sensors = <13>; 4899 4900 #thermal-sensor-cells = <1>; 4901 }; 4902 4903 tsens3: thermal-sensor@c22f000 { 4904 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4905 reg = <0x0 0x0c22f000 0x0 0x1000>, 4906 <0x0 0x0c225000 0x0 0x1000>; 4907 4908 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 4909 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 4910 interrupt-names = "uplow", 4911 "critical"; 4912 4913 #qcom,sensors = <8>; 4914 4915 #thermal-sensor-cells = <1>; 4916 }; 4917 4918 tsens4: thermal-sensor@c230000 { 4919 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4920 reg = <0x0 0x0c230000 0x0 0x1000>, 4921 <0x0 0x0c226000 0x0 0x1000>; 4922 4923 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4924 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4925 interrupt-names = "uplow", 4926 "critical"; 4927 4928 #qcom,sensors = <13>; 4929 4930 #thermal-sensor-cells = <1>; 4931 }; 4932 4933 tsens5: thermal-sensor@c231000 { 4934 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4935 reg = <0x0 0x0c231000 0x0 0x1000>, 4936 <0x0 0x0c227000 0x0 0x1000>; 4937 4938 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 4940 interrupt-names = "uplow", 4941 "critical"; 4942 4943 #qcom,sensors = <8>; 4944 4945 #thermal-sensor-cells = <1>; 4946 }; 4947 4948 tsens6: thermal-sensor@c232000 { 4949 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4950 reg = <0x0 0x0c232000 0x0 0x1000>, 4951 <0x0 0x0c228000 0x0 0x1000>; 4952 4953 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 4954 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 4955 interrupt-names = "uplow", 4956 "critical"; 4957 4958 #qcom,sensors = <13>; 4959 4960 #thermal-sensor-cells = <1>; 4961 }; 4962 4963 tsens7: thermal-sensor@c233000 { 4964 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4965 reg = <0x0 0x0c233000 0x0 0x1000>, 4966 <0x0 0x0c229000 0x0 0x1000>; 4967 4968 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 4970 interrupt-names = "uplow", 4971 "critical"; 4972 4973 #qcom,sensors = <15>; 4974 4975 #thermal-sensor-cells = <1>; 4976 }; 4977 4978 aoss_qmp: power-management@c300000 { 4979 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 4980 reg = <0x0 0x0c300000 0x0 0x400>; 4981 interrupt-parent = <&ipcc>; 4982 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4983 IRQ_TYPE_EDGE_RISING>; 4984 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4985 4986 #clock-cells = <0>; 4987 }; 4988 4989 sram@c30f000 { 4990 compatible = "qcom,rpmh-stats"; 4991 reg = <0x0 0x0c30f000 0x0 0x400>; 4992 }; 4993 4994 arbiter@c400000 { 4995 compatible = "qcom,glymur-spmi-pmic-arb"; 4996 reg = <0x0 0x0c400000 0x0 0x3000>, 4997 <0x0 0x0c900000 0x0 0x400000>, 4998 <0x0 0x0c4c0000 0x0 0x400000>, 4999 <0x0 0x0c403000 0x0 0x8000>; 5000 reg-names = "core", 5001 "chnls", 5002 "obsrvr", 5003 "chnl_map"; 5004 #address-cells = <2>; 5005 #size-cells = <2>; 5006 ranges; 5007 qcom,channel = <0>; 5008 qcom,ee = <0>; 5009 5010 spmi_bus0: spmi@c426000 { 5011 reg = <0x0 0x0c426000 0x0 0x4000>, 5012 <0x0 0x0c8c0000 0x0 0x10000>, 5013 <0x0 0x0c42a000 0x0 0x8000>; 5014 reg-names = "cnfg", 5015 "intr", 5016 "chnl_owner"; 5017 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5018 interrupt-names = "periph_irq"; 5019 interrupt-controller; 5020 #interrupt-cells = <4>; 5021 #address-cells = <2>; 5022 #size-cells = <0>; 5023 }; 5024 5025 spmi_bus1: spmi@c437000 { 5026 reg = <0x0 0x0c437000 0x0 0x4000>, 5027 <0x0 0x0c8d0000 0x0 0x10000>, 5028 <0x0 0x0c43b000 0x0 0x8000>; 5029 reg-names = "cnfg", 5030 "intr", 5031 "chnl_owner"; 5032 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5033 interrupt-names = "periph_irq"; 5034 interrupt-controller; 5035 #interrupt-cells = <4>; 5036 #address-cells = <2>; 5037 #size-cells = <0>; 5038 }; 5039 5040 spmi_bus2: spmi@c48000 { 5041 reg = <0x0 0x0c448000 0x0 0x4000>, 5042 <0x0 0x0c8e0000 0x0 0x10000>, 5043 <0x0 0x0c44c000 0x0 0x8000>; 5044 reg-names = "cnfg", 5045 "intr", 5046 "chnl_owner"; 5047 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 5048 interrupt-names = "periph_irq"; 5049 interrupt-controller; 5050 #interrupt-cells = <4>; 5051 #address-cells = <2>; 5052 #size-cells = <0>; 5053 }; 5054 }; 5055 5056 tlmm: pinctrl@f100000 { 5057 compatible = "qcom,glymur-tlmm"; 5058 reg = <0x0 0x0f100000 0x0 0xf00000>; 5059 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5060 gpio-controller; 5061 #gpio-cells = <2>; 5062 interrupt-controller; 5063 #interrupt-cells = <2>; 5064 gpio-ranges = <&tlmm 0 0 249>; 5065 wakeup-parent = <&pdc>; 5066 5067 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5068 /* SDA, SCL */ 5069 pins = "gpio0", "gpio1"; 5070 function = "qup0_se0"; 5071 drive-strength = <2>; 5072 bias-pull-up = <2200>; 5073 }; 5074 5075 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5076 /* SDA, SCL */ 5077 pins = "gpio4", "gpio5"; 5078 function = "qup0_se1"; 5079 drive-strength = <2>; 5080 bias-pull-up = <2200>; 5081 }; 5082 5083 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5084 /* SDA, SCL */ 5085 pins = "gpio8", "gpio9"; 5086 function = "qup0_se2"; 5087 drive-strength = <2>; 5088 bias-pull-up = <2200>; 5089 }; 5090 5091 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5092 /* SDA, SCL */ 5093 pins = "gpio12", "gpio13"; 5094 function = "qup0_se3"; 5095 drive-strength = <2>; 5096 bias-pull-up = <2200>; 5097 }; 5098 5099 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5100 /* SDA, SCL */ 5101 pins = "gpio16", "gpio17"; 5102 function = "qup0_se4"; 5103 drive-strength = <2>; 5104 bias-pull-up = <2200>; 5105 }; 5106 5107 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5108 /* SDA, SCL */ 5109 pins = "gpio20", "gpio21"; 5110 function = "qup0_se5"; 5111 drive-strength = <2>; 5112 bias-pull-up = <2200>; 5113 }; 5114 5115 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5116 /* SDA, SCL */ 5117 pins = "gpio6", "gpio7"; 5118 function = "qup0_se6"; 5119 drive-strength = <2>; 5120 bias-pull-up = <2200>; 5121 }; 5122 5123 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5124 /* SDA, SCL */ 5125 pins = "gpio14", "gpio15"; 5126 function = "qup0_se7"; 5127 drive-strength = <2>; 5128 bias-pull-up = <2200>; 5129 }; 5130 5131 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5132 /* SDA, SCL */ 5133 pins = "gpio32", "gpio33"; 5134 function = "qup1_se0"; 5135 drive-strength = <2>; 5136 bias-pull-up = <2200>; 5137 }; 5138 5139 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5140 /* SDA, SCL */ 5141 pins = "gpio36", "gpio37"; 5142 function = "qup1_se1"; 5143 drive-strength = <2>; 5144 bias-pull-up = <2200>; 5145 }; 5146 5147 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5148 /* SDA, SCL */ 5149 pins = "gpio40", "gpio41"; 5150 function = "qup1_se2"; 5151 drive-strength = <2>; 5152 bias-pull-up = <2200>; 5153 }; 5154 5155 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5156 /* SDA, SCL */ 5157 pins = "gpio44", "gpio45"; 5158 function = "qup1_se3"; 5159 drive-strength = <2>; 5160 bias-pull-up = <2200>; 5161 }; 5162 5163 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5164 /* SDA, SCL */ 5165 pins = "gpio48", "gpio49"; 5166 function = "qup1_se4"; 5167 drive-strength = <2>; 5168 bias-pull-up = <2200>; 5169 }; 5170 5171 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5172 /* SDA, SCL */ 5173 pins = "gpio52", "gpio53"; 5174 function = "qup1_se5"; 5175 drive-strength = <2>; 5176 bias-pull-up = <2200>; 5177 }; 5178 5179 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5180 /* SDA, SCL */ 5181 pins = "gpio56", "gpio57"; 5182 function = "qup1_se6"; 5183 drive-strength = <2>; 5184 bias-pull-up = <2200>; 5185 }; 5186 5187 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5188 /* SDA, SCL */ 5189 pins = "gpio54", "gpio55"; 5190 function = "qup1_se7"; 5191 drive-strength = <2>; 5192 bias-pull-up = <2200>; 5193 }; 5194 5195 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5196 /* SDA, SCL */ 5197 pins = "gpio64", "gpio65"; 5198 function = "qup2_se0"; 5199 drive-strength = <2>; 5200 bias-pull-up = <2200>; 5201 }; 5202 5203 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5204 /* SDA, SCL */ 5205 pins = "gpio68", "gpio69"; 5206 function = "qup2_se1"; 5207 drive-strength = <2>; 5208 bias-pull-up = <2200>; 5209 }; 5210 5211 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5212 /* SDA, SCL */ 5213 pins = "gpio72", "gpio73"; 5214 function = "qup2_se2"; 5215 drive-strength = <2>; 5216 bias-pull-up = <2200>; 5217 }; 5218 5219 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5220 /* SDA, SCL */ 5221 pins = "gpio76", "gpio77"; 5222 function = "qup2_se3"; 5223 drive-strength = <2>; 5224 bias-pull-up = <2200>; 5225 }; 5226 5227 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5228 /* SDA, SCL */ 5229 pins = "gpio80", "gpio81"; 5230 function = "qup2_se4"; 5231 drive-strength = <2>; 5232 bias-pull-up = <2200>; 5233 }; 5234 5235 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5236 /* SDA, SCL */ 5237 pins = "gpio84", "gpio85"; 5238 function = "qup2_se5"; 5239 drive-strength = <2>; 5240 bias-pull-up = <2200>; 5241 }; 5242 5243 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5244 /* SDA, SCL */ 5245 pins = "gpio88", "gpio89"; 5246 function = "qup2_se6"; 5247 drive-strength = <2>; 5248 bias-pull-up = <2200>; 5249 }; 5250 5251 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5252 /* SDA, SCL */ 5253 pins = "gpio80", "gpio81"; 5254 function = "qup2_se7"; 5255 drive-strength = <2>; 5256 bias-pull-up = <2200>; 5257 }; 5258 5259 qup_spi0_cs: qup-spi0-cs-state { 5260 pins = "gpio3"; 5261 function = "qup0_se0"; 5262 drive-strength = <6>; 5263 bias-disable; 5264 }; 5265 5266 qup_spi0_data_clk: qup-spi0-data-clk-state { 5267 /* MISO, MOSI, CLK */ 5268 pins = "gpio0", "gpio1", "gpio2"; 5269 function = "qup0_se0"; 5270 drive-strength = <6>; 5271 bias-disable; 5272 }; 5273 5274 qup_spi1_cs: qup-spi1-cs-state { 5275 pins = "gpio7"; 5276 function = "qup0_se1"; 5277 drive-strength = <6>; 5278 bias-disable; 5279 }; 5280 5281 qup_spi1_data_clk: qup-spi1-data-clk-state { 5282 /* MISO, MOSI, CLK */ 5283 pins = "gpio4", "gpio5", "gpio6"; 5284 function = "qup0_se1"; 5285 drive-strength = <6>; 5286 bias-disable; 5287 }; 5288 5289 qup_spi2_cs: qup-spi2-cs-state { 5290 pins = "gpio11"; 5291 function = "qup0_se2"; 5292 drive-strength = <6>; 5293 bias-disable; 5294 }; 5295 5296 qup_spi2_data_clk: qup-spi2-data-clk-state { 5297 /* MISO, MOSI, CLK */ 5298 pins = "gpio8", "gpio9", "gpio10"; 5299 function = "qup0_se2"; 5300 drive-strength = <6>; 5301 bias-disable; 5302 }; 5303 5304 qup_spi3_cs: qup-spi3-cs-state { 5305 pins = "gpio15"; 5306 function = "qup0_se3"; 5307 drive-strength = <6>; 5308 bias-disable; 5309 }; 5310 5311 qup_spi3_data_clk: qup-spi3-data-clk-state { 5312 /* MISO, MOSI, CLK */ 5313 pins = "gpio12", "gpio13", "gpio14"; 5314 function = "qup0_se3"; 5315 drive-strength = <6>; 5316 bias-disable; 5317 }; 5318 5319 qup_spi4_cs: qup-spi4-cs-state { 5320 pins = "gpio19"; 5321 function = "qup0_se4"; 5322 drive-strength = <6>; 5323 bias-disable; 5324 }; 5325 5326 qup_spi4_data_clk: qup-spi4-data-clk-state { 5327 /* MISO, MOSI, CLK */ 5328 pins = "gpio16", "gpio17", "gpio18"; 5329 function = "qup0_se4"; 5330 drive-strength = <6>; 5331 bias-disable; 5332 }; 5333 5334 qup_spi5_cs: qup-spi5-cs-state { 5335 pins = "gpio23"; 5336 function = "qup0_se5"; 5337 drive-strength = <6>; 5338 bias-disable; 5339 }; 5340 5341 qup_spi5_data_clk: qup-spi5-data-clk-state { 5342 /* MISO, MOSI, CLK */ 5343 pins = "gpio20", "gpio21", "gpio22"; 5344 function = "qup0_se5"; 5345 drive-strength = <6>; 5346 bias-disable; 5347 }; 5348 5349 qup_spi6_cs: qup-spi6-cs-state { 5350 pins = "gpio5"; 5351 function = "qup0_se6"; 5352 drive-strength = <6>; 5353 bias-disable; 5354 }; 5355 5356 qup_spi6_data_clk: qup-spi6-data-clk-state { 5357 /* MISO, MOSI, CLK */ 5358 pins = "gpio6", "gpio7", "gpio4"; 5359 function = "qup0_se6"; 5360 drive-strength = <6>; 5361 bias-disable; 5362 }; 5363 5364 qup_spi7_cs: qup-spi7-cs-state { 5365 pins = "gpio13"; 5366 function = "qup0_se7"; 5367 drive-strength = <6>; 5368 bias-disable; 5369 }; 5370 5371 qup_spi7_data_clk: qup-spi7-data-clk-state { 5372 /* MISO, MOSI, CLK */ 5373 pins = "gpio14", "gpio15", "gpio12"; 5374 function = "qup0_se7"; 5375 drive-strength = <6>; 5376 bias-disable; 5377 }; 5378 5379 qup_spi8_cs: qup-spi8-cs-state { 5380 pins = "gpio35"; 5381 function = "qup1_se0"; 5382 drive-strength = <6>; 5383 bias-disable; 5384 }; 5385 5386 qup_spi8_data_clk: qup-spi8-data-clk-state { 5387 /* MISO, MOSI, CLK */ 5388 pins = "gpio32", "gpio33", "gpio34"; 5389 function = "qup1_se0"; 5390 drive-strength = <6>; 5391 bias-disable; 5392 }; 5393 5394 qup_spi9_cs: qup-spi9-cs-state { 5395 pins = "gpio39"; 5396 function = "qup1_se1"; 5397 drive-strength = <6>; 5398 bias-disable; 5399 }; 5400 5401 qup_spi9_data_clk: qup-spi9-data-clk-state { 5402 /* MISO, MOSI, CLK */ 5403 pins = "gpio36", "gpio37", "gpio38"; 5404 function = "qup1_se1"; 5405 drive-strength = <6>; 5406 bias-disable; 5407 }; 5408 5409 qup_spi10_cs: qup-spi10-cs-state { 5410 pins = "gpio43"; 5411 function = "qup1_se2"; 5412 drive-strength = <6>; 5413 bias-disable; 5414 }; 5415 5416 qup_spi10_data_clk: qup-spi10-data-clk-state { 5417 /* MISO, MOSI, CLK */ 5418 pins = "gpio40", "gpio41", "gpio42"; 5419 function = "qup1_se2"; 5420 drive-strength = <6>; 5421 bias-disable; 5422 }; 5423 5424 qup_spi11_cs: qup-spi11-cs-state { 5425 pins = "gpio47"; 5426 function = "qup1_se3"; 5427 drive-strength = <6>; 5428 bias-disable; 5429 }; 5430 5431 qup_spi11_data_clk: qup-spi11-data-clk-state { 5432 pins = "gpio44", "gpio45", "gpio46"; 5433 function = "qup1_se3"; 5434 drive-strength = <6>; 5435 bias-disable; 5436 }; 5437 5438 qup_spi12_cs: qup-spi12-cs-state { 5439 pins = "gpio51"; 5440 function = "qup1_se4"; 5441 drive-strength = <6>; 5442 bias-disable; 5443 }; 5444 5445 qup_spi12_data_clk: qup-spi12-data-clk-state { 5446 /* MISO, MOSI, CLK */ 5447 pins = "gpio48", "gpio49", "gpio50"; 5448 function = "qup1_se4"; 5449 drive-strength = <6>; 5450 bias-disable; 5451 }; 5452 5453 qup_spi13_cs: qup-spi13-cs-state { 5454 pins = "gpio55"; 5455 function = "qup1_se5"; 5456 drive-strength = <6>; 5457 bias-disable; 5458 }; 5459 5460 qup_spi13_data_clk: qup-spi13-data-clk-state { 5461 /* MISO, MOSI, CLK */ 5462 pins = "gpio52", "gpio53", "gpio54"; 5463 function = "qup1_se5"; 5464 drive-strength = <6>; 5465 bias-disable; 5466 }; 5467 5468 qup_spi14_cs: qup-spi14-cs-state { 5469 pins = "gpio59"; 5470 function = "qup1_se6"; 5471 drive-strength = <6>; 5472 bias-disable; 5473 }; 5474 5475 qup_spi14_data_clk: qup-spi14-data-clk-state { 5476 /* MISO, MOSI, CLK */ 5477 pins = "gpio56", "gpio57", "gpio58"; 5478 function = "qup1_se6"; 5479 drive-strength = <6>; 5480 bias-disable; 5481 }; 5482 5483 qup_spi15_cs: qup-spi15-cs-state { 5484 pins = "gpio53"; 5485 function = "qup1_se7"; 5486 drive-strength = <6>; 5487 bias-disable; 5488 }; 5489 5490 qup_spi15_data_clk: qup-spi15-data-clk-state { 5491 /* MISO, MOSI, CLK */ 5492 pins = "gpio54", "gpio55", "gpio52"; 5493 function = "qup1_se7"; 5494 drive-strength = <6>; 5495 bias-disable; 5496 }; 5497 5498 qup_spi16_cs: qup-spi16-cs-state { 5499 pins = "gpio67"; 5500 function = "qup2_se0"; 5501 drive-strength = <6>; 5502 bias-disable; 5503 }; 5504 5505 qup_spi16_data_clk: qup-spi16-data-clk-state { 5506 /* MISO, MOSI, CLK */ 5507 pins = "gpio64", "gpio65", "gpio66"; 5508 function = "qup2_se0"; 5509 drive-strength = <6>; 5510 bias-disable; 5511 }; 5512 5513 qup_spi17_cs: qup-spi17-cs-state { 5514 pins = "gpio71"; 5515 function = "qup2_se1"; 5516 drive-strength = <6>; 5517 bias-disable; 5518 }; 5519 5520 qup_spi17_data_clk: qup-spi17-data-clk-state { 5521 /* MISO, MOSI, CLK */ 5522 pins = "gpio68", "gpio69", "gpio70"; 5523 function = "qup2_se1"; 5524 drive-strength = <6>; 5525 bias-disable; 5526 }; 5527 5528 qup_spi18_cs: qup-spi18-cs-state { 5529 pins = "gpio75"; 5530 function = "qup2_se2"; 5531 drive-strength = <6>; 5532 bias-disable; 5533 }; 5534 5535 qup_spi18_data_clk: qup-spi18-data-clk-state { 5536 /* MISO, MOSI, CLK */ 5537 pins = "gpio72", "gpio73", "gpio74"; 5538 function = "qup2_se2"; 5539 drive-strength = <6>; 5540 bias-disable; 5541 }; 5542 5543 qup_spi19_cs: qup-spi19-cs-state { 5544 pins = "gpio79"; 5545 function = "qup2_se3"; 5546 drive-strength = <6>; 5547 bias-disable; 5548 }; 5549 5550 qup_spi19_data_clk: qup-spi19-data-clk-state { 5551 /* MISO, MOSI, CLK */ 5552 pins = "gpio76", "gpio77", "gpio78"; 5553 function = "qup2_se3"; 5554 drive-strength = <6>; 5555 bias-disable; 5556 }; 5557 5558 qup_spi20_cs: qup-spi20-cs-state { 5559 pins = "gpio83"; 5560 function = "qup2_se4"; 5561 drive-strength = <6>; 5562 bias-disable; 5563 }; 5564 5565 qup_spi20_data_clk: qup-spi20-data-clk-state { 5566 /* MISO, MOSI, CLK */ 5567 pins = "gpio80", "gpio81", "gpio82"; 5568 function = "qup2_se4"; 5569 drive-strength = <6>; 5570 bias-disable; 5571 }; 5572 5573 qup_spi21_cs: qup-spi21-cs-state { 5574 pins = "gpio87"; 5575 function = "qup2_se5"; 5576 drive-strength = <6>; 5577 bias-disable; 5578 }; 5579 5580 qup_spi21_data_clk: qup-spi21-data-clk-state { 5581 /* MISO, MOSI, CLK */ 5582 pins = "gpio84", "gpio85", "gpio86"; 5583 function = "qup2_se5"; 5584 drive-strength = <6>; 5585 bias-disable; 5586 }; 5587 5588 qup_spi22_cs: qup-spi22-cs-state { 5589 pins = "gpio91"; 5590 function = "qup2_se6"; 5591 drive-strength = <6>; 5592 bias-disable; 5593 }; 5594 5595 qup_spi22_data_clk: qup-spi22-data-clk-state { 5596 /* MISO, MOSI, CLK */ 5597 pins = "gpio88", "gpio89", "gpio90"; 5598 function = "qup2_se6"; 5599 drive-strength = <6>; 5600 bias-disable; 5601 }; 5602 5603 qup_spi23_cs: qup-spi23-cs-state { 5604 pins = "gpio83"; 5605 function = "qup2_se7"; 5606 drive-strength = <6>; 5607 bias-disable; 5608 }; 5609 5610 qup_spi23_data_clk: qup-spi23-data-clk-state { 5611 /* MISO, MOSI, CLK */ 5612 pins = "gpio80", "gpio81", "gpio82"; 5613 function = "qup2_se7"; 5614 drive-strength = <6>; 5615 bias-disable; 5616 }; 5617 5618 qup_uart2_default: qup-uart2-default-state { 5619 tx-pins { 5620 pins = "gpio10"; 5621 function = "qup0_se2"; 5622 drive-strength = <2>; 5623 bias-disable; 5624 }; 5625 5626 rx-pins { 5627 pins = "gpio11"; 5628 function = "qup0_se2"; 5629 drive-strength = <2>; 5630 bias-disable; 5631 }; 5632 }; 5633 5634 qup_uart14_default: qup-uart14-default-state { 5635 cts-pins { 5636 pins = "gpio56"; 5637 function = "qup1_se6"; 5638 drive-strength = <2>; 5639 bias-disable; 5640 }; 5641 5642 rts-pins { 5643 pins = "gpio57"; 5644 function = "qup1_se6"; 5645 drive-strength = <2>; 5646 bias-disable; 5647 }; 5648 5649 tx-pins { 5650 pins = "gpio58"; 5651 function = "qup1_se6"; 5652 drive-strength = <2>; 5653 bias-disable; 5654 }; 5655 5656 rx-pins { 5657 pins = "gpio59"; 5658 function = "qup1_se6"; 5659 drive-strength = <2>; 5660 bias-disable; 5661 }; 5662 }; 5663 5664 qup_uart19_default: qup-uart19-default-state { 5665 cts-pins { 5666 pins = "gpio76"; 5667 function = "qup2_se3"; 5668 drive-strength = <2>; 5669 bias-disable; 5670 }; 5671 5672 rts-pins { 5673 pins = "gpio77"; 5674 function = "qup2_se3"; 5675 drive-strength = <2>; 5676 bias-disable; 5677 }; 5678 5679 tx-pins { 5680 pins = "gpio78"; 5681 function = "qup2_se3"; 5682 drive-strength = <2>; 5683 bias-disable; 5684 }; 5685 5686 rx-pins { 5687 pins = "gpio79"; 5688 function = "qup2_se3"; 5689 drive-strength = <2>; 5690 bias-disable; 5691 }; 5692 }; 5693 5694 qup_uart21_default: qup-uart21-default-state { 5695 tx-pins { 5696 pins = "gpio86"; 5697 function = "qup2_se5"; 5698 drive-strength = <2>; 5699 bias-disable; 5700 }; 5701 5702 rx-pins { 5703 pins = "gpio87"; 5704 function = "qup2_se5"; 5705 drive-strength = <2>; 5706 bias-disable; 5707 }; 5708 }; 5709 5710 qup_uart22_default: qup-uart22-default-state { 5711 tx-pins { 5712 pins = "gpio90"; 5713 function = "qup2_se6"; 5714 drive-strength = <2>; 5715 bias-disable; 5716 }; 5717 5718 rx-pins { 5719 pins = "gpio91"; 5720 function = "qup2_se6"; 5721 drive-strength = <2>; 5722 bias-disable; 5723 }; 5724 }; 5725 }; 5726 5727 stm: stm@10002000 { 5728 compatible = "arm,coresight-stm", "arm,primecell"; 5729 reg = <0x0 0x10002000 0x0 0x1000>, 5730 <0x0 0x16280000 0x0 0x180000>; 5731 reg-names = "stm-base", 5732 "stm-stimulus-base"; 5733 5734 clocks = <&aoss_qmp>; 5735 clock-names = "apb_pclk"; 5736 5737 out-ports { 5738 port { 5739 stm_out: endpoint { 5740 remote-endpoint = <&funnel0_in7>; 5741 }; 5742 }; 5743 }; 5744 }; 5745 5746 tpda@10004000 { 5747 compatible = "qcom,coresight-tpda", "arm,primecell"; 5748 reg = <0x0 0x10004000 0x0 0x1000>; 5749 5750 clocks = <&aoss_qmp>; 5751 clock-names = "apb_pclk"; 5752 5753 in-ports { 5754 #address-cells = <1>; 5755 #size-cells = <0>; 5756 5757 port@1 { 5758 reg = <1>; 5759 5760 qdss_tpda_in1: endpoint { 5761 remote-endpoint = <&spdm_tpdm_out>; 5762 }; 5763 }; 5764 }; 5765 5766 out-ports { 5767 port { 5768 qdss_tpda_out: endpoint { 5769 remote-endpoint = <&funnel0_in6>; 5770 }; 5771 }; 5772 }; 5773 }; 5774 5775 tpdm@1000f000 { 5776 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5777 reg = <0x0 0x1000f000 0x0 0x1000>; 5778 5779 clocks = <&aoss_qmp>; 5780 clock-names = "apb_pclk"; 5781 5782 qcom,cmb-element-bits = <32>; 5783 qcom,cmb-msrs-num = <32>; 5784 5785 out-ports { 5786 port { 5787 spdm_tpdm_out: endpoint { 5788 remote-endpoint = <&qdss_tpda_in1>; 5789 }; 5790 }; 5791 }; 5792 }; 5793 5794 funnel@10041000 { 5795 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5796 reg = <0x0 0x10041000 0x0 0x1000>; 5797 5798 clocks = <&aoss_qmp>; 5799 clock-names = "apb_pclk"; 5800 5801 in-ports { 5802 #address-cells = <1>; 5803 #size-cells = <0>; 5804 5805 port@0 { 5806 reg = <0>; 5807 5808 funnel0_in0: endpoint { 5809 remote-endpoint = <&tn_ag_out>; 5810 }; 5811 }; 5812 5813 port@6 { 5814 reg = <6>; 5815 5816 funnel0_in6: endpoint { 5817 remote-endpoint = <&qdss_tpda_out>; 5818 }; 5819 }; 5820 5821 port@7 { 5822 reg = <7>; 5823 5824 funnel0_in7: endpoint { 5825 remote-endpoint = <&stm_out>; 5826 }; 5827 }; 5828 }; 5829 5830 out-ports { 5831 port { 5832 funnel0_out: endpoint { 5833 remote-endpoint = <&aoss_funnel_in6>; 5834 }; 5835 }; 5836 }; 5837 }; 5838 5839 tpdm@1102c000 { 5840 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5841 reg = <0x0 0x1102c000 0x0 0x1000>; 5842 5843 clocks = <&aoss_qmp>; 5844 clock-names = "apb_pclk"; 5845 5846 qcom,dsb-msrs-num = <32>; 5847 5848 out-ports { 5849 port { 5850 gcc_tpdm_out: endpoint { 5851 remote-endpoint = <&tn_ag_in36>; 5852 }; 5853 }; 5854 }; 5855 }; 5856 5857 tpdm@11180000 { 5858 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5859 reg = <0x0 0x11180000 0x0 0x1000>; 5860 5861 clocks = <&aoss_qmp>; 5862 clock-names = "apb_pclk"; 5863 5864 qcom,dsb-element-bits = <32>; 5865 qcom,dsb-msrs-num = <32>; 5866 5867 out-ports { 5868 port { 5869 cdsp_tpdm_out: endpoint { 5870 remote-endpoint = <&cdsp_tpda_in0>; 5871 }; 5872 }; 5873 }; 5874 }; 5875 5876 tpdm@11185000 { 5877 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5878 reg = <0x0 0x11185000 0x0 0x1000>; 5879 5880 clocks = <&aoss_qmp>; 5881 clock-names = "apb_pclk"; 5882 5883 qcom,cmb-element-bits = <64>; 5884 qcom,cmb-msrs-num = <32>; 5885 5886 out-ports { 5887 port { 5888 cdsp_dpm1_tpdm_out: endpoint { 5889 remote-endpoint = <&cdsp_tpda_in5>; 5890 }; 5891 }; 5892 }; 5893 }; 5894 5895 tpdm@11186000 { 5896 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5897 reg = <0x0 0x11186000 0x0 0x1000>; 5898 5899 clocks = <&aoss_qmp>; 5900 clock-names = "apb_pclk"; 5901 5902 qcom,cmb-element-bits = <64>; 5903 qcom,cmb-msrs-num = <32>; 5904 5905 out-ports { 5906 port { 5907 cdsp_dpm2_tpdm_out: endpoint { 5908 remote-endpoint = <&cdsp_tpda_in6>; 5909 }; 5910 }; 5911 }; 5912 }; 5913 5914 tpda@11188000 { 5915 compatible = "qcom,coresight-tpda", "arm,primecell"; 5916 reg = <0x0 0x11188000 0x0 0x1000>; 5917 5918 clocks = <&aoss_qmp>; 5919 clock-names = "apb_pclk"; 5920 5921 in-ports { 5922 #address-cells = <1>; 5923 #size-cells = <0>; 5924 5925 port@0 { 5926 reg = <0>; 5927 5928 cdsp_tpda_in0: endpoint { 5929 remote-endpoint = <&cdsp_tpdm_out>; 5930 }; 5931 }; 5932 5933 port@1 { 5934 reg = <1>; 5935 5936 cdsp_tpda_in1: endpoint { 5937 remote-endpoint = <&cdsp_llm_tpdm_out>; 5938 }; 5939 }; 5940 5941 port@2 { 5942 reg = <2>; 5943 5944 cdsp_tpda_in2: endpoint { 5945 remote-endpoint = <&cdsp_llm2_tpdm_out>; 5946 }; 5947 }; 5948 5949 port@3 { 5950 reg = <3>; 5951 5952 cdsp_tpda_in3: endpoint { 5953 remote-endpoint = <&cdsp_cmsr_tpdm_out>; 5954 }; 5955 }; 5956 5957 port@4 { 5958 reg = <4>; 5959 5960 cdsp_tpda_in4: endpoint { 5961 remote-endpoint = <&cdsp_cmsr2_tpdm_out>; 5962 }; 5963 }; 5964 5965 port@5 { 5966 reg = <5>; 5967 5968 cdsp_tpda_in5: endpoint { 5969 remote-endpoint = <&cdsp_dpm1_tpdm_out>; 5970 }; 5971 }; 5972 5973 port@6 { 5974 reg = <6>; 5975 5976 cdsp_tpda_in6: endpoint { 5977 remote-endpoint = <&cdsp_dpm2_tpdm_out>; 5978 }; 5979 }; 5980 }; 5981 5982 out-ports { 5983 port { 5984 cdsp_tpda_out: endpoint { 5985 remote-endpoint = <&cdsp_funnel_in0>; 5986 }; 5987 }; 5988 }; 5989 }; 5990 5991 funnel@11189000 { 5992 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5993 reg = <0x0 0x11189000 0x0 0x1000>; 5994 5995 clocks = <&aoss_qmp>; 5996 clock-names = "apb_pclk"; 5997 5998 in-ports { 5999 port { 6000 cdsp_funnel_in0: endpoint { 6001 remote-endpoint = <&cdsp_tpda_out>; 6002 }; 6003 }; 6004 }; 6005 6006 out-ports { 6007 port { 6008 cdsp_funnel_out: endpoint { 6009 remote-endpoint = <&tn_ag_in53>; 6010 }; 6011 }; 6012 }; 6013 }; 6014 6015 cti@11193000 { 6016 compatible = "arm,coresight-cti", "arm,primecell"; 6017 reg = <0x0 0x11193000 0x0 0x1000>; 6018 6019 clocks = <&aoss_qmp>; 6020 clock-names = "apb_pclk"; 6021 }; 6022 6023 cti_wpss: cti@111ab000 { 6024 compatible = "arm,coresight-cti", "arm,primecell"; 6025 reg = <0x0 0x111ab000 0x0 0x1000>; 6026 6027 clocks = <&aoss_qmp>; 6028 clock-names = "apb_pclk"; 6029 }; 6030 6031 tpdm@111d0000 { 6032 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6033 reg = <0x0 0x111d0000 0x0 0x1000>; 6034 6035 clocks = <&aoss_qmp>; 6036 clock-names = "apb_pclk"; 6037 6038 qcom,dsb-msrs-num = <32>; 6039 6040 out-ports { 6041 port { 6042 qm_tpdm_out: endpoint { 6043 remote-endpoint = <&tn_ag_in35>; 6044 }; 6045 }; 6046 }; 6047 }; 6048 6049 itnoc@11200000 { 6050 compatible = "qcom,coresight-itnoc"; 6051 reg = <0x0 0x11200000 0x0 0x3c00>; 6052 6053 clocks = <&aoss_qmp>; 6054 clock-names = "apb"; 6055 6056 in-ports { 6057 #address-cells = <1>; 6058 #size-cells = <0>; 6059 6060 port@6 { 6061 reg = <6>; 6062 6063 tn_ag_in6: endpoint { 6064 remote-endpoint = <&mm_dsb_tpdm_out>; 6065 }; 6066 }; 6067 6068 port@10 { 6069 reg = <0x10>; 6070 6071 tn_ag_in16: endpoint { 6072 remote-endpoint = <&east_dsb_tpdm_out>; 6073 }; 6074 }; 6075 6076 port@21 { 6077 reg = <0x21>; 6078 6079 tn_ag_in33: endpoint { 6080 remote-endpoint = <&west_dsb_tpdm_out>; 6081 }; 6082 }; 6083 6084 port@23 { 6085 reg = <0x23>; 6086 6087 tn_ag_in35: endpoint { 6088 remote-endpoint = <&qm_tpdm_out>; 6089 }; 6090 }; 6091 6092 port@24 { 6093 reg = <0x24>; 6094 6095 tn_ag_in36: endpoint { 6096 remote-endpoint = <&gcc_tpdm_out>; 6097 }; 6098 }; 6099 6100 port@32 { 6101 reg = <0x32>; 6102 6103 tn_ag_in50: endpoint { 6104 remote-endpoint = <&pcie_rscc_tpda_out>; 6105 }; 6106 }; 6107 6108 port@35 { 6109 reg = <0x35>; 6110 6111 tn_ag_in53: endpoint { 6112 remote-endpoint = <&cdsp_funnel_out>; 6113 }; 6114 }; 6115 6116 port@3f { 6117 reg = <0x3f>; 6118 6119 tn_ag_in63: endpoint { 6120 remote-endpoint = <¢er_dsb_tpdm_out>; 6121 }; 6122 }; 6123 6124 port@40 { 6125 reg = <0x40>; 6126 6127 tn_ag_in64: endpoint { 6128 remote-endpoint = <&ipcc_cmb_tpdm_out>; 6129 }; 6130 }; 6131 6132 port@41 { 6133 reg = <0x41>; 6134 6135 tn_ag_in65: endpoint { 6136 remote-endpoint = <&qrng_tpdm_out>; 6137 }; 6138 }; 6139 6140 port@42 { 6141 reg = <0x42>; 6142 6143 tn_ag_in66: endpoint { 6144 remote-endpoint = <&pmu_tpdm_out>; 6145 }; 6146 }; 6147 6148 port@43 { 6149 reg = <0x43>; 6150 6151 tn_ag_in67: endpoint { 6152 remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; 6153 }; 6154 }; 6155 6156 port@44 { 6157 reg = <0x44>; 6158 6159 tn_ag_in68: endpoint { 6160 remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; 6161 }; 6162 }; 6163 6164 port@45 { 6165 reg = <0x45>; 6166 6167 tn_ag_in69: endpoint { 6168 remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; 6169 }; 6170 }; 6171 6172 port@4b { 6173 reg = <0x4b>; 6174 6175 tn_ag_in75: endpoint { 6176 remote-endpoint = <&south_dsb2_tpdm_out>; 6177 }; 6178 }; 6179 6180 port@52 { 6181 reg = <0x52>; 6182 6183 tn_ag_in82: endpoint { 6184 remote-endpoint = <&south_dsb_tpdm_out>; 6185 }; 6186 }; 6187 6188 port@53 { 6189 reg = <0x53>; 6190 6191 tn_ag_in83: endpoint { 6192 remote-endpoint = <¢er_dsb1_tpdm_out>; 6193 }; 6194 }; 6195 }; 6196 6197 out-ports { 6198 port { 6199 tn_ag_out: endpoint { 6200 remote-endpoint = <&funnel0_in0>; 6201 }; 6202 }; 6203 }; 6204 }; 6205 6206 tpdm@11207000 { 6207 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6208 reg = <0x0 0x11207000 0x0 0x1000>; 6209 6210 clocks = <&aoss_qmp>; 6211 clock-names = "apb_pclk"; 6212 6213 qcom,dsb-msrs-num = <32>; 6214 6215 out-ports { 6216 port { 6217 mm_dsb_tpdm_out: endpoint { 6218 remote-endpoint = <&tn_ag_in6>; 6219 }; 6220 }; 6221 }; 6222 }; 6223 6224 tpdm@1120b000 { 6225 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6226 reg = <0x0 0x1120b000 0x0 0x1000>; 6227 6228 clocks = <&aoss_qmp>; 6229 clock-names = "apb_pclk"; 6230 6231 qcom,dsb-msrs-num = <32>; 6232 6233 out-ports { 6234 port { 6235 east_dsb_tpdm_out: endpoint { 6236 remote-endpoint = <&tn_ag_in16>; 6237 }; 6238 }; 6239 }; 6240 }; 6241 6242 tpdm@11213000 { 6243 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6244 reg = <0x0 0x11213000 0x0 0x1000>; 6245 6246 clocks = <&aoss_qmp>; 6247 clock-names = "apb_pclk"; 6248 6249 qcom,dsb-msrs-num = <32>; 6250 6251 out-ports { 6252 port { 6253 west_dsb_tpdm_out: endpoint { 6254 remote-endpoint = <&tn_ag_in33>; 6255 }; 6256 }; 6257 }; 6258 }; 6259 6260 tpdm@11219000 { 6261 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6262 reg = <0x0 0x11219000 0x0 0x1000>; 6263 6264 clocks = <&aoss_qmp>; 6265 clock-names = "apb_pclk"; 6266 6267 qcom,dsb-msrs-num = <32>; 6268 6269 out-ports { 6270 port { 6271 center_dsb_tpdm_out: endpoint { 6272 remote-endpoint = <&tn_ag_in63>; 6273 }; 6274 }; 6275 }; 6276 }; 6277 6278 tpdm@1121a000 { 6279 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6280 reg = <0x0 0x1121a000 0x0 0x1000>; 6281 6282 clocks = <&aoss_qmp>; 6283 clock-names = "apb_pclk"; 6284 6285 qcom,cmb-msrs-num = <32>; 6286 6287 out-ports { 6288 port { 6289 ipcc_cmb_tpdm_out: endpoint { 6290 remote-endpoint = <&tn_ag_in64>; 6291 }; 6292 }; 6293 }; 6294 }; 6295 6296 tpdm@1121b000 { 6297 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6298 reg = <0x0 0x1121b000 0x0 0x1000>; 6299 6300 clocks = <&aoss_qmp>; 6301 clock-names = "apb_pclk"; 6302 6303 qcom,cmb-msrs-num = <32>; 6304 6305 out-ports { 6306 port { 6307 qrng_tpdm_out: endpoint { 6308 remote-endpoint = <&tn_ag_in65>; 6309 }; 6310 }; 6311 }; 6312 }; 6313 6314 tpdm@1121c000 { 6315 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6316 reg = <0x0 0x1121c000 0x0 0x1000>; 6317 6318 clocks = <&aoss_qmp>; 6319 clock-names = "apb_pclk"; 6320 6321 qcom,dsb-msrs-num = <32>; 6322 6323 out-ports { 6324 port { 6325 pmu_tpdm_out: endpoint { 6326 remote-endpoint = <&tn_ag_in66>; 6327 }; 6328 }; 6329 }; 6330 }; 6331 6332 tpdm@1121d000 { 6333 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6334 reg = <0x0 0x1121d000 0x0 0x1000>; 6335 6336 clocks = <&aoss_qmp>; 6337 clock-names = "apb_pclk"; 6338 6339 qcom,cmb-msrs-num = <32>; 6340 6341 out-ports { 6342 port { 6343 rdpm_west_cmb0_tpdm_out: endpoint { 6344 remote-endpoint = <&tn_ag_in67>; 6345 }; 6346 }; 6347 }; 6348 }; 6349 6350 tpdm@1121e000 { 6351 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6352 reg = <0x0 0x1121e000 0x0 0x1000>; 6353 6354 clocks = <&aoss_qmp>; 6355 clock-names = "apb_pclk"; 6356 6357 qcom,cmb-msrs-num = <32>; 6358 6359 out-ports { 6360 port { 6361 rdpm_west_cmb1_tpdm_out: endpoint { 6362 remote-endpoint = <&tn_ag_in68>; 6363 }; 6364 }; 6365 }; 6366 }; 6367 6368 tpdm@1121f000 { 6369 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6370 reg = <0x0 0x1121f000 0x0 0x1000>; 6371 6372 clocks = <&aoss_qmp>; 6373 clock-names = "apb_pclk"; 6374 6375 qcom,cmb-msrs-num = <32>; 6376 6377 out-ports { 6378 port { 6379 rdpm_west_cmb2_tpdm_out: endpoint { 6380 remote-endpoint = <&tn_ag_in69>; 6381 }; 6382 }; 6383 }; 6384 }; 6385 6386 tpdm@11220000 { 6387 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6388 reg = <0x0 0x11220000 0x0 0x1000>; 6389 6390 clocks = <&aoss_qmp>; 6391 clock-names = "apb_pclk"; 6392 6393 qcom,dsb-msrs-num = <32>; 6394 6395 out-ports { 6396 port { 6397 center_dsb1_tpdm_out: endpoint { 6398 remote-endpoint = <&tn_ag_in83>; 6399 }; 6400 }; 6401 }; 6402 }; 6403 6404 tpdm@11224000 { 6405 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6406 reg = <0x0 0x11224000 0x0 0x1000>; 6407 6408 clocks = <&aoss_qmp>; 6409 clock-names = "apb_pclk"; 6410 6411 qcom,dsb-msrs-num = <32>; 6412 6413 out-ports { 6414 port { 6415 south_dsb2_tpdm_out: endpoint { 6416 remote-endpoint = <&tn_ag_in75>; 6417 }; 6418 }; 6419 }; 6420 }; 6421 6422 tpdm@11228000 { 6423 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6424 reg = <0x0 0x11228000 0x0 0x1000>; 6425 6426 clocks = <&aoss_qmp>; 6427 clock-names = "apb_pclk"; 6428 6429 qcom,dsb-msrs-num = <32>; 6430 6431 out-ports { 6432 port { 6433 south_dsb_tpdm_out: endpoint { 6434 remote-endpoint = <&tn_ag_in82>; 6435 }; 6436 }; 6437 }; 6438 }; 6439 6440 tpdm@11470000 { 6441 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6442 reg = <0x0 0x11470000 0x0 0x1000>; 6443 6444 clocks = <&aoss_qmp>; 6445 clock-names = "apb_pclk"; 6446 6447 qcom,cmb-element-bits = <32>; 6448 qcom,cmb-msrs-num = <32>; 6449 6450 out-ports { 6451 port { 6452 pcie_rscc_tpdm_out: endpoint { 6453 remote-endpoint = <&pcie_rscc_tpda_in0>; 6454 }; 6455 }; 6456 }; 6457 }; 6458 6459 tpda@11471000 { 6460 compatible = "qcom,coresight-tpda", "arm,primecell"; 6461 reg = <0x0 0x11471000 0x0 0x1000>; 6462 6463 clocks = <&aoss_qmp>; 6464 clock-names = "apb_pclk"; 6465 6466 in-ports { 6467 port { 6468 pcie_rscc_tpda_in0: endpoint { 6469 remote-endpoint = <&pcie_rscc_tpdm_out>; 6470 }; 6471 }; 6472 }; 6473 6474 out-ports { 6475 port { 6476 pcie_rscc_tpda_out: endpoint { 6477 remote-endpoint = <&tn_ag_in50>; 6478 }; 6479 }; 6480 }; 6481 }; 6482 6483 tpdm@11c03000 { 6484 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6485 reg = <0x0 0x11c03000 0x0 0x1000>; 6486 6487 clocks = <&aoss_qmp>; 6488 clock-names = "apb_pclk"; 6489 6490 qcom,cmb-element-bits = <64>; 6491 qcom,cmb-msrs-num = <32>; 6492 6493 out-ports { 6494 port { 6495 swao_prio4_tpdm_out: endpoint { 6496 remote-endpoint = <&aoss_tpda_in4>; 6497 }; 6498 }; 6499 }; 6500 }; 6501 6502 funnel@11c04000 { 6503 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6504 reg = <0x0 0x11c04000 0x0 0x1000>; 6505 6506 clocks = <&aoss_qmp>; 6507 clock-names = "apb_pclk"; 6508 6509 in-ports { 6510 #address-cells = <1>; 6511 #size-cells = <0>; 6512 6513 port@5 { 6514 reg = <5>; 6515 6516 aoss_funnel_in5: endpoint { 6517 remote-endpoint = <&aoss_tpda_out>; 6518 }; 6519 }; 6520 6521 port@6 { 6522 reg = <6>; 6523 6524 aoss_funnel_in6: endpoint { 6525 remote-endpoint = <&funnel0_out>; 6526 }; 6527 }; 6528 }; 6529 6530 out-ports { 6531 port { 6532 aoss_funnel_out: endpoint { 6533 remote-endpoint = <&etf0_in>; 6534 }; 6535 }; 6536 }; 6537 }; 6538 6539 tmc_etf: tmc@11c05000 { 6540 compatible = "arm,coresight-tmc", "arm,primecell"; 6541 reg = <0x0 0x11c05000 0x0 0x1000>; 6542 6543 clocks = <&aoss_qmp>; 6544 clock-names = "apb_pclk"; 6545 6546 in-ports { 6547 port { 6548 etf0_in: endpoint { 6549 remote-endpoint = <&aoss_funnel_out>; 6550 }; 6551 }; 6552 }; 6553 6554 out-ports { 6555 port { 6556 etf0_out: endpoint { 6557 remote-endpoint = <&swao_rep_in>; 6558 }; 6559 }; 6560 }; 6561 }; 6562 6563 replicator@11c06000 { 6564 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6565 reg = <0x0 0x11c06000 0x0 0x1000>; 6566 6567 clocks = <&aoss_qmp>; 6568 clock-names = "apb_pclk"; 6569 6570 in-ports { 6571 port { 6572 swao_rep_in: endpoint { 6573 remote-endpoint = <&etf0_out>; 6574 }; 6575 }; 6576 }; 6577 6578 out-ports { 6579 #address-cells = <1>; 6580 #size-cells = <0>; 6581 6582 port@1 { 6583 reg = <1>; 6584 6585 swao_rep_out1: endpoint { 6586 remote-endpoint = <&eud_in>; 6587 }; 6588 }; 6589 }; 6590 }; 6591 6592 tpda@11c08000 { 6593 compatible = "qcom,coresight-tpda", "arm,primecell"; 6594 reg = <0x0 0x11c08000 0x0 0x1000>; 6595 6596 clocks = <&aoss_qmp>; 6597 clock-names = "apb_pclk"; 6598 6599 in-ports { 6600 #address-cells = <1>; 6601 #size-cells = <0>; 6602 6603 port@0 { 6604 reg = <0>; 6605 6606 aoss_tpda_in0: endpoint { 6607 remote-endpoint = <&swao_prio0_tpdm_out>; 6608 }; 6609 }; 6610 6611 port@1 { 6612 reg = <1>; 6613 6614 aoss_tpda_in1: endpoint { 6615 remote-endpoint = <&swao_prio1_tpdm_out>; 6616 }; 6617 }; 6618 6619 port@2 { 6620 reg = <2>; 6621 6622 aoss_tpda_in2: endpoint { 6623 remote-endpoint = <&swao_prio2_tpdm_out>; 6624 }; 6625 }; 6626 6627 port@3 { 6628 reg = <3>; 6629 6630 aoss_tpda_in3: endpoint { 6631 remote-endpoint = <&swao_prio3_tpdm_out>; 6632 }; 6633 }; 6634 6635 port@4 { 6636 reg = <4>; 6637 6638 aoss_tpda_in4: endpoint { 6639 remote-endpoint = <&swao_prio4_tpdm_out>; 6640 }; 6641 }; 6642 6643 port@5 { 6644 reg = <5>; 6645 6646 aoss_tpda_in5: endpoint { 6647 remote-endpoint = <&swao_tpdm_out>; 6648 }; 6649 }; 6650 }; 6651 6652 out-ports { 6653 port { 6654 aoss_tpda_out: endpoint { 6655 remote-endpoint = <&aoss_funnel_in5>; 6656 }; 6657 }; 6658 }; 6659 }; 6660 6661 tpdm@11c09000 { 6662 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6663 reg = <0x0 0x11c09000 0x0 0x1000>; 6664 6665 clocks = <&aoss_qmp>; 6666 clock-names = "apb_pclk"; 6667 6668 qcom,cmb-element-bits = <64>; 6669 qcom,cmb-msrs-num = <32>; 6670 6671 out-ports { 6672 port { 6673 swao_prio0_tpdm_out: endpoint { 6674 remote-endpoint = <&aoss_tpda_in0>; 6675 }; 6676 }; 6677 }; 6678 }; 6679 6680 tpdm@11c0a000 { 6681 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6682 reg = <0x0 0x11c0a000 0x0 0x1000>; 6683 6684 clocks = <&aoss_qmp>; 6685 clock-names = "apb_pclk"; 6686 6687 qcom,cmb-element-bits = <64>; 6688 qcom,cmb-msrs-num = <32>; 6689 6690 out-ports { 6691 port { 6692 swao_prio1_tpdm_out: endpoint { 6693 remote-endpoint = <&aoss_tpda_in1>; 6694 }; 6695 }; 6696 }; 6697 }; 6698 6699 tpdm@11c0b000 { 6700 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6701 reg = <0x0 0x11c0b000 0x0 0x1000>; 6702 6703 clocks = <&aoss_qmp>; 6704 clock-names = "apb_pclk"; 6705 6706 qcom,cmb-element-bits = <64>; 6707 qcom,cmb-msrs-num = <32>; 6708 6709 out-ports { 6710 port { 6711 swao_prio2_tpdm_out: endpoint { 6712 remote-endpoint = <&aoss_tpda_in2>; 6713 }; 6714 }; 6715 }; 6716 }; 6717 6718 tpdm@11c0c000 { 6719 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6720 reg = <0x0 0x11c0c000 0x0 0x1000>; 6721 6722 clocks = <&aoss_qmp>; 6723 clock-names = "apb_pclk"; 6724 6725 qcom,cmb-element-bits = <64>; 6726 qcom,cmb-msrs-num = <32>; 6727 6728 out-ports { 6729 port { 6730 swao_prio3_tpdm_out: endpoint { 6731 remote-endpoint = <&aoss_tpda_in3>; 6732 }; 6733 }; 6734 }; 6735 }; 6736 6737 tpdm@11c0d000 { 6738 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6739 reg = <0x0 0x11c0d000 0x0 0x1000>; 6740 6741 clocks = <&aoss_qmp>; 6742 clock-names = "apb_pclk"; 6743 6744 qcom,dsb-element-bits = <32>; 6745 qcom,dsb-msrs-num = <32>; 6746 6747 out-ports { 6748 port { 6749 swao_tpdm_out: endpoint { 6750 remote-endpoint = <&aoss_tpda_in5>; 6751 }; 6752 }; 6753 }; 6754 }; 6755 6756 apps_smmu: iommu@15000000 { 6757 compatible = "qcom,glymur-smmu-500", 6758 "qcom,smmu-500", 6759 "arm,mmu-500"; 6760 reg = <0x0 0x15000000 0x0 0x100000>; 6761 6762 #iommu-cells = <2>; 6763 #global-interrupts = <1>; 6764 6765 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6766 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6767 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6768 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6769 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6770 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6771 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6772 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6773 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6774 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6775 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6776 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6777 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6778 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6779 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6780 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6781 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6782 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6783 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6784 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6785 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6786 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6787 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6788 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6789 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6790 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6791 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6792 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6793 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6794 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6795 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6796 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6797 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6798 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6799 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6800 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6801 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6802 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6803 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6804 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6805 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6806 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6807 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6808 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6809 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6810 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6811 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6812 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6813 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6814 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6815 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6816 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6817 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6818 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6819 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6820 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6821 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6822 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6823 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6824 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6825 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6826 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6827 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6828 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6829 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6830 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6831 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6832 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6833 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6834 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6835 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6836 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6837 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6838 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6839 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6840 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6841 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6842 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6843 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6844 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6845 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6846 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6847 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6848 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6849 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6850 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6851 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6852 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6853 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6854 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6855 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6856 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6857 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6858 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6859 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6860 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6861 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 6862 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6863 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 6864 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 6865 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 6866 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 6867 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 6868 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 6869 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 6870 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 6871 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 6872 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 6873 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 6874 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 6875 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 6876 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 6877 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 6878 6879 dma-coherent; 6880 }; 6881 6882 pcie_smmu: iommu@15480000 { 6883 compatible = "arm,smmu-v3"; 6884 reg = <0x0 0x15480000 0x0 0x20000>; 6885 interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>, 6886 <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>, 6887 <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>; 6888 interrupt-names = "eventq", "cmdq-sync", "gerror"; 6889 dma-coherent; 6890 #iommu-cells = <1>; 6891 }; 6892 6893 intc: interrupt-controller@17000000 { 6894 compatible = "arm,gic-v3"; 6895 reg = <0x0 0x17000000 0x0 0x10000>, 6896 <0x0 0x17080000 0x0 0x480000>; 6897 6898 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6899 6900 #interrupt-cells = <3>; 6901 interrupt-controller; 6902 6903 #address-cells = <2>; 6904 #size-cells = <2>; 6905 ranges; 6906 6907 gic_its: msi-controller@17040000 { 6908 compatible = "arm,gic-v3-its"; 6909 reg = <0x0 0x17040000 0x0 0x40000>; 6910 6911 msi-controller; 6912 #msi-cells = <1>; 6913 }; 6914 }; 6915 6916 watchdog@17600000 { 6917 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 6918 reg = <0x0 0x17600000 0x0 0x1000>; 6919 clocks = <&sleep_clk>; 6920 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6921 }; 6922 6923 pdp0_mbox: mailbox@17610000 { 6924 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 6925 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 6926 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 6927 #mbox-cells = <1>; 6928 }; 6929 6930 timer@17810000 { 6931 compatible = "arm,armv7-timer-mem"; 6932 reg = <0x0 0x17810000 0x0 0x1000>; 6933 #address-cells = <2>; 6934 #size-cells = <1>; 6935 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 6936 6937 frame@17811000 { 6938 reg = <0x0 0x17811000 0x1000>, 6939 <0x0 0x17812000 0x1000>; 6940 6941 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6942 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6943 6944 frame-number = <0>; 6945 }; 6946 6947 frame@17813000 { 6948 reg = <0x0 0x17813000 0x1000>; 6949 6950 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6951 6952 frame-number = <1>; 6953 6954 status = "disabled"; 6955 }; 6956 6957 frame@17815000 { 6958 reg = <0x0 0x17815000 0x1000>; 6959 6960 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6961 6962 frame-number = <2>; 6963 6964 status = "disabled"; 6965 }; 6966 6967 frame@17817000 { 6968 reg = <0x0 0x17817000 0x1000>; 6969 6970 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6971 6972 frame-number = <3>; 6973 6974 status = "disabled"; 6975 }; 6976 6977 frame@17819000 { 6978 reg = <0x0 0x17819000 0x1000>; 6979 6980 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6981 6982 frame-number = <4>; 6983 6984 status = "disabled"; 6985 }; 6986 6987 frame@1781b000 { 6988 reg = <0x0 0x1781b000 0x1000>; 6989 6990 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6991 6992 frame-number = <5>; 6993 6994 status = "disabled"; 6995 }; 6996 6997 frame@1781d000 { 6998 reg = <0x0 0x1781d000 0x1000>; 6999 7000 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7001 7002 frame-number = <6>; 7003 7004 status = "disabled"; 7005 }; 7006 }; 7007 7008 apps_rsc: rsc@18900000 { 7009 compatible = "qcom,rpmh-rsc"; 7010 label = "apps_rsc"; 7011 reg = <0x0 0x18900000 0x0 0x10000>, 7012 <0x0 0x18910000 0x0 0x10000>, 7013 <0x0 0x18920000 0x0 0x10000>; 7014 reg-names = "drv-0", 7015 "drv-1", 7016 "drv-2"; 7017 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7018 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7019 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7020 qcom,tcs-offset = <0xd00>; 7021 qcom,drv-id = <2>; 7022 qcom,tcs-config = <ACTIVE_TCS 2>, 7023 <SLEEP_TCS 3>, 7024 <WAKE_TCS 3>, 7025 <CONTROL_TCS 0>; 7026 power-domains = <&system_pd>; 7027 7028 apps_bcm_voter: bcm-voter { 7029 compatible = "qcom,bcm-voter"; 7030 }; 7031 7032 rpmhcc: clock-controller { 7033 compatible = "qcom,glymur-rpmh-clk"; 7034 7035 clocks = <&xo_board>; 7036 clock-names = "xo"; 7037 7038 #clock-cells = <1>; 7039 }; 7040 7041 rpmhpd: power-controller { 7042 compatible = "qcom,glymur-rpmhpd"; 7043 7044 operating-points-v2 = <&rpmhpd_opp_table>; 7045 7046 #power-domain-cells = <1>; 7047 7048 rpmhpd_opp_table: opp-table { 7049 compatible = "operating-points-v2"; 7050 7051 rpmhpd_opp_ret: opp-16 { 7052 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7053 }; 7054 7055 rpmhpd_opp_min_svs: opp-48 { 7056 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7057 }; 7058 7059 rpmhpd_opp_low_svs_d2: opp-52 { 7060 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 7061 }; 7062 7063 rpmhpd_opp_low_svs_d1: opp-56 { 7064 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 7065 }; 7066 7067 rpmhpd_opp_low_svs_d0: opp-60 { 7068 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 7069 }; 7070 7071 rpmhpd_opp_low_svs: opp-64 { 7072 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7073 }; 7074 7075 rpmhpd_opp_low_svs_l1: opp-80 { 7076 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 7077 }; 7078 7079 rpmhpd_opp_svs: opp-128 { 7080 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7081 }; 7082 7083 rpmhpd_opp_svs_l0: opp-144 { 7084 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 7085 }; 7086 7087 rpmhpd_opp_svs_l1: opp-192 { 7088 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7089 }; 7090 7091 rpmhpd_opp_nom: opp-256 { 7092 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7093 }; 7094 7095 rpmhpd_opp_nom_l1: opp-320 { 7096 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7097 }; 7098 7099 rpmhpd_opp_nom_l2: opp-336 { 7100 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7101 }; 7102 7103 rpmhpd_opp_turbo: opp-384 { 7104 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7105 }; 7106 7107 rpmhpd_opp_turbo_l1: opp-416 { 7108 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7109 }; 7110 }; 7111 }; 7112 }; 7113 7114 nsi_noc: interconnect@1d600000 { 7115 compatible = "qcom,glymur-nsinoc"; 7116 reg = <0x0 0x1d600000 0x0 0x14080>; 7117 qcom,bcm-voters = <&apps_bcm_voter>; 7118 #interconnect-cells = <2>; 7119 }; 7120 7121 oobm_ss_noc: interconnect@1f300000 { 7122 compatible = "qcom,glymur-oobm-ss-noc"; 7123 reg = <0x0 0x1f300000 0x0 0x49a00>; 7124 qcom,bcm-voters = <&apps_bcm_voter>; 7125 #interconnect-cells = <2>; 7126 }; 7127 7128 system-cache-controller@21800000 { 7129 compatible = "qcom,glymur-llcc"; 7130 reg = <0x0 0x21800000 0x0 0x100000>, 7131 <0x0 0x21a00000 0x0 0x100000>, 7132 <0x0 0x21c00000 0x0 0x100000>, 7133 <0x0 0x21e00000 0x0 0x100000>, 7134 <0x0 0x22800000 0x0 0x100000>, 7135 <0x0 0x22a00000 0x0 0x100000>, 7136 <0x0 0x22c00000 0x0 0x100000>, 7137 <0x0 0x22e00000 0x0 0x100000>, 7138 <0x0 0x23800000 0x0 0x100000>, 7139 <0x0 0x23a00000 0x0 0x100000>, 7140 <0x0 0x23c00000 0x0 0x100000>, 7141 <0x0 0x23e00000 0x0 0x100000>, 7142 <0x0 0x20400000 0x0 0x100000>, 7143 <0x0 0x20600000 0x0 0x100000>; 7144 reg-names = "llcc0_base", 7145 "llcc1_base", 7146 "llcc2_base", 7147 "llcc3_base", 7148 "llcc4_base", 7149 "llcc5_base", 7150 "llcc6_base", 7151 "llcc7_base", 7152 "llcc8_base", 7153 "llcc9_base", 7154 "llcc10_base", 7155 "llcc11_base", 7156 "llcc_broadcast_base", 7157 "llcc_broadcast_and_base"; 7158 7159 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 7160 }; 7161 7162 remoteproc_cdsp: remoteproc@32300000 { 7163 compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; 7164 reg = <0x0 0x32300000 0x0 0x10000>; 7165 7166 iommus = <&apps_smmu 0x2400 0x400>; 7167 7168 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7169 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7170 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7171 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7172 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 7173 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 7174 interrupt-names = "wdog", 7175 "fatal", 7176 "ready", 7177 "handover", 7178 "stop-ack", 7179 "shutdown-ack"; 7180 7181 clocks = <&rpmhcc RPMH_CXO_CLK>; 7182 clock-names = "xo"; 7183 7184 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7185 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7186 7187 power-domains = <&rpmhpd RPMHPD_CX>, 7188 <&rpmhpd RPMHPD_MXC>, 7189 <&rpmhpd RPMHPD_NSP>; 7190 power-domain-names = "cx", 7191 "mxc", 7192 "nsp"; 7193 7194 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 7195 qcom,qmp = <&aoss_qmp>; 7196 qcom,smem-states = <&smp2p_cdsp_out 0>; 7197 qcom,smem-state-names = "stop"; 7198 7199 status = "disabled"; 7200 7201 glink-edge { 7202 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 7203 IPCC_MPROC_SIGNAL_GLINK_QMP 7204 IRQ_TYPE_EDGE_RISING>; 7205 mboxes = <&ipcc IPCC_MPROC_CDSP 7206 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7207 qcom,remote-pid = <5>; 7208 label = "cdsp"; 7209 7210 fastrpc { 7211 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 7212 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7213 label = "cdsp"; 7214 #address-cells = <1>; 7215 #size-cells = <0>; 7216 7217 compute-cb@1 { 7218 compatible = "qcom,fastrpc-compute-cb"; 7219 reg = <1>; 7220 7221 iommus = <&apps_smmu 0x2401 0x440>, 7222 <&apps_smmu 0x1961 0x0>, 7223 <&apps_smmu 0x19c1 0x0>; 7224 dma-coherent; 7225 }; 7226 7227 compute-cb@2 { 7228 compatible = "qcom,fastrpc-compute-cb"; 7229 reg = <2>; 7230 7231 iommus = <&apps_smmu 0x2402 0x440>, 7232 <&apps_smmu 0x1962 0x0>, 7233 <&apps_smmu 0x19c2 0x0>; 7234 dma-coherent; 7235 }; 7236 7237 compute-cb@3 { 7238 compatible = "qcom,fastrpc-compute-cb"; 7239 reg = <3>; 7240 7241 iommus = <&apps_smmu 0x2403 0x440>, 7242 <&apps_smmu 0x1963 0x0>, 7243 <&apps_smmu 0x19c3 0x0>; 7244 dma-coherent; 7245 }; 7246 7247 compute-cb@4 { 7248 compatible = "qcom,fastrpc-compute-cb"; 7249 reg = <4>; 7250 7251 iommus = <&apps_smmu 0x2404 0x440>, 7252 <&apps_smmu 0x1964 0x0>, 7253 <&apps_smmu 0x19c4 0x0>; 7254 dma-coherent; 7255 }; 7256 7257 compute-cb@5 { 7258 compatible = "qcom,fastrpc-compute-cb"; 7259 reg = <5>; 7260 7261 iommus = <&apps_smmu 0x2405 0x440>, 7262 <&apps_smmu 0x1965 0x0>, 7263 <&apps_smmu 0x19c5 0x0>; 7264 dma-coherent; 7265 }; 7266 7267 compute-cb@6 { 7268 compatible = "qcom,fastrpc-compute-cb"; 7269 reg = <6>; 7270 7271 iommus = <&apps_smmu 0x2406 0x440>, 7272 <&apps_smmu 0x1966 0x0>, 7273 <&apps_smmu 0x19c6 0x0>; 7274 dma-coherent; 7275 }; 7276 7277 compute-cb@7 { 7278 compatible = "qcom,fastrpc-compute-cb"; 7279 reg = <7>; 7280 7281 iommus = <&apps_smmu 0x2407 0x440>, 7282 <&apps_smmu 0x1967 0x0>, 7283 <&apps_smmu 0x19c7 0x0>; 7284 dma-coherent; 7285 }; 7286 7287 compute-cb@8 { 7288 compatible = "qcom,fastrpc-compute-cb"; 7289 reg = <8>; 7290 7291 iommus = <&apps_smmu 0x2408 0x440>, 7292 <&apps_smmu 0x1968 0x0>, 7293 <&apps_smmu 0x19c8 0x0>; 7294 dma-coherent; 7295 }; 7296 7297 /* note: compute-cb@9 is secure */ 7298 7299 compute-cb@10 { 7300 compatible = "qcom,fastrpc-compute-cb"; 7301 reg = <10>; 7302 7303 iommus = <&apps_smmu 0x240c 0x440>, 7304 <&apps_smmu 0x196c 0x0>, 7305 <&apps_smmu 0x19cc 0x0>; 7306 dma-coherent; 7307 }; 7308 7309 compute-cb@11 { 7310 compatible = "qcom,fastrpc-compute-cb"; 7311 reg = <11>; 7312 7313 iommus = <&apps_smmu 0x240d 0x440>, 7314 <&apps_smmu 0x196d 0x0>, 7315 <&apps_smmu 0x19cd 0x0>; 7316 dma-coherent; 7317 }; 7318 7319 compute-cb@12 { 7320 compatible = "qcom,fastrpc-compute-cb"; 7321 reg = <12>; 7322 7323 iommus = <&apps_smmu 0x240e 0x440>, 7324 <&apps_smmu 0x196e 0x0>, 7325 <&apps_smmu 0x19ce 0x0>; 7326 dma-coherent; 7327 }; 7328 }; 7329 }; 7330 }; 7331 7332 nsp_noc: interconnect@320c0000 { 7333 compatible = "qcom,glymur-nsp-noc"; 7334 reg = <0x0 0x320c0000 0x0 0x21280>; 7335 qcom,bcm-voters = <&apps_bcm_voter>; 7336 #interconnect-cells = <2>; 7337 }; 7338 7339 qfprom: efuse@361c8000 { 7340 compatible = "qcom,glymur-qfprom", "qcom,qfprom"; 7341 reg = <0x0 0x361c8000 0x0 0x1000>; 7342 #address-cells = <1>; 7343 #size-cells = <1>; 7344 7345 gpu_speed_bin: gpu-speed-bin@138 { 7346 reg = <0x138 0x2>; 7347 bits = <0 9>; 7348 }; 7349 }; 7350 7351 imem: sram@81e08600 { 7352 compatible = "mmio-sram"; 7353 reg = <0x0 0x81e08600 0x0 0x300>; 7354 7355 #address-cells = <1>; 7356 #size-cells = <1>; 7357 ranges = <0x0 0x0 0x81e08600 0x300>; 7358 7359 cpu_scp_lpri0: scp-sram-section@0 { 7360 compatible = "arm,scmi-shmem"; 7361 reg = <0x0 0x180>; 7362 }; 7363 7364 cpu_scp_lpri1: scp-sram-section@180 { 7365 compatible = "arm,scmi-shmem"; 7366 reg = <0x180 0x180>; 7367 }; 7368 }; 7369 }; 7370 7371 timer { 7372 compatible = "arm,armv8-timer"; 7373 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7374 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7375 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7376 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 7377 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 7378 }; 7379 7380 thermal_zones: thermal-zones { 7381 aoss-0-thermal { 7382 thermal-sensors = <&tsens0 0>; 7383 7384 trips { 7385 aoss-0-critical { 7386 temperature = <115000>; 7387 hysteresis = <1000>; 7388 type = "critical"; 7389 }; 7390 }; 7391 }; 7392 7393 cpu-0-0-0-thermal { 7394 thermal-sensors = <&tsens0 1>; 7395 7396 trips { 7397 cpu-0-0-0-critical { 7398 temperature = <115000>; 7399 hysteresis = <1000>; 7400 type = "critical"; 7401 }; 7402 }; 7403 }; 7404 7405 cpu-0-0-1-thermal { 7406 thermal-sensors = <&tsens0 2>; 7407 7408 trips { 7409 cpu-0-0-1-critical { 7410 temperature = <115000>; 7411 hysteresis = <1000>; 7412 type = "critical"; 7413 }; 7414 }; 7415 }; 7416 7417 cpu-0-1-0-thermal { 7418 thermal-sensors = <&tsens0 3>; 7419 7420 trips { 7421 cpu-0-1-0-critical { 7422 temperature = <115000>; 7423 hysteresis = <1000>; 7424 type = "critical"; 7425 }; 7426 }; 7427 }; 7428 7429 cpu-0-1-1-thermal { 7430 thermal-sensors = <&tsens0 4>; 7431 7432 trips { 7433 cpu-0-1-1-critical { 7434 temperature = <115000>; 7435 hysteresis = <1000>; 7436 type = "critical"; 7437 }; 7438 }; 7439 }; 7440 7441 cpu-0-2-0-thermal { 7442 thermal-sensors = <&tsens0 5>; 7443 7444 trips { 7445 cpu-0-2-0-critical { 7446 temperature = <115000>; 7447 hysteresis = <1000>; 7448 type = "critical"; 7449 }; 7450 }; 7451 }; 7452 7453 cpu-0-2-1-thermal { 7454 thermal-sensors = <&tsens0 6>; 7455 7456 trips { 7457 cpu-0-2-1-critical { 7458 temperature = <115000>; 7459 hysteresis = <1000>; 7460 type = "critical"; 7461 }; 7462 }; 7463 }; 7464 7465 cpu-0-3-0-thermal { 7466 thermal-sensors = <&tsens0 7>; 7467 7468 trips { 7469 cpu-0-3-0-critical { 7470 temperature = <115000>; 7471 hysteresis = <1000>; 7472 type = "critical"; 7473 }; 7474 }; 7475 }; 7476 7477 cpu-0-3-1-thermal { 7478 thermal-sensors = <&tsens0 8>; 7479 7480 trips { 7481 cpu-0-3-1-critical { 7482 temperature = <115000>; 7483 hysteresis = <1000>; 7484 type = "critical"; 7485 }; 7486 }; 7487 }; 7488 7489 cpu-0-4-0-thermal { 7490 thermal-sensors = <&tsens0 9>; 7491 7492 trips { 7493 cpu-0-4-0-critical { 7494 temperature = <115000>; 7495 hysteresis = <1000>; 7496 type = "critical"; 7497 }; 7498 }; 7499 }; 7500 7501 cpu-0-4-1-thermal { 7502 thermal-sensors = <&tsens0 10>; 7503 7504 trips { 7505 cpu-0-4-1-critical { 7506 temperature = <115000>; 7507 hysteresis = <1000>; 7508 type = "critical"; 7509 }; 7510 }; 7511 }; 7512 7513 cpu-0-5-0-thermal { 7514 thermal-sensors = <&tsens0 11>; 7515 7516 trips { 7517 cpu-0-5-0-critical { 7518 temperature = <115000>; 7519 hysteresis = <1000>; 7520 type = "critical"; 7521 }; 7522 }; 7523 }; 7524 7525 cpu-0-5-1-thermal { 7526 thermal-sensors = <&tsens0 12>; 7527 7528 trips { 7529 cpu-0-5-1-critical { 7530 temperature = <115000>; 7531 hysteresis = <1000>; 7532 type = "critical"; 7533 }; 7534 }; 7535 }; 7536 7537 aoss-1-thermal { 7538 thermal-sensors = <&tsens1 0>; 7539 7540 trips { 7541 aoss-1-critical { 7542 temperature = <115000>; 7543 hysteresis = <1000>; 7544 type = "critical"; 7545 }; 7546 }; 7547 }; 7548 7549 cpullc-0-0-thermal { 7550 thermal-sensors = <&tsens1 1>; 7551 7552 trips { 7553 cpullc-0-0-critical { 7554 temperature = <115000>; 7555 hysteresis = <1000>; 7556 type = "critical"; 7557 }; 7558 }; 7559 }; 7560 7561 cpullc-0-1-thermal { 7562 thermal-sensors = <&tsens1 2>; 7563 7564 trips { 7565 cpullc-0-1-critical { 7566 temperature = <115000>; 7567 hysteresis = <1000>; 7568 type = "critical"; 7569 }; 7570 }; 7571 }; 7572 7573 qmx-0-0-thermal { 7574 thermal-sensors = <&tsens1 3>; 7575 7576 trips { 7577 qmx-0-0-critical { 7578 temperature = <115000>; 7579 hysteresis = <1000>; 7580 type = "critical"; 7581 }; 7582 }; 7583 }; 7584 7585 qmx-0-1-thermal { 7586 thermal-sensors = <&tsens1 4>; 7587 7588 trips { 7589 qmx-0-1-critical { 7590 temperature = <115000>; 7591 hysteresis = <1000>; 7592 type = "critical"; 7593 }; 7594 }; 7595 }; 7596 7597 qmx-0-2-thermal { 7598 thermal-sensors = <&tsens1 5>; 7599 7600 trips { 7601 qmx-0-2-critical { 7602 temperature = <115000>; 7603 hysteresis = <1000>; 7604 type = "critical"; 7605 }; 7606 }; 7607 }; 7608 7609 ddr-0-thermal { 7610 thermal-sensors = <&tsens1 6>; 7611 7612 trips { 7613 ddr-0-critical { 7614 temperature = <115000>; 7615 hysteresis = <1000>; 7616 type = "critical"; 7617 }; 7618 }; 7619 }; 7620 7621 thermal_video_0: video-0-thermal { 7622 thermal-sensors = <&tsens1 7>; 7623 7624 trips { 7625 video-0-critical { 7626 temperature = <115000>; 7627 hysteresis = <1000>; 7628 type = "critical"; 7629 }; 7630 }; 7631 }; 7632 7633 thermal_video_1: video-1-thermal { 7634 thermal-sensors = <&tsens1 8>; 7635 7636 trips { 7637 video-1-critical { 7638 temperature = <115000>; 7639 hysteresis = <1000>; 7640 type = "critical"; 7641 }; 7642 }; 7643 }; 7644 7645 aoss-2-thermal { 7646 thermal-sensors = <&tsens2 0>; 7647 7648 trips { 7649 aoss-2-critical { 7650 temperature = <115000>; 7651 hysteresis = <1000>; 7652 type = "critical"; 7653 }; 7654 }; 7655 }; 7656 7657 cpu-1-0-0-thermal { 7658 thermal-sensors = <&tsens2 1>; 7659 7660 trips { 7661 cpu-1-0-0-critical { 7662 temperature = <115000>; 7663 hysteresis = <1000>; 7664 type = "critical"; 7665 }; 7666 }; 7667 }; 7668 7669 cpu-1-0-1-thermal { 7670 thermal-sensors = <&tsens2 2>; 7671 7672 trips { 7673 cpu-1-0-1-critical { 7674 temperature = <115000>; 7675 hysteresis = <1000>; 7676 type = "critical"; 7677 }; 7678 }; 7679 }; 7680 7681 cpu-1-1-0-thermal { 7682 thermal-sensors = <&tsens2 3>; 7683 7684 trips { 7685 cpu-1-1-0-critical { 7686 temperature = <115000>; 7687 hysteresis = <1000>; 7688 type = "critical"; 7689 }; 7690 }; 7691 }; 7692 7693 cpu-1-1-1-thermal { 7694 thermal-sensors = <&tsens2 4>; 7695 7696 trips { 7697 cpu-1-1-1-critical { 7698 temperature = <115000>; 7699 hysteresis = <1000>; 7700 type = "critical"; 7701 }; 7702 }; 7703 }; 7704 7705 cpu-1-2-0-thermal { 7706 thermal-sensors = <&tsens2 5>; 7707 7708 trips { 7709 cpu-1-2-0-critical { 7710 temperature = <115000>; 7711 hysteresis = <1000>; 7712 type = "critical"; 7713 }; 7714 }; 7715 }; 7716 7717 cpu-1-2-1-thermal { 7718 thermal-sensors = <&tsens2 6>; 7719 7720 trips { 7721 cpu-1-2-1-critical { 7722 temperature = <115000>; 7723 hysteresis = <1000>; 7724 type = "critical"; 7725 }; 7726 }; 7727 }; 7728 7729 cpu-1-3-0-thermal { 7730 thermal-sensors = <&tsens2 7>; 7731 7732 trips { 7733 cpu-1-3-0-critical { 7734 temperature = <115000>; 7735 hysteresis = <1000>; 7736 type = "critical"; 7737 }; 7738 }; 7739 }; 7740 7741 cpu-1-3-1-thermal { 7742 thermal-sensors = <&tsens2 8>; 7743 7744 trips { 7745 cpu-1-3-1-critical { 7746 temperature = <115000>; 7747 hysteresis = <1000>; 7748 type = "critical"; 7749 }; 7750 }; 7751 }; 7752 7753 cpu-1-4-0-thermal { 7754 thermal-sensors = <&tsens2 9>; 7755 7756 trips { 7757 cpu-1-4-0-critical { 7758 temperature = <115000>; 7759 hysteresis = <1000>; 7760 type = "critical"; 7761 }; 7762 }; 7763 }; 7764 7765 cpu-1-4-1-thermal { 7766 thermal-sensors = <&tsens2 10>; 7767 7768 trips { 7769 cpu-1-4-1-critical { 7770 temperature = <115000>; 7771 hysteresis = <1000>; 7772 type = "critical"; 7773 }; 7774 }; 7775 }; 7776 7777 cpu-1-5-0-thermal { 7778 thermal-sensors = <&tsens2 11>; 7779 7780 trips { 7781 cpu-1-5-0-critical { 7782 temperature = <115000>; 7783 hysteresis = <1000>; 7784 type = "critical"; 7785 }; 7786 }; 7787 }; 7788 7789 cpu-1-5-1-thermal { 7790 thermal-sensors = <&tsens2 12>; 7791 7792 trips { 7793 cpu-1-5-1-critical { 7794 temperature = <115000>; 7795 hysteresis = <1000>; 7796 type = "critical"; 7797 }; 7798 }; 7799 }; 7800 7801 aoss-3-thermal { 7802 thermal-sensors = <&tsens3 0>; 7803 7804 trips { 7805 aoss-3-critical { 7806 temperature = <115000>; 7807 hysteresis = <1000>; 7808 type = "critical"; 7809 }; 7810 }; 7811 }; 7812 7813 cpullc-1-0-thermal { 7814 thermal-sensors = <&tsens3 1>; 7815 7816 trips { 7817 cpullc-1-0-critical { 7818 temperature = <115000>; 7819 hysteresis = <1000>; 7820 type = "critical"; 7821 }; 7822 }; 7823 }; 7824 7825 cpullc-1-1-thermal { 7826 thermal-sensors = <&tsens3 2>; 7827 7828 trips { 7829 cpullc-1-1-critical { 7830 temperature = <115000>; 7831 hysteresis = <1000>; 7832 type = "critical"; 7833 }; 7834 }; 7835 }; 7836 7837 qmx-1-0-thermal { 7838 thermal-sensors = <&tsens3 3>; 7839 7840 trips { 7841 qmx-1-0-critical { 7842 temperature = <115000>; 7843 hysteresis = <1000>; 7844 type = "critical"; 7845 }; 7846 }; 7847 }; 7848 7849 qmx-1-1-thermal { 7850 thermal-sensors = <&tsens3 4>; 7851 7852 trips { 7853 qmx-1-1-critical { 7854 temperature = <115000>; 7855 hysteresis = <1000>; 7856 type = "critical"; 7857 }; 7858 }; 7859 }; 7860 7861 qmx-1-2-thermal { 7862 thermal-sensors = <&tsens3 5>; 7863 7864 trips { 7865 qmx-1-2-critical { 7866 temperature = <115000>; 7867 hysteresis = <1000>; 7868 type = "critical"; 7869 }; 7870 }; 7871 }; 7872 7873 qmx-1-3-thermal { 7874 thermal-sensors = <&tsens3 6>; 7875 7876 trips { 7877 qmx-1-3-critical { 7878 temperature = <115000>; 7879 hysteresis = <1000>; 7880 type = "critical"; 7881 }; 7882 }; 7883 }; 7884 7885 qmx-1-4-thermal { 7886 thermal-sensors = <&tsens3 7>; 7887 7888 trips { 7889 qmx-1-4-critical { 7890 temperature = <115000>; 7891 hysteresis = <1000>; 7892 type = "critical"; 7893 }; 7894 }; 7895 }; 7896 7897 aoss-4-thermal { 7898 thermal-sensors = <&tsens4 0>; 7899 7900 trips { 7901 aoss-4-critical { 7902 temperature = <115000>; 7903 hysteresis = <1000>; 7904 type = "critical"; 7905 }; 7906 }; 7907 }; 7908 7909 thermal_cpu_2_0_0: cpu-2-0-0-thermal { 7910 thermal-sensors = <&tsens4 1>; 7911 7912 trips { 7913 cpu-2-0-0-critical { 7914 temperature = <115000>; 7915 hysteresis = <1000>; 7916 type = "critical"; 7917 }; 7918 }; 7919 }; 7920 7921 thermal_cpu_2_0_1: cpu-2-0-1-thermal { 7922 thermal-sensors = <&tsens4 2>; 7923 7924 trips { 7925 cpu-2-0-1-critical { 7926 temperature = <115000>; 7927 hysteresis = <1000>; 7928 type = "critical"; 7929 }; 7930 }; 7931 }; 7932 7933 thermal_cpu_2_1_0: cpu-2-1-0-thermal { 7934 thermal-sensors = <&tsens4 3>; 7935 7936 trips { 7937 cpu-2-1-0-critical { 7938 temperature = <115000>; 7939 hysteresis = <1000>; 7940 type = "critical"; 7941 }; 7942 }; 7943 }; 7944 7945 thermal_cpu_2_1_1: cpu-2-1-1-thermal { 7946 thermal-sensors = <&tsens4 4>; 7947 7948 trips { 7949 cpu-2-1-1-critical { 7950 temperature = <115000>; 7951 hysteresis = <1000>; 7952 type = "critical"; 7953 }; 7954 }; 7955 }; 7956 7957 thermal_cpu_2_2_0: cpu-2-2-0-thermal { 7958 thermal-sensors = <&tsens4 5>; 7959 7960 trips { 7961 cpu-2-2-0-critical { 7962 temperature = <115000>; 7963 hysteresis = <1000>; 7964 type = "critical"; 7965 }; 7966 }; 7967 }; 7968 7969 thermal_cpu_2_2_1: cpu-2-2-1-thermal { 7970 thermal-sensors = <&tsens4 6>; 7971 7972 trips { 7973 cpu-2-2-1-critical { 7974 temperature = <115000>; 7975 hysteresis = <1000>; 7976 type = "critical"; 7977 }; 7978 }; 7979 }; 7980 7981 thermal_cpu_2_3_0: cpu-2-3-0-thermal { 7982 thermal-sensors = <&tsens4 7>; 7983 7984 trips { 7985 cpu-2-3-0-critical { 7986 temperature = <115000>; 7987 hysteresis = <1000>; 7988 type = "critical"; 7989 }; 7990 }; 7991 }; 7992 7993 thermal_cpu_2_3_1: cpu-2-3-1-thermal { 7994 thermal-sensors = <&tsens4 8>; 7995 7996 trips { 7997 cpu-2-3-1-critical { 7998 temperature = <115000>; 7999 hysteresis = <1000>; 8000 type = "critical"; 8001 }; 8002 }; 8003 }; 8004 8005 thermal_cpu_2_4_0: cpu-2-4-0-thermal { 8006 thermal-sensors = <&tsens4 9>; 8007 8008 trips { 8009 cpu-2-4-0-critical { 8010 temperature = <115000>; 8011 hysteresis = <1000>; 8012 type = "critical"; 8013 }; 8014 }; 8015 }; 8016 8017 thermal_cpu_2_4_1: cpu-2-4-1-thermal { 8018 thermal-sensors = <&tsens4 10>; 8019 8020 trips { 8021 cpu-2-4-1-critical { 8022 temperature = <115000>; 8023 hysteresis = <1000>; 8024 type = "critical"; 8025 }; 8026 }; 8027 }; 8028 8029 thermal_cpu_2_5_0: cpu-2-5-0-thermal { 8030 thermal-sensors = <&tsens4 11>; 8031 8032 trips { 8033 cpu-2-5-0-critical { 8034 temperature = <115000>; 8035 hysteresis = <1000>; 8036 type = "critical"; 8037 }; 8038 }; 8039 }; 8040 8041 thermal_cpu_2_5_1: cpu-2-5-1-thermal { 8042 thermal-sensors = <&tsens4 12>; 8043 8044 trips { 8045 cpu-2-5-1-critical { 8046 temperature = <115000>; 8047 hysteresis = <1000>; 8048 type = "critical"; 8049 }; 8050 }; 8051 }; 8052 8053 aoss-5-thermal { 8054 thermal-sensors = <&tsens5 0>; 8055 8056 trips { 8057 aoss-5-critical { 8058 temperature = <115000>; 8059 hysteresis = <1000>; 8060 type = "critical"; 8061 }; 8062 }; 8063 }; 8064 8065 thermal_cpullc_2_0: cpullc-2-0-thermal { 8066 thermal-sensors = <&tsens5 1>; 8067 8068 trips { 8069 cpullc-2-0-critical { 8070 temperature = <115000>; 8071 hysteresis = <1000>; 8072 type = "critical"; 8073 }; 8074 }; 8075 }; 8076 8077 thermal_cpuillc_2_1: cpuillc-2-1-thermal { 8078 thermal-sensors = <&tsens5 2>; 8079 8080 trips { 8081 cpullc-2-1-critical { 8082 temperature = <115000>; 8083 hysteresis = <1000>; 8084 type = "critical"; 8085 }; 8086 }; 8087 }; 8088 8089 thermal_qmx_2_0: qmx-2-0-thermal { 8090 thermal-sensors = <&tsens5 3>; 8091 8092 trips { 8093 qmx-2-0-critical { 8094 temperature = <115000>; 8095 hysteresis = <1000>; 8096 type = "critical"; 8097 }; 8098 }; 8099 }; 8100 8101 thermal_qmx_2_1: qmx-2-1-thermal { 8102 thermal-sensors = <&tsens5 4>; 8103 8104 trips { 8105 qmx-2-1-critical { 8106 temperature = <115000>; 8107 hysteresis = <1000>; 8108 type = "critical"; 8109 }; 8110 }; 8111 }; 8112 8113 thermal_qmx_2_2: qmx-2-2-thermal { 8114 thermal-sensors = <&tsens5 5>; 8115 8116 trips { 8117 qmx-2-2-critical { 8118 temperature = <115000>; 8119 hysteresis = <1000>; 8120 type = "critical"; 8121 }; 8122 }; 8123 }; 8124 8125 thermal_qmx_2_3: qmx-2-3-thermal { 8126 thermal-sensors = <&tsens5 6>; 8127 8128 trips { 8129 qmx-2-3-critical { 8130 temperature = <115000>; 8131 hysteresis = <1000>; 8132 type = "critical"; 8133 }; 8134 }; 8135 }; 8136 8137 thermal_qmx_2_4: qmx-2-4-thermal { 8138 thermal-sensors = <&tsens5 7>; 8139 8140 trips { 8141 qmx-2-4-critical { 8142 temperature = <115000>; 8143 hysteresis = <1000>; 8144 type = "critical"; 8145 }; 8146 }; 8147 }; 8148 8149 thermal_aoss_6: aoss-6-thermal { 8150 thermal-sensors = <&tsens6 0>; 8151 8152 trips { 8153 aoss-6-critical { 8154 temperature = <115000>; 8155 hysteresis = <1000>; 8156 type = "critical"; 8157 }; 8158 }; 8159 }; 8160 8161 thermal_nsphvx_0: nsphvx-0-thermal { 8162 thermal-sensors = <&tsens6 1>; 8163 8164 trips { 8165 nsphvx-0-critical { 8166 temperature = <115000>; 8167 hysteresis = <1000>; 8168 type = "critical"; 8169 }; 8170 }; 8171 }; 8172 8173 thermal_nsphvx_1: nsphvx-1-thermal { 8174 thermal-sensors = <&tsens6 2>; 8175 8176 trips { 8177 nsphvx-1-critical { 8178 temperature = <115000>; 8179 hysteresis = <1000>; 8180 type = "critical"; 8181 }; 8182 }; 8183 }; 8184 8185 thermal_nsphvx_2: nsphvx-2-thermal { 8186 thermal-sensors = <&tsens6 3>; 8187 8188 trips { 8189 nsphvx-2-critical { 8190 temperature = <115000>; 8191 hysteresis = <1000>; 8192 type = "critical"; 8193 }; 8194 }; 8195 }; 8196 8197 thermal_nsphvx_3: nsphvx-3-thermal { 8198 thermal-sensors = <&tsens6 4>; 8199 8200 trips { 8201 nsphvx-3-critical { 8202 temperature = <115000>; 8203 hysteresis = <1000>; 8204 type = "critical"; 8205 }; 8206 }; 8207 }; 8208 8209 thermal_nsphmx_0: nsphmx-0-thermal { 8210 thermal-sensors = <&tsens6 5>; 8211 8212 trips { 8213 nsphmx-0-critical { 8214 temperature = <115000>; 8215 hysteresis = <1000>; 8216 type = "critical"; 8217 }; 8218 }; 8219 }; 8220 8221 thermal_nsphmx_1: nsphmx-1-thermal { 8222 thermal-sensors = <&tsens6 6>; 8223 8224 trips { 8225 nsphmx-1-critical { 8226 temperature = <115000>; 8227 hysteresis = <1000>; 8228 type = "critical"; 8229 }; 8230 }; 8231 }; 8232 8233 thermal_nsphmx_2: nsphmx-2-thermal { 8234 thermal-sensors = <&tsens6 7>; 8235 8236 trips { 8237 nsphmx-2-critical { 8238 temperature = <115000>; 8239 hysteresis = <1000>; 8240 type = "critical"; 8241 }; 8242 }; 8243 }; 8244 8245 thermal_nsphmx_3: nsphmx-3-thermal { 8246 thermal-sensors = <&tsens6 8>; 8247 8248 trips { 8249 nsphmx-3-critical { 8250 temperature = <115000>; 8251 hysteresis = <1000>; 8252 type = "critical"; 8253 }; 8254 }; 8255 }; 8256 8257 thermal_camera_0: camera-0-thermal { 8258 thermal-sensors = <&tsens6 9>; 8259 8260 trips { 8261 camera-0-critical { 8262 temperature = <115000>; 8263 hysteresis = <1000>; 8264 type = "critical"; 8265 }; 8266 }; 8267 }; 8268 8269 thermal_camera_1: camera-1-thermal { 8270 thermal-sensors = <&tsens6 10>; 8271 8272 trips { 8273 camera-1-critical { 8274 temperature = <115000>; 8275 hysteresis = <1000>; 8276 type = "critical"; 8277 }; 8278 }; 8279 }; 8280 8281 thermal_ddr_1: ddr-1-thermal { 8282 thermal-sensors = <&tsens6 11>; 8283 8284 trips { 8285 ddr-1-critical { 8286 temperature = <115000>; 8287 hysteresis = <1000>; 8288 type = "critical"; 8289 }; 8290 }; 8291 }; 8292 8293 thermal_ddr_2: ddr-2-thermal { 8294 thermal-sensors = <&tsens6 12>; 8295 8296 trips { 8297 ddr-2-critical { 8298 temperature = <115000>; 8299 hysteresis = <1000>; 8300 type = "critical"; 8301 }; 8302 }; 8303 }; 8304 8305 thermal_aoss_7: aoss-7-thermal { 8306 thermal-sensors = <&tsens7 0>; 8307 8308 trips { 8309 aoss-7-critical { 8310 temperature = <115000>; 8311 hysteresis = <1000>; 8312 type = "critical"; 8313 }; 8314 }; 8315 }; 8316 8317 thermal_gpu_0_0: gpu-0-0-thermal { 8318 thermal-sensors = <&tsens7 1>; 8319 8320 trips { 8321 trip-point0 { 8322 temperature = <90000>; 8323 hysteresis = <5000>; 8324 type = "hot"; 8325 }; 8326 8327 gpu-0-0-critical { 8328 temperature = <115000>; 8329 hysteresis = <1000>; 8330 type = "critical"; 8331 }; 8332 }; 8333 }; 8334 8335 thermal_gpu_0_1: gpu-0-1-thermal { 8336 thermal-sensors = <&tsens7 2>; 8337 8338 trips { 8339 trip-point0 { 8340 temperature = <90000>; 8341 hysteresis = <5000>; 8342 type = "hot"; 8343 }; 8344 8345 gpu-0-1-critical { 8346 temperature = <115000>; 8347 hysteresis = <1000>; 8348 type = "critical"; 8349 }; 8350 }; 8351 }; 8352 8353 thermal_gpu_0_2: gpu-0-2-thermal { 8354 thermal-sensors = <&tsens7 3>; 8355 8356 trips { 8357 trip-point0 { 8358 temperature = <90000>; 8359 hysteresis = <5000>; 8360 type = "hot"; 8361 }; 8362 8363 gpu-0-2-critical { 8364 temperature = <115000>; 8365 hysteresis = <1000>; 8366 type = "critical"; 8367 }; 8368 }; 8369 }; 8370 8371 thermal_gpu_1_0: gpu-1-0-thermal { 8372 thermal-sensors = <&tsens7 4>; 8373 8374 trips { 8375 trip-point0 { 8376 temperature = <90000>; 8377 hysteresis = <5000>; 8378 type = "hot"; 8379 }; 8380 8381 gpu-1-0-critical { 8382 temperature = <115000>; 8383 hysteresis = <1000>; 8384 type = "critical"; 8385 }; 8386 }; 8387 }; 8388 8389 thermal_gpu_1_1: gpu-1-1-thermal { 8390 thermal-sensors = <&tsens7 5>; 8391 8392 trips { 8393 trip-point0 { 8394 temperature = <90000>; 8395 hysteresis = <5000>; 8396 type = "hot"; 8397 }; 8398 8399 gpu-1-1-critical { 8400 temperature = <115000>; 8401 hysteresis = <1000>; 8402 type = "critical"; 8403 }; 8404 }; 8405 }; 8406 8407 thermal_gpu_1_2: gpu-1-2-thermal { 8408 thermal-sensors = <&tsens7 6>; 8409 8410 trips { 8411 trip-point0 { 8412 temperature = <90000>; 8413 hysteresis = <5000>; 8414 type = "hot"; 8415 }; 8416 8417 gpu-1-2-critical { 8418 temperature = <115000>; 8419 hysteresis = <1000>; 8420 type = "critical"; 8421 }; 8422 }; 8423 }; 8424 8425 thermal_gpu_2_0: gpu-2-0-thermal { 8426 thermal-sensors = <&tsens7 7>; 8427 8428 trips { 8429 trip-point0 { 8430 temperature = <90000>; 8431 hysteresis = <5000>; 8432 type = "hot"; 8433 }; 8434 8435 gpu-2-0-critical { 8436 temperature = <115000>; 8437 hysteresis = <1000>; 8438 type = "critical"; 8439 }; 8440 }; 8441 }; 8442 8443 thermal_gpu_2_1: gpu-2-1-thermal { 8444 thermal-sensors = <&tsens7 8>; 8445 8446 trips { 8447 trip-point0 { 8448 temperature = <90000>; 8449 hysteresis = <5000>; 8450 type = "hot"; 8451 }; 8452 8453 gpu-2-1-critical { 8454 temperature = <115000>; 8455 hysteresis = <1000>; 8456 type = "critical"; 8457 }; 8458 }; 8459 }; 8460 8461 thermal_gpu_2_2: gpu-2-2-thermal { 8462 thermal-sensors = <&tsens7 9>; 8463 8464 trips { 8465 trip-point0 { 8466 temperature = <90000>; 8467 hysteresis = <5000>; 8468 type = "hot"; 8469 }; 8470 8471 gpu-2-2-critical { 8472 temperature = <115000>; 8473 hysteresis = <1000>; 8474 type = "critical"; 8475 }; 8476 }; 8477 }; 8478 8479 thermal_gpu_3_0: gpu-3-0-thermal { 8480 thermal-sensors = <&tsens7 10>; 8481 8482 trips { 8483 trip-point0 { 8484 temperature = <90000>; 8485 hysteresis = <5000>; 8486 type = "hot"; 8487 }; 8488 8489 gpu-3-0-critical { 8490 temperature = <115000>; 8491 hysteresis = <1000>; 8492 type = "critical"; 8493 }; 8494 }; 8495 }; 8496 8497 thermal_gpu_3_1: gpu-3-1-thermal { 8498 thermal-sensors = <&tsens7 11>; 8499 8500 trips { 8501 trip-point0 { 8502 temperature = <90000>; 8503 hysteresis = <5000>; 8504 type = "hot"; 8505 }; 8506 8507 gpu-3-1-critical { 8508 temperature = <115000>; 8509 hysteresis = <1000>; 8510 type = "critical"; 8511 }; 8512 }; 8513 }; 8514 8515 thermal_gpu_3_2: gpu-3-2-thermal { 8516 thermal-sensors = <&tsens7 12>; 8517 8518 trips { 8519 trip-point0 { 8520 temperature = <90000>; 8521 hysteresis = <5000>; 8522 type = "hot"; 8523 }; 8524 8525 gpu-3-2-critical { 8526 temperature = <115000>; 8527 hysteresis = <1000>; 8528 type = "critical"; 8529 }; 8530 }; 8531 }; 8532 8533 thermal_gpuss_0: gpuss-0-thermal { 8534 thermal-sensors = <&tsens7 13>; 8535 8536 trips { 8537 trip-point0 { 8538 temperature = <90000>; 8539 hysteresis = <5000>; 8540 type = "hot"; 8541 }; 8542 8543 gpuss-0-critical { 8544 temperature = <115000>; 8545 hysteresis = <1000>; 8546 type = "critical"; 8547 }; 8548 }; 8549 }; 8550 8551 thermal_gpuss_1: gpuss-1-thermal { 8552 thermal-sensors = <&tsens7 14>; 8553 8554 trips { 8555 trip-point0 { 8556 temperature = <90000>; 8557 hysteresis = <5000>; 8558 type = "hot"; 8559 }; 8560 8561 gpuss-1-critical { 8562 temperature = <115000>; 8563 hysteresis = <1000>; 8564 type = "critical"; 8565 }; 8566 }; 8567 }; 8568 }; 8569 8570 tpdm-cdsp-llm { 8571 compatible = "qcom,coresight-static-tpdm"; 8572 qcom,cmb-element-bits = <32>; 8573 8574 out-ports { 8575 port { 8576 cdsp_llm_tpdm_out: endpoint { 8577 remote-endpoint = <&cdsp_tpda_in1>; 8578 }; 8579 }; 8580 }; 8581 }; 8582 8583 tpdm-cdsp-llm2 { 8584 compatible = "qcom,coresight-static-tpdm"; 8585 qcom,cmb-element-bits = <32>; 8586 8587 out-ports { 8588 port { 8589 cdsp_llm2_tpdm_out: endpoint { 8590 remote-endpoint = <&cdsp_tpda_in2>; 8591 }; 8592 }; 8593 }; 8594 }; 8595 8596 tpdm-cdsp-cmsr { 8597 compatible = "qcom,coresight-static-tpdm"; 8598 8599 qcom,cmb-element-bits = <32>; 8600 qcom,dsb-element-bits = <32>; 8601 8602 out-ports { 8603 port { 8604 cdsp_cmsr_tpdm_out: endpoint { 8605 remote-endpoint = <&cdsp_tpda_in3>; 8606 }; 8607 }; 8608 }; 8609 }; 8610 8611 tpdm-cdsp-cmsr2 { 8612 compatible = "qcom,coresight-static-tpdm"; 8613 8614 qcom,cmb-element-bits = <32>; 8615 qcom,dsb-element-bits = <32>; 8616 8617 out-ports { 8618 port { 8619 cdsp_cmsr2_tpdm_out: endpoint { 8620 remote-endpoint = <&cdsp_tpda_in4>; 8621 }; 8622 }; 8623 }; 8624 }; 8625}; 8626