1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-dispcc.h> 7#include <dt-bindings/clock/qcom,glymur-gcc.h> 8#include <dt-bindings/clock/qcom,glymur-gpucc.h> 9#include <dt-bindings/clock/qcom,glymur-tcsr.h> 10#include <dt-bindings/clock/qcom,glymur-videocc.h> 11#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/spmi/spmi.h> 25 26#include "glymur-ipcc.h" 27 28/ { 29 interrupt-parent = <&intc>; 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "qcom,oryon-2-2"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 43 power-domain-names = "psci", "perf"; 44 next-level-cache = <&l2_0>; 45 #cooling-cells = <2>; 46 47 l2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 cache-unified; 51 }; 52 }; 53 54 cpu1: cpu@100 { 55 device_type = "cpu"; 56 compatible = "qcom,oryon-2-2"; 57 reg = <0x0 0x100>; 58 enable-method = "psci"; 59 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 60 power-domain-names = "psci", "perf"; 61 next-level-cache = <&l2_0>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@200 { 66 device_type = "cpu"; 67 compatible = "qcom,oryon-2-2"; 68 reg = <0x0 0x200>; 69 enable-method = "psci"; 70 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 71 power-domain-names = "psci", "perf"; 72 next-level-cache = <&l2_0>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu3: cpu@300 { 77 device_type = "cpu"; 78 compatible = "qcom,oryon-2-2"; 79 reg = <0x0 0x300>; 80 enable-method = "psci"; 81 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 82 power-domain-names = "psci", "perf"; 83 next-level-cache = <&l2_0>; 84 #cooling-cells = <2>; 85 }; 86 87 cpu4: cpu@400 { 88 device_type = "cpu"; 89 compatible = "qcom,oryon-2-2"; 90 reg = <0x0 0x400>; 91 enable-method = "psci"; 92 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 93 power-domain-names = "psci", "perf"; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu5: cpu@500 { 99 device_type = "cpu"; 100 compatible = "qcom,oryon-2-2"; 101 reg = <0x0 0x500>; 102 enable-method = "psci"; 103 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 104 power-domain-names = "psci", "perf"; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu6: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "qcom,oryon-2-1"; 112 reg = <0x0 0x10000>; 113 enable-method = "psci"; 114 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 115 power-domain-names = "psci", "perf"; 116 next-level-cache = <&l2_1>; 117 #cooling-cells = <2>; 118 119 l2_1: l2-cache { 120 compatible = "cache"; 121 cache-level = <2>; 122 cache-unified; 123 }; 124 }; 125 126 cpu7: cpu@10100 { 127 device_type = "cpu"; 128 compatible = "qcom,oryon-2-1"; 129 reg = <0x0 0x10100>; 130 enable-method = "psci"; 131 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 132 power-domain-names = "psci", "perf"; 133 next-level-cache = <&l2_1>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu8: cpu@10200 { 138 device_type = "cpu"; 139 compatible = "qcom,oryon-2-1"; 140 reg = <0x0 0x10200>; 141 enable-method = "psci"; 142 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 143 power-domain-names = "psci", "perf"; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu9: cpu@10300 { 149 device_type = "cpu"; 150 compatible = "qcom,oryon-2-1"; 151 reg = <0x0 0x10300>; 152 enable-method = "psci"; 153 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 154 power-domain-names = "psci", "perf"; 155 next-level-cache = <&l2_1>; 156 #cooling-cells = <2>; 157 }; 158 159 cpu10: cpu@10400 { 160 device_type = "cpu"; 161 compatible = "qcom,oryon-2-1"; 162 reg = <0x0 0x10400>; 163 enable-method = "psci"; 164 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 165 power-domain-names = "psci", "perf"; 166 next-level-cache = <&l2_1>; 167 #cooling-cells = <2>; 168 }; 169 170 cpu11: cpu@10500 { 171 device_type = "cpu"; 172 compatible = "qcom,oryon-2-1"; 173 reg = <0x0 0x10500>; 174 enable-method = "psci"; 175 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 176 power-domain-names = "psci", "perf"; 177 next-level-cache = <&l2_1>; 178 #cooling-cells = <2>; 179 }; 180 181 cpu12: cpu@20000 { 182 device_type = "cpu"; 183 compatible = "qcom,oryon-2-1"; 184 reg = <0x0 0x20000>; 185 enable-method = "psci"; 186 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 187 power-domain-names = "psci", "perf"; 188 next-level-cache = <&l2_2>; 189 #cooling-cells = <2>; 190 191 l2_2: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 }; 196 }; 197 198 cpu13: cpu@20100 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon-2-1"; 201 reg = <0x0 0x20100>; 202 enable-method = "psci"; 203 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 204 power-domain-names = "psci", "perf"; 205 next-level-cache = <&l2_2>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu14: cpu@20200 { 210 device_type = "cpu"; 211 compatible = "qcom,oryon-2-1"; 212 reg = <0x0 0x20200>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 215 power-domain-names = "psci", "perf"; 216 next-level-cache = <&l2_2>; 217 #cooling-cells = <2>; 218 }; 219 220 cpu15: cpu@20300 { 221 device_type = "cpu"; 222 compatible = "qcom,oryon-2-1"; 223 reg = <0x0 0x20300>; 224 enable-method = "psci"; 225 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 226 power-domain-names = "psci", "perf"; 227 next-level-cache = <&l2_2>; 228 #cooling-cells = <2>; 229 }; 230 231 cpu16: cpu@20400 { 232 device_type = "cpu"; 233 compatible = "qcom,oryon-2-1"; 234 reg = <0x0 0x20400>; 235 enable-method = "psci"; 236 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 237 power-domain-names = "psci", "perf"; 238 next-level-cache = <&l2_2>; 239 #cooling-cells = <2>; 240 }; 241 242 cpu17: cpu@20500 { 243 device_type = "cpu"; 244 compatible = "qcom,oryon-2-1"; 245 reg = <0x0 0x20500>; 246 enable-method = "psci"; 247 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 248 power-domain-names = "psci", "perf"; 249 next-level-cache = <&l2_2>; 250 #cooling-cells = <2>; 251 }; 252 253 cpu-map { 254 cluster0 { 255 core0 { 256 cpu = <&cpu0>; 257 }; 258 259 core1 { 260 cpu = <&cpu1>; 261 }; 262 263 core2 { 264 cpu = <&cpu2>; 265 }; 266 267 core3 { 268 cpu = <&cpu3>; 269 }; 270 271 core4 { 272 cpu = <&cpu4>; 273 }; 274 275 core5 { 276 cpu = <&cpu5>; 277 }; 278 }; 279 280 cluster1 { 281 core0 { 282 cpu = <&cpu6>; 283 }; 284 285 core1 { 286 cpu = <&cpu7>; 287 }; 288 289 core2 { 290 cpu = <&cpu8>; 291 }; 292 293 core3 { 294 cpu = <&cpu9>; 295 }; 296 297 core4 { 298 cpu = <&cpu10>; 299 }; 300 301 core5 { 302 cpu = <&cpu11>; 303 }; 304 }; 305 306 cpu_map_cluster2: cluster2 { 307 core0 { 308 cpu = <&cpu12>; 309 }; 310 311 core1 { 312 cpu = <&cpu13>; 313 }; 314 315 core2 { 316 cpu = <&cpu14>; 317 }; 318 319 core3 { 320 cpu = <&cpu15>; 321 }; 322 323 core4 { 324 cpu = <&cpu16>; 325 }; 326 327 core5 { 328 cpu = <&cpu17>; 329 }; 330 }; 331 }; 332 333 idle-states { 334 entry-method = "psci"; 335 336 cpu_c4: cpu-sleep-0 { 337 compatible = "arm,idle-state"; 338 idle-state-name = "ret"; 339 arm,psci-suspend-param = <0x00000004>; 340 entry-latency-us = <180>; 341 exit-latency-us = <320>; 342 min-residency-us = <1000>; 343 }; 344 }; 345 346 domain-idle-states { 347 cluster_cl5: cluster-sleep-0 { 348 compatible = "domain-idle-state"; 349 arm,psci-suspend-param = <0x01000054>; 350 entry-latency-us = <2000>; 351 exit-latency-us = <2000>; 352 min-residency-us = <9000>; 353 }; 354 355 domain_ss3: domain-sleep-0 { 356 compatible = "domain-idle-state"; 357 arm,psci-suspend-param = <0x0200c354>; 358 entry-latency-us = <2800>; 359 exit-latency-us = <4400>; 360 min-residency-us = <10150>; 361 }; 362 }; 363 }; 364 365 firmware { 366 scm: scm { 367 compatible = "qcom,scm-glymur", "qcom,scm"; 368 qcom,dload-mode = <&tcsr 0x4000>; 369 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 370 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 371 }; 372 373 scmi { 374 compatible = "arm,scmi"; 375 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 376 mbox-names = "tx", "rx"; 377 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 378 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 scmi_perf: protocol@13 { 383 reg = <0x13>; 384 #power-domain-cells = <1>; 385 }; 386 }; 387 }; 388 389 clk_virt: interconnect-0 { 390 compatible = "qcom,glymur-clk-virt"; 391 #interconnect-cells = <2>; 392 qcom,bcm-voters = <&apps_bcm_voter>; 393 }; 394 395 mc_virt: interconnect-1 { 396 compatible = "qcom,glymur-mc-virt"; 397 #interconnect-cells = <2>; 398 qcom,bcm-voters = <&apps_bcm_voter>; 399 }; 400 401 pmu { 402 compatible = "arm,armv8-pmuv3"; 403 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 404 }; 405 406 psci { 407 compatible = "arm,psci-1.0"; 408 method = "smc"; 409 410 cpu_pd0: power-domain-cpu0 { 411 #power-domain-cells = <0>; 412 power-domains = <&cluster0_pd>; 413 domain-idle-states = <&cpu_c4>; 414 }; 415 416 cpu_pd1: power-domain-cpu1 { 417 #power-domain-cells = <0>; 418 power-domains = <&cluster0_pd>; 419 domain-idle-states = <&cpu_c4>; 420 }; 421 422 cpu_pd2: power-domain-cpu2 { 423 #power-domain-cells = <0>; 424 power-domains = <&cluster0_pd>; 425 domain-idle-states = <&cpu_c4>; 426 }; 427 428 cpu_pd3: power-domain-cpu3 { 429 #power-domain-cells = <0>; 430 power-domains = <&cluster0_pd>; 431 domain-idle-states = <&cpu_c4>; 432 }; 433 434 cpu_pd4: power-domain-cpu4 { 435 #power-domain-cells = <0>; 436 power-domains = <&cluster0_pd>; 437 domain-idle-states = <&cpu_c4>; 438 }; 439 440 cpu_pd5: power-domain-cpu5 { 441 #power-domain-cells = <0>; 442 power-domains = <&cluster0_pd>; 443 domain-idle-states = <&cpu_c4>; 444 }; 445 446 cpu_pd6: power-domain-cpu6 { 447 #power-domain-cells = <0>; 448 power-domains = <&cluster1_pd>; 449 domain-idle-states = <&cpu_c4>; 450 }; 451 452 cpu_pd7: power-domain-cpu7 { 453 #power-domain-cells = <0>; 454 power-domains = <&cluster1_pd>; 455 domain-idle-states = <&cpu_c4>; 456 }; 457 458 cpu_pd8: power-domain-cpu8 { 459 #power-domain-cells = <0>; 460 power-domains = <&cluster1_pd>; 461 domain-idle-states = <&cpu_c4>; 462 }; 463 464 cpu_pd9: power-domain-cpu9 { 465 #power-domain-cells = <0>; 466 power-domains = <&cluster1_pd>; 467 domain-idle-states = <&cpu_c4>; 468 }; 469 470 cpu_pd10: power-domain-cpu10 { 471 #power-domain-cells = <0>; 472 power-domains = <&cluster1_pd>; 473 domain-idle-states = <&cpu_c4>; 474 }; 475 476 cpu_pd11: power-domain-cpu11 { 477 #power-domain-cells = <0>; 478 power-domains = <&cluster1_pd>; 479 domain-idle-states = <&cpu_c4>; 480 }; 481 482 cpu_pd12: power-domain-cpu12 { 483 #power-domain-cells = <0>; 484 power-domains = <&cluster2_pd>; 485 domain-idle-states = <&cpu_c4>; 486 }; 487 488 cpu_pd13: power-domain-cpu13 { 489 #power-domain-cells = <0>; 490 power-domains = <&cluster2_pd>; 491 domain-idle-states = <&cpu_c4>; 492 }; 493 494 cpu_pd14: power-domain-cpu14 { 495 #power-domain-cells = <0>; 496 power-domains = <&cluster2_pd>; 497 domain-idle-states = <&cpu_c4>; 498 }; 499 500 cpu_pd15: power-domain-cpu15 { 501 #power-domain-cells = <0>; 502 power-domains = <&cluster2_pd>; 503 domain-idle-states = <&cpu_c4>; 504 }; 505 506 cpu_pd16: power-domain-cpu16 { 507 #power-domain-cells = <0>; 508 power-domains = <&cluster2_pd>; 509 domain-idle-states = <&cpu_c4>; 510 }; 511 512 cpu_pd17: power-domain-cpu17 { 513 #power-domain-cells = <0>; 514 power-domains = <&cluster2_pd>; 515 domain-idle-states = <&cpu_c4>; 516 }; 517 518 cluster0_pd: power-domain-cpu-cluster0 { 519 #power-domain-cells = <0>; 520 power-domains = <&system_pd>; 521 domain-idle-states = <&cluster_cl5>; 522 }; 523 524 cluster1_pd: power-domain-cpu-cluster1 { 525 #power-domain-cells = <0>; 526 power-domains = <&system_pd>; 527 domain-idle-states = <&cluster_cl5>; 528 }; 529 530 cluster2_pd: power-domain-cpu-cluster2 { 531 #power-domain-cells = <0>; 532 power-domains = <&system_pd>; 533 domain-idle-states = <&cluster_cl5>; 534 }; 535 536 system_pd: power-domain-system { 537 #power-domain-cells = <0>; 538 domain-idle-states = <&domain_ss3>; 539 }; 540 }; 541 542 reserved-memory { 543 #address-cells = <2>; 544 #size-cells = <2>; 545 ranges; 546 547 pdp_mem: pdp@81400000 { 548 reg = <0x0 0x81400000 0x0 0x100000>; 549 no-map; 550 }; 551 552 aop_cmd_db_mem: aop-cmd-db@81c60000 { 553 compatible = "qcom,cmd-db"; 554 reg = <0x0 0x81c60000 0x0 0x20000>; 555 no-map; 556 }; 557 558 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 559 reg = <0x0 0x81e00000 0x0 0x200000>; 560 no-map; 561 }; 562 563 oobdaretag_mem: oobdaretag@86e10000 { 564 reg = <0x0 0x86e10000 0x0 0x360000>; 565 no-map; 566 }; 567 568 oob_secure_mem: oob-secure@87170000 { 569 reg = <0x0 0x87170000 0x0 0xbc0000>; 570 no-map; 571 }; 572 573 oobdtbqc_mem: oobdtbqc@87d30000 { 574 reg = <0x0 0x87d30000 0x0 0x20000>; 575 no-map; 576 }; 577 578 oobdtboem_mem: oobdtboem@87d50000 { 579 reg = <0x0 0x87d50000 0x0 0x20000>; 580 no-map; 581 }; 582 583 oob_nonsecure_mem: oob-nonsecure@87e00000 { 584 reg = <0x0 0x87e00000 0x0 0xc00000>; 585 no-map; 586 }; 587 588 spss_region_mem: spss@88a00000 { 589 reg = <0x0 0x88a00000 0x0 0x400000>; 590 no-map; 591 }; 592 593 soccpdtb_mem: soccpdtb@892e0000 { 594 reg = <0x0 0x892e0000 0x0 0x20000>; 595 no-map; 596 }; 597 598 soccp_mem: soccp@89300000 { 599 reg = <0x0 0x89300000 0x0 0x400000>; 600 no-map; 601 }; 602 603 cvp_mem: cvp@89700000 { 604 reg = <0x0 0x89700000 0x0 0x700000>; 605 no-map; 606 }; 607 608 adspslpi_mem: adspslpi@89e00000 { 609 reg = <0x0 0x89e00000 0x0 0x3a00000>; 610 no-map; 611 }; 612 613 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 614 reg = <0x0 0x8d800000 0x0 0x80000>; 615 no-map; 616 }; 617 618 cdsp_mem: cdsp@8d900000 { 619 reg = <0x0 0x8d900000 0x0 0x4000000>; 620 no-map; 621 }; 622 623 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 624 reg = <0x0 0x91900000 0x0 0x80000>; 625 no-map; 626 }; 627 628 gpu_microcode_mem: gpu-microcode@919fe000 { 629 reg = <0x0 0x919fe000 0x0 0x2000>; 630 no-map; 631 }; 632 633 camera_mem: camera@91a00000 { 634 reg = <0x0 0x91a00000 0x0 0x800000>; 635 no-map; 636 }; 637 638 av1_encoder_mem: av1-encoder@92200000 { 639 reg = <0x0 0x92200000 0x0 0x700000>; 640 no-map; 641 }; 642 643 video_mem: video@92900000 { 644 reg = <0x0 0x92900000 0x0 0xc00000>; 645 no-map; 646 }; 647 648 smem_mem: smem@ffe00000 { 649 compatible = "qcom,smem"; 650 reg = <0x0 0xffe00000 0x0 0x200000>; 651 hwlocks = <&tcsr_mutex 3>; 652 no-map; 653 }; 654 }; 655 656 smp2p-adsp { 657 compatible = "qcom,smp2p"; 658 659 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 660 IPCC_MPROC_SIGNAL_SMP2P 661 IRQ_TYPE_EDGE_RISING>; 662 663 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 664 665 qcom,smem = <443>, <429>; 666 qcom,local-pid = <0>; 667 qcom,remote-pid = <2>; 668 669 smp2p_adsp_out: master-kernel { 670 qcom,entry-name = "master-kernel"; 671 #qcom,smem-state-cells = <1>; 672 }; 673 674 smp2p_adsp_in: slave-kernel { 675 qcom,entry-name = "slave-kernel"; 676 interrupt-controller; 677 #interrupt-cells = <2>; 678 }; 679 }; 680 681 smp2p-cdsp { 682 compatible = "qcom,smp2p"; 683 684 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 685 IPCC_MPROC_SIGNAL_SMP2P 686 IRQ_TYPE_EDGE_RISING>; 687 688 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 689 690 qcom,smem = <94>, <432>; 691 qcom,local-pid = <0>; 692 qcom,remote-pid = <5>; 693 694 smp2p_cdsp_out: master-kernel { 695 qcom,entry-name = "master-kernel"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 smp2p_cdsp_in: slave-kernel { 700 qcom,entry-name = "slave-kernel"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 }; 705 706 smp2p-soccp { 707 compatible = "qcom,smp2p"; 708 709 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 710 IPCC_MPROC_SIGNAL_SMP2P 711 IRQ_TYPE_EDGE_RISING>; 712 713 mboxes = <&ipcc IPCC_MPROC_SOCCP 714 IPCC_MPROC_SIGNAL_SMP2P>; 715 716 qcom,smem = <617>, <616>; 717 qcom,local-pid = <0>; 718 qcom,remote-pid = <19>; 719 720 soccp_smp2p_out: master-kernel { 721 qcom,entry-name = "master-kernel"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 soccp_smp2p_in: slave-kernel { 726 qcom,entry-name = "slave-kernel"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 }; 731 732 soc: soc@0 { 733 compatible = "simple-bus"; 734 #address-cells = <2>; 735 #size-cells = <2>; 736 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 737 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 738 739 gcc: clock-controller@100000 { 740 compatible = "qcom,glymur-gcc"; 741 reg = <0x0 0x00100000 0x0 0x1f9000>; 742 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 743 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 744 <&sleep_clk>, /* Sleep */ 745 <0>, /* USB 0 Phy DP0 GMUX */ 746 <0>, /* USB 0 Phy DP1 GMUX */ 747 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 748 <0>, /* USB 0 Phy PIPEGMUX */ 749 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 750 <0>, /* USB 1 Phy DP0 GMUX 2 */ 751 <0>, /* USB 1 Phy DP1 GMUX 2 */ 752 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 753 <0>, /* USB 1 Phy PIPEGMUX */ 754 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 755 <0>, /* USB 2 Phy DP0 GMUX 2 */ 756 <0>, /* USB 2 Phy DP1 GMUX 2 */ 757 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 758 <0>, /* USB 2 Phy PIPEGMUX */ 759 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 760 <0>, /* PCIe 3a */ 761 <&pcie3b_phy>, /* PCIe 3b */ 762 <&pcie4_phy>, /* PCIe 4 */ 763 <&pcie5_phy>, /* PCIe 5 */ 764 <&pcie6_phy>, /* PCIe 6 */ 765 <0>, /* QUSB4 0 PHY RX 0 */ 766 <0>, /* QUSB4 0 PHY RX 1 */ 767 <0>, /* QUSB4 1 PHY RX 0 */ 768 <0>, /* QUSB4 1 PHY RX 1 */ 769 <0>, /* QUSB4 2 PHY RX 0 */ 770 <0>, /* QUSB4 2 PHY RX 1 */ 771 <0>, /* UFS PHY RX Symbol 0 */ 772 <0>, /* UFS PHY RX Symbol 1 */ 773 <0>, /* UFS PHY TX Symbol 0 */ 774 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 775 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 776 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 777 <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, 778 <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, 779 <0>, /* USB4 PHY 0 pcie pipe */ 780 <0>, /* USB4 PHY 0 Max pipe */ 781 <0>, /* USB4 PHY 1 pcie pipe */ 782 <0>, /* USB4 PHY 1 Max pipe */ 783 <0>, /* USB4 PHY 2 pcie */ 784 <0>; /* USB4 PHY 2 Max */ 785 #clock-cells = <1>; 786 #reset-cells = <1>; 787 #power-domain-cells = <1>; 788 }; 789 790 gpi_dma2: dma-controller@800000 { 791 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 792 reg = <0x0 0x00800000 0x0 0x60000>; 793 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 809 dma-channels = <16>; 810 dma-channel-mask = <0x3f>; 811 #dma-cells = <3>; 812 iommus = <&apps_smmu 0xd76 0x0>; 813 }; 814 815 qupv3_2: geniqup@8c0000 { 816 compatible = "qcom,geni-se-qup"; 817 reg = <0x0 0x008c0000 0x0 0x3000>; 818 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 819 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 820 clock-names = "m-ahb", 821 "s-ahb"; 822 iommus = <&apps_smmu 0xd63 0x0>; 823 #address-cells = <2>; 824 #size-cells = <2>; 825 ranges; 826 827 i2c16: i2c@880000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0x0 0x00880000 0x0 0x4000>; 830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 832 clock-names = "se"; 833 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 834 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 835 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 836 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 837 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 838 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 839 interconnect-names = "qup-core", 840 "qup-config", 841 "qup-memory"; 842 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 843 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 844 dma-names = "tx", 845 "rx"; 846 pinctrl-0 = <&qup_i2c16_data_clk>; 847 pinctrl-names = "default"; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 851 status = "disabled"; 852 }; 853 854 spi16: spi@880000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0x0 0x00880000 0x0 0x4000>; 857 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 859 clock-names = "se"; 860 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 861 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 862 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 863 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 864 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 865 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 866 interconnect-names = "qup-core", 867 "qup-config", 868 "qup-memory"; 869 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 870 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 871 dma-names = "tx", 872 "rx"; 873 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 874 pinctrl-names = "default"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 878 status = "disabled"; 879 }; 880 881 i2c17: i2c@884000 { 882 compatible = "qcom,geni-i2c"; 883 reg = <0x0 0x00884000 0x0 0x4000>; 884 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 886 clock-names = "se"; 887 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 888 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 889 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 890 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 891 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 892 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 893 interconnect-names = "qup-core", 894 "qup-config", 895 "qup-memory"; 896 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 897 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 898 dma-names = "tx", 899 "rx"; 900 pinctrl-0 = <&qup_i2c17_data_clk>; 901 pinctrl-names = "default"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 905 status = "disabled"; 906 }; 907 908 spi17: spi@884000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0x0 0x00884000 0x0 0x4000>; 911 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 913 clock-names = "se"; 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 915 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 916 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 917 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 918 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 920 interconnect-names = "qup-core", 921 "qup-config", 922 "qup-memory"; 923 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 924 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 925 dma-names = "tx", 926 "rx"; 927 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 928 pinctrl-names = "default"; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 status = "disabled"; 933 }; 934 935 i2c18: i2c@888000 { 936 compatible = "qcom,geni-i2c"; 937 reg = <0x0 0x00888000 0x0 0x4000>; 938 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 940 clock-names = "se"; 941 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 942 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 943 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 944 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 945 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 946 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 947 interconnect-names = "qup-core", 948 "qup-config", 949 "qup-memory"; 950 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 951 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 952 dma-names = "tx", 953 "rx"; 954 pinctrl-0 = <&qup_i2c18_data_clk>; 955 pinctrl-names = "default"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 959 status = "disabled"; 960 }; 961 962 spi18: spi@888000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0x0 0x00888000 0x0 0x4000>; 965 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 967 clock-names = "se"; 968 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 969 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 970 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 971 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 972 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 973 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 974 interconnect-names = "qup-core", 975 "qup-config", 976 "qup-memory"; 977 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 978 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 979 dma-names = "tx", 980 "rx"; 981 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 982 pinctrl-names = "default"; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 986 status = "disabled"; 987 }; 988 989 i2c19: i2c@88c000 { 990 compatible = "qcom,geni-i2c"; 991 reg = <0x0 0x0088c000 0x0 0x4000>; 992 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 994 clock-names = "se"; 995 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 996 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 997 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 998 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 999 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1000 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1001 interconnect-names = "qup-core", 1002 "qup-config", 1003 "qup-memory"; 1004 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1005 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1006 dma-names = "tx", 1007 "rx"; 1008 pinctrl-0 = <&qup_i2c19_data_clk>; 1009 pinctrl-names = "default"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 1013 status = "disabled"; 1014 }; 1015 1016 spi19: spi@88c000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0x0 0x0088c000 0x0 0x4000>; 1019 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1021 clock-names = "se"; 1022 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1023 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1024 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1025 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1026 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1028 interconnect-names = "qup-core", 1029 "qup-config", 1030 "qup-memory"; 1031 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1032 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1033 dma-names = "tx", 1034 "rx"; 1035 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1036 pinctrl-names = "default"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 status = "disabled"; 1041 }; 1042 1043 uart19: serial@88c000 { 1044 compatible = "qcom,geni-uart"; 1045 reg = <0x0 0x0088c000 0x0 0x4000>; 1046 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1048 clock-names = "se"; 1049 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1050 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1051 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1052 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1053 interconnect-names = "qup-core", 1054 "qup-config"; 1055 pinctrl-0 = <&qup_uart19_default>; 1056 pinctrl-names = "default"; 1057 1058 status = "disabled"; 1059 }; 1060 1061 i2c20: i2c@890000 { 1062 compatible = "qcom,geni-i2c"; 1063 reg = <0x0 0x00890000 0x0 0x4000>; 1064 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1066 clock-names = "se"; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1068 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1069 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1070 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1071 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1073 interconnect-names = "qup-core", 1074 "qup-config", 1075 "qup-memory"; 1076 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1077 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1078 dma-names = "tx", 1079 "rx"; 1080 pinctrl-0 = <&qup_i2c20_data_clk>; 1081 pinctrl-names = "default"; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 status = "disabled"; 1086 }; 1087 1088 spi20: spi@890000 { 1089 compatible = "qcom,geni-spi"; 1090 reg = <0x0 0x00890000 0x0 0x4000>; 1091 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1093 clock-names = "se"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1098 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1100 interconnect-names = "qup-core", 1101 "qup-config", 1102 "qup-memory"; 1103 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1104 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1105 dma-names = "tx", 1106 "rx"; 1107 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1108 pinctrl-names = "default"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 1112 status = "disabled"; 1113 }; 1114 1115 i2c21: i2c@894000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0x0 0x00894000 0x0 0x4000>; 1118 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1120 clock-names = "se"; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1122 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1124 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1125 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1131 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1132 dma-names = "tx", 1133 "rx"; 1134 pinctrl-0 = <&qup_i2c21_data_clk>; 1135 pinctrl-names = "default"; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 1139 status = "disabled"; 1140 }; 1141 1142 spi21: spi@894000 { 1143 compatible = "qcom,geni-spi"; 1144 reg = <0x0 0x00894000 0x0 0x4000>; 1145 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1147 clock-names = "se"; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1149 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1150 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1151 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1152 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1153 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1154 interconnect-names = "qup-core", 1155 "qup-config", 1156 "qup-memory"; 1157 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1158 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1159 dma-names = "tx", 1160 "rx"; 1161 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1162 pinctrl-names = "default"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 1166 status = "disabled"; 1167 }; 1168 1169 uart21: serial@894000 { 1170 compatible = "qcom,geni-debug-uart"; 1171 reg = <0x0 0x00894000 0x0 0x4000>; 1172 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1174 clock-names = "se"; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1176 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1177 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1178 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1179 interconnect-names = "qup-core", 1180 "qup-config"; 1181 pinctrl-0 = <&qup_uart21_default>; 1182 pinctrl-names = "default"; 1183 }; 1184 1185 i2c22: i2c@898000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0x0 0x00898000 0x0 0x4000>; 1188 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1190 clock-names = "se"; 1191 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1192 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1193 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1194 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1195 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1196 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1197 interconnect-names = "qup-core", 1198 "qup-config", 1199 "qup-memory"; 1200 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1201 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1202 dma-names = "tx", 1203 "rx"; 1204 pinctrl-0 = <&qup_i2c22_data_clk>; 1205 pinctrl-names = "default"; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 1209 status = "disabled"; 1210 }; 1211 1212 spi22: spi@898000 { 1213 compatible = "qcom,geni-spi"; 1214 reg = <0x0 0x00898000 0x0 0x4000>; 1215 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1217 clock-names = "se"; 1218 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1219 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1220 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1221 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1222 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1224 interconnect-names = "qup-core", 1225 "qup-config", 1226 "qup-memory"; 1227 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1228 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1229 dma-names = "tx", 1230 "rx"; 1231 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1232 pinctrl-names = "default"; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 1236 status = "disabled"; 1237 }; 1238 1239 uart22: serial@898000 { 1240 compatible = "qcom,geni-uart"; 1241 reg = <0x0 0x00898000 0x0 0x4000>; 1242 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1244 clock-names = "se"; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1246 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1247 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1248 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1249 interconnect-names = "qup-core", 1250 "qup-config"; 1251 pinctrl-0 = <&qup_uart22_default>; 1252 pinctrl-names = "default"; 1253 1254 status = "disabled"; 1255 }; 1256 1257 i2c23: i2c@89c000 { 1258 compatible = "qcom,geni-i2c"; 1259 reg = <0x0 0x0089c000 0x0 0x4000>; 1260 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1262 clock-names = "se"; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1264 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1265 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1266 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1267 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1268 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1269 interconnect-names = "qup-core", 1270 "qup-config", 1271 "qup-memory"; 1272 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1273 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1274 dma-names = "tx", 1275 "rx"; 1276 pinctrl-0 = <&qup_i2c23_data_clk>; 1277 pinctrl-names = "default"; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 1281 status = "disabled"; 1282 }; 1283 1284 spi23: spi@89c000 { 1285 compatible = "qcom,geni-spi"; 1286 reg = <0x0 0x0089c000 0x0 0x4000>; 1287 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1289 clock-names = "se"; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1291 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1292 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1293 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1294 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1295 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1296 interconnect-names = "qup-core", 1297 "qup-config", 1298 "qup-memory"; 1299 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1300 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1301 dma-names = "tx", 1302 "rx"; 1303 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1304 pinctrl-names = "default"; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 1308 status = "disabled"; 1309 }; 1310 }; 1311 1312 gpi_dma1: dma-controller@a00000 { 1313 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1314 reg = <0x0 0x00a00000 0x0 0x60000>; 1315 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1331 dma-channels = <16>; 1332 dma-channel-mask = <0x3f>; 1333 #dma-cells = <3>; 1334 iommus = <&apps_smmu 0xcb6 0x0>; 1335 }; 1336 1337 qupv3_1: geniqup@ac0000 { 1338 compatible = "qcom,geni-se-qup"; 1339 reg = <0x0 0x00ac0000 0x0 0x3000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1341 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1342 clock-names = "m-ahb", 1343 "s-ahb"; 1344 iommus = <&apps_smmu 0xca3 0x0>; 1345 #address-cells = <2>; 1346 #size-cells = <2>; 1347 ranges; 1348 1349 i2c8: i2c@a80000 { 1350 compatible = "qcom,geni-i2c"; 1351 reg = <0x0 0x00a80000 0x0 0x4000>; 1352 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1354 clock-names = "se"; 1355 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1356 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1357 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1358 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1359 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1360 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1361 interconnect-names = "qup-core", 1362 "qup-config", 1363 "qup-memory"; 1364 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1365 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1366 dma-names = "tx", 1367 "rx"; 1368 pinctrl-0 = <&qup_i2c8_data_clk>; 1369 pinctrl-names = "default"; 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 1373 status = "disabled"; 1374 }; 1375 1376 spi8: spi@a80000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0x0 0x00a80000 0x0 0x4000>; 1379 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1381 clock-names = "se"; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1383 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1384 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1385 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1386 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1387 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1388 interconnect-names = "qup-core", 1389 "qup-config", 1390 "qup-memory"; 1391 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1392 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1393 dma-names = "tx", 1394 "rx"; 1395 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1396 pinctrl-names = "default"; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 1400 status = "disabled"; 1401 }; 1402 1403 i2c9: i2c@a84000 { 1404 compatible = "qcom,geni-i2c"; 1405 reg = <0x0 0x00a84000 0x0 0x4000>; 1406 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1407 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1408 clock-names = "se"; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1410 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1411 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1412 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1413 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1414 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1415 interconnect-names = "qup-core", 1416 "qup-config", 1417 "qup-memory"; 1418 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1419 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1420 dma-names = "tx", 1421 "rx"; 1422 pinctrl-0 = <&qup_i2c9_data_clk>; 1423 pinctrl-names = "default"; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 1427 status = "disabled"; 1428 }; 1429 1430 spi9: spi@a84000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0x0 0x00a84000 0x0 0x4000>; 1433 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1434 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1435 clock-names = "se"; 1436 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1437 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1438 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1439 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1440 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1441 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1442 interconnect-names = "qup-core", 1443 "qup-config", 1444 "qup-memory"; 1445 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1446 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1447 dma-names = "tx", 1448 "rx"; 1449 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1450 pinctrl-names = "default"; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 1454 status = "disabled"; 1455 }; 1456 1457 i2c10: i2c@a88000 { 1458 compatible = "qcom,geni-i2c"; 1459 reg = <0x0 0x00a88000 0x0 0x4000>; 1460 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1461 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1462 clock-names = "se"; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1464 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1465 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1466 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1467 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1468 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1469 interconnect-names = "qup-core", 1470 "qup-config", 1471 "qup-memory"; 1472 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1473 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1474 dma-names = "tx", 1475 "rx"; 1476 pinctrl-0 = <&qup_i2c10_data_clk>; 1477 pinctrl-names = "default"; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 1481 status = "disabled"; 1482 }; 1483 1484 spi10: spi@a88000 { 1485 compatible = "qcom,geni-spi"; 1486 reg = <0x0 0x00a88000 0x0 0x4000>; 1487 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1488 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1489 clock-names = "se"; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1491 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1492 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1493 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1494 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1495 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1496 interconnect-names = "qup-core", 1497 "qup-config", 1498 "qup-memory"; 1499 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1500 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1501 dma-names = "tx", 1502 "rx"; 1503 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1504 pinctrl-names = "default"; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 1508 status = "disabled"; 1509 }; 1510 1511 i2c11: i2c@a8c000 { 1512 compatible = "qcom,geni-i2c"; 1513 reg = <0x0 0x00a8c000 0x0 0x4000>; 1514 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1516 clock-names = "se"; 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1518 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1519 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1520 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1521 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1522 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1523 interconnect-names = "qup-core", 1524 "qup-config", 1525 "qup-memory"; 1526 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1527 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1528 dma-names = "tx", 1529 "rx"; 1530 pinctrl-0 = <&qup_i2c11_data_clk>; 1531 pinctrl-names = "default"; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 1535 status = "disabled"; 1536 }; 1537 1538 spi11: spi@a8c000 { 1539 compatible = "qcom,geni-spi"; 1540 reg = <0x0 0x00a8c000 0x0 0x4000>; 1541 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1542 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1543 clock-names = "se"; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1545 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1546 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1547 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1548 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1549 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1550 interconnect-names = "qup-core", 1551 "qup-config", 1552 "qup-memory"; 1553 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1554 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1555 dma-names = "tx", 1556 "rx"; 1557 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1558 pinctrl-names = "default"; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 status = "disabled"; 1563 }; 1564 1565 i2c12: i2c@a90000 { 1566 compatible = "qcom,geni-i2c"; 1567 reg = <0x0 0x00a90000 0x0 0x4000>; 1568 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1570 clock-names = "se"; 1571 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1572 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1573 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1574 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1575 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1576 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1577 interconnect-names = "qup-core", 1578 "qup-config", 1579 "qup-memory"; 1580 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1581 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1582 dma-names = "tx", 1583 "rx"; 1584 pinctrl-0 = <&qup_i2c12_data_clk>; 1585 pinctrl-names = "default"; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 1589 status = "disabled"; 1590 }; 1591 1592 spi12: spi@a90000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0x0 0x00a90000 0x0 0x4000>; 1595 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1597 clock-names = "se"; 1598 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1599 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1600 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1601 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1602 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1603 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1604 interconnect-names = "qup-core", 1605 "qup-config", 1606 "qup-memory"; 1607 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1608 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1609 dma-names = "tx", 1610 "rx"; 1611 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1612 pinctrl-names = "default"; 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 1616 status = "disabled"; 1617 }; 1618 1619 i2c13: i2c@a94000 { 1620 compatible = "qcom,geni-i2c"; 1621 reg = <0x0 0x00a94000 0x0 0x4000>; 1622 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1624 clock-names = "se"; 1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1626 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1627 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1628 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1629 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1630 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1631 interconnect-names = "qup-core", 1632 "qup-config", 1633 "qup-memory"; 1634 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1635 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1636 dma-names = "tx", 1637 "rx"; 1638 pinctrl-0 = <&qup_i2c13_data_clk>; 1639 pinctrl-names = "default"; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 1643 status = "disabled"; 1644 }; 1645 1646 spi13: spi@a94000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0x0 0x00a94000 0x0 0x4000>; 1649 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1651 clock-names = "se"; 1652 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1653 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1654 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1655 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1656 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1657 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1658 interconnect-names = "qup-core", 1659 "qup-config", 1660 "qup-memory"; 1661 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1662 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1663 dma-names = "tx", 1664 "rx"; 1665 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1666 pinctrl-names = "default"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 1670 status = "disabled"; 1671 }; 1672 1673 i2c14: i2c@a98000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0x0 0x00a98000 0x0 0x4000>; 1676 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1678 clock-names = "se"; 1679 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1680 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1681 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1682 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1683 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1684 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1685 interconnect-names = "qup-core", 1686 "qup-config", 1687 "qup-memory"; 1688 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1689 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1690 dma-names = "tx", 1691 "rx"; 1692 pinctrl-0 = <&qup_i2c14_data_clk>; 1693 pinctrl-names = "default"; 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 1697 status = "disabled"; 1698 }; 1699 1700 spi14: spi@a98000 { 1701 compatible = "qcom,geni-spi"; 1702 reg = <0x0 0x00a98000 0x0 0x4000>; 1703 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1704 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1705 clock-names = "se"; 1706 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1707 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1708 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1709 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1710 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1711 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1712 interconnect-names = "qup-core", 1713 "qup-config", 1714 "qup-memory"; 1715 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1716 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1717 dma-names = "tx", 1718 "rx"; 1719 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1720 pinctrl-names = "default"; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 status = "disabled"; 1725 }; 1726 1727 uart14: serial@a98000 { 1728 compatible = "qcom,geni-uart"; 1729 reg = <0x0 0x00a98000 0x0 0x4000>; 1730 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1732 clock-names = "se"; 1733 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1734 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1735 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1736 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1737 interconnect-names = "qup-core", 1738 "qup-config"; 1739 pinctrl-0 = <&qup_uart14_default>; 1740 pinctrl-names = "default"; 1741 1742 status = "disabled"; 1743 }; 1744 1745 i2c15: i2c@a9c000 { 1746 compatible = "qcom,geni-i2c"; 1747 reg = <0x0 0x00a9c000 0x0 0x4000>; 1748 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1749 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1750 clock-names = "se"; 1751 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1752 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1753 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1754 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1755 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1756 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1757 interconnect-names = "qup-core", 1758 "qup-config", 1759 "qup-memory"; 1760 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1761 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1762 dma-names = "tx", 1763 "rx"; 1764 pinctrl-0 = <&qup_i2c15_data_clk>; 1765 pinctrl-names = "default"; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 1769 status = "disabled"; 1770 }; 1771 1772 spi15: spi@a9c000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0x0 0x00a9c000 0x0 0x4000>; 1775 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1776 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1777 clock-names = "se"; 1778 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1779 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1780 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1781 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1782 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1783 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1784 interconnect-names = "qup-core", 1785 "qup-config", 1786 "qup-memory"; 1787 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1788 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1789 dma-names = "tx", 1790 "rx"; 1791 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1792 pinctrl-names = "default"; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 1796 status = "disabled"; 1797 }; 1798 }; 1799 1800 gpi_dma0: dma-controller@b00000 { 1801 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1802 reg = <0x0 0x00b00000 0x0 0x60000>; 1803 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1819 dma-channels = <16>; 1820 dma-channel-mask = <0x3f>; 1821 #dma-cells = <3>; 1822 iommus = <&apps_smmu 0xd36 0x0>; 1823 }; 1824 1825 qupv3_0: geniqup@bc0000 { 1826 compatible = "qcom,geni-se-qup"; 1827 reg = <0x0 0x00bc0000 0x0 0x3000>; 1828 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1829 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1830 clock-names = "m-ahb", 1831 "s-ahb"; 1832 iommus = <&apps_smmu 0xd23 0x0>; 1833 #address-cells = <2>; 1834 #size-cells = <2>; 1835 ranges; 1836 1837 i2c0: i2c@b80000 { 1838 compatible = "qcom,geni-i2c"; 1839 reg = <0x0 0x00b80000 0x0 0x4000>; 1840 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1842 clock-names = "se"; 1843 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1844 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1845 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1846 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1847 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1848 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1849 interconnect-names = "qup-core", 1850 "qup-config", 1851 "qup-memory"; 1852 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1853 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1854 dma-names = "tx", 1855 "rx"; 1856 pinctrl-0 = <&qup_i2c0_data_clk>; 1857 pinctrl-names = "default"; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 1861 status = "disabled"; 1862 }; 1863 1864 spi0: spi@b80000 { 1865 compatible = "qcom,geni-spi"; 1866 reg = <0x0 0x00b80000 0x0 0x4000>; 1867 interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>; 1868 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1869 clock-names = "se"; 1870 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1871 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1872 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1873 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1874 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1875 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1876 interconnect-names = "qup-core", 1877 "qup-config", 1878 "qup-memory"; 1879 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1880 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1881 dma-names = "tx", 1882 "rx"; 1883 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1884 pinctrl-names = "default"; 1885 #address-cells = <1>; 1886 #size-cells = <0>; 1887 1888 status = "disabled"; 1889 }; 1890 1891 i2c1: i2c@b84000 { 1892 compatible = "qcom,geni-i2c"; 1893 reg = <0x0 0x00b84000 0x0 0x4000>; 1894 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1895 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1896 clock-names = "se"; 1897 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1898 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1899 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1900 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1901 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1903 interconnect-names = "qup-core", 1904 "qup-config", 1905 "qup-memory"; 1906 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1907 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1908 dma-names = "tx", 1909 "rx"; 1910 pinctrl-0 = <&qup_i2c1_data_clk>; 1911 pinctrl-names = "default"; 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 1915 status = "disabled"; 1916 }; 1917 1918 spi1: spi@b84000 { 1919 compatible = "qcom,geni-spi"; 1920 reg = <0x0 0x00b84000 0x0 0x4000>; 1921 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1922 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1923 clock-names = "se"; 1924 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1925 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1926 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1927 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1928 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1930 interconnect-names = "qup-core", 1931 "qup-config", 1932 "qup-memory"; 1933 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1934 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1935 dma-names = "tx", 1936 "rx"; 1937 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1938 pinctrl-names = "default"; 1939 #address-cells = <1>; 1940 #size-cells = <0>; 1941 1942 status = "disabled"; 1943 }; 1944 1945 i2c2: i2c@b88000 { 1946 compatible = "qcom,geni-i2c"; 1947 reg = <0x0 0x00b88000 0x0 0x4000>; 1948 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1949 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1950 clock-names = "se"; 1951 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1952 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1953 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1954 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1955 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1956 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1957 interconnect-names = "qup-core", 1958 "qup-config", 1959 "qup-memory"; 1960 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1961 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1962 dma-names = "tx", 1963 "rx"; 1964 pinctrl-0 = <&qup_i2c2_data_clk>; 1965 pinctrl-names = "default"; 1966 #address-cells = <1>; 1967 #size-cells = <0>; 1968 1969 status = "disabled"; 1970 }; 1971 1972 spi2: spi@b88000 { 1973 compatible = "qcom,geni-spi"; 1974 reg = <0x0 0x00b88000 0x0 0x4000>; 1975 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1976 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1977 clock-names = "se"; 1978 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1979 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1980 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1981 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1982 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1983 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1984 interconnect-names = "qup-core", 1985 "qup-config", 1986 "qup-memory"; 1987 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1988 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1989 dma-names = "tx", 1990 "rx"; 1991 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1992 pinctrl-names = "default"; 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 1996 status = "disabled"; 1997 }; 1998 1999 uart2: serial@b88000 { 2000 compatible = "qcom,geni-uart"; 2001 reg = <0x0 0x00b88000 0x0 0x4000>; 2002 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 2003 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2004 clock-names = "se"; 2005 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2006 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2007 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2008 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2009 interconnect-names = "qup-core", 2010 "qup-config"; 2011 pinctrl-0 = <&qup_uart2_default>; 2012 pinctrl-names = "default"; 2013 2014 status = "disabled"; 2015 }; 2016 2017 i2c3: i2c@b8c000 { 2018 compatible = "qcom,geni-i2c"; 2019 reg = <0x0 0x00b8c000 0x0 0x4000>; 2020 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2021 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2022 clock-names = "se"; 2023 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2024 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2025 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2026 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2027 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2029 interconnect-names = "qup-core", 2030 "qup-config", 2031 "qup-memory"; 2032 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2033 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2034 dma-names = "tx", 2035 "rx"; 2036 pinctrl-0 = <&qup_i2c3_data_clk>; 2037 pinctrl-names = "default"; 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 2041 status = "disabled"; 2042 }; 2043 2044 spi3: spi@b8c000 { 2045 compatible = "qcom,geni-spi"; 2046 reg = <0x0 0x00b8c000 0x0 0x4000>; 2047 interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>; 2048 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2049 clock-names = "se"; 2050 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2051 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2052 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2053 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2054 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2055 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2056 interconnect-names = "qup-core", 2057 "qup-config", 2058 "qup-memory"; 2059 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2060 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2061 dma-names = "tx", 2062 "rx"; 2063 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2064 pinctrl-names = "default"; 2065 #address-cells = <1>; 2066 #size-cells = <0>; 2067 2068 status = "disabled"; 2069 }; 2070 2071 i2c4: i2c@b90000 { 2072 compatible = "qcom,geni-i2c"; 2073 reg = <0x0 0x00b90000 0x0 0x4000>; 2074 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2075 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2076 clock-names = "se"; 2077 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2078 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2079 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2080 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2081 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2082 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2083 interconnect-names = "qup-core", 2084 "qup-config", 2085 "qup-memory"; 2086 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2087 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2088 dma-names = "tx", 2089 "rx"; 2090 pinctrl-0 = <&qup_i2c4_data_clk>; 2091 pinctrl-names = "default"; 2092 #address-cells = <1>; 2093 #size-cells = <0>; 2094 2095 status = "disabled"; 2096 }; 2097 2098 spi4: spi@b90000 { 2099 compatible = "qcom,geni-spi"; 2100 reg = <0x0 0x00b90000 0x0 0x4000>; 2101 interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>; 2102 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2103 clock-names = "se"; 2104 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2105 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2106 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2107 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2108 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2109 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2110 interconnect-names = "qup-core", 2111 "qup-config", 2112 "qup-memory"; 2113 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2114 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2115 dma-names = "tx", 2116 "rx"; 2117 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2118 pinctrl-names = "default"; 2119 #address-cells = <1>; 2120 #size-cells = <0>; 2121 2122 status = "disabled"; 2123 }; 2124 2125 i2c5: i2c@b94000 { 2126 compatible = "qcom,geni-i2c"; 2127 reg = <0x0 0x00b94000 0x0 0x4000>; 2128 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2129 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2130 clock-names = "se"; 2131 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2132 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2133 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2134 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2135 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2137 interconnect-names = "qup-core", 2138 "qup-config", 2139 "qup-memory"; 2140 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2141 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2142 dma-names = "tx", 2143 "rx"; 2144 pinctrl-0 = <&qup_i2c5_data_clk>; 2145 pinctrl-names = "default"; 2146 #address-cells = <1>; 2147 #size-cells = <0>; 2148 2149 status = "disabled"; 2150 }; 2151 2152 spi5: spi@b94000 { 2153 compatible = "qcom,geni-spi"; 2154 reg = <0x0 0x00b94000 0x0 0x4000>; 2155 interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>; 2156 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2157 clock-names = "se"; 2158 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2159 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2160 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2161 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2162 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2163 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2164 interconnect-names = "qup-core", 2165 "qup-config", 2166 "qup-memory"; 2167 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2168 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2169 dma-names = "tx", 2170 "rx"; 2171 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2172 pinctrl-names = "default"; 2173 #address-cells = <1>; 2174 #size-cells = <0>; 2175 2176 status = "disabled"; 2177 }; 2178 2179 i2c6: i2c@b98000 { 2180 compatible = "qcom,geni-i2c"; 2181 reg = <0x0 0x00b98000 0x0 0x4000>; 2182 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2183 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2184 clock-names = "se"; 2185 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2186 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2187 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2188 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2189 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2190 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2191 interconnect-names = "qup-core", 2192 "qup-config", 2193 "qup-memory"; 2194 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2195 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2196 dma-names = "tx", 2197 "rx"; 2198 pinctrl-0 = <&qup_i2c6_data_clk>; 2199 pinctrl-names = "default"; 2200 #address-cells = <1>; 2201 #size-cells = <0>; 2202 2203 status = "disabled"; 2204 }; 2205 2206 spi6: spi@b98000 { 2207 compatible = "qcom,geni-spi"; 2208 reg = <0x0 0x00b98000 0x0 0x4000>; 2209 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2210 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2211 clock-names = "se"; 2212 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2213 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2214 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2215 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2216 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2217 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2218 interconnect-names = "qup-core", 2219 "qup-config", 2220 "qup-memory"; 2221 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2222 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2223 dma-names = "tx", 2224 "rx"; 2225 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2226 pinctrl-names = "default"; 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 2230 status = "disabled"; 2231 }; 2232 2233 i2c7: i2c@b9c000 { 2234 compatible = "qcom,geni-i2c"; 2235 reg = <0x0 0x00b9c000 0x0 0x4000>; 2236 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2237 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2238 clock-names = "se"; 2239 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2240 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2241 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2242 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2243 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2244 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2245 interconnect-names = "qup-core", 2246 "qup-config", 2247 "qup-memory"; 2248 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2249 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2250 dma-names = "tx", 2251 "rx"; 2252 pinctrl-0 = <&qup_i2c7_data_clk>; 2253 pinctrl-names = "default"; 2254 #address-cells = <1>; 2255 #size-cells = <0>; 2256 2257 status = "disabled"; 2258 }; 2259 2260 spi7: spi@b9c000 { 2261 compatible = "qcom,geni-spi"; 2262 reg = <0x0 0x00b9c000 0x0 0x4000>; 2263 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2264 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2265 clock-names = "se"; 2266 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2267 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2268 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2269 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2270 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2271 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2272 interconnect-names = "qup-core", 2273 "qup-config", 2274 "qup-memory"; 2275 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2276 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2277 dma-names = "tx", 2278 "rx"; 2279 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2280 pinctrl-names = "default"; 2281 #address-cells = <1>; 2282 #size-cells = <0>; 2283 2284 status = "disabled"; 2285 }; 2286 }; 2287 2288 usb_hs_phy: phy@fa0000 { 2289 compatible = "qcom,glymur-m31-eusb2-phy", 2290 "qcom,sm8750-m31-eusb2-phy"; 2291 reg = <0x0 0x00fa0000 0x0 0x154>; 2292 #phy-cells = <0>; 2293 2294 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2295 clock-names = "ref"; 2296 2297 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2298 2299 status = "disabled"; 2300 }; 2301 2302 usb_mp_hsphy0: phy@fa1000 { 2303 compatible = "qcom,glymur-m31-eusb2-phy", 2304 "qcom,sm8750-m31-eusb2-phy"; 2305 2306 reg = <0x0 0x00fa1000 0x0 0x29c>; 2307 #phy-cells = <0>; 2308 2309 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2310 clock-names = "ref"; 2311 2312 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2313 2314 status = "disabled"; 2315 }; 2316 2317 usb_mp_hsphy1: phy@fa2000 { 2318 compatible = "qcom,glymur-m31-eusb2-phy", 2319 "qcom,sm8750-m31-eusb2-phy"; 2320 2321 reg = <0x0 0x00fa2000 0x0 0x29c>; 2322 #phy-cells = <0>; 2323 2324 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2325 clock-names = "ref"; 2326 2327 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2328 2329 status = "disabled"; 2330 }; 2331 2332 usb_mp_qmpphy0: phy@fa3000 { 2333 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2334 reg = <0x0 0x00fa3000 0x0 0x2000>; 2335 2336 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2337 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2338 <&rpmhcc RPMH_CXO_CLK>, 2339 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2340 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2341 clock-names = "aux", 2342 "clkref", 2343 "ref", 2344 "com_aux", 2345 "pipe"; 2346 2347 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2348 2349 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2350 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2351 reset-names = "phy", 2352 "phy_phy"; 2353 2354 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2355 #clock-cells = <0>; 2356 #phy-cells = <0>; 2357 2358 status = "disabled"; 2359 }; 2360 2361 usb_mp_qmpphy1: phy@fa5000 { 2362 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2363 reg = <0x0 0x00fa5000 0x0 0x2000>; 2364 2365 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2366 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2367 <&rpmhcc RPMH_CXO_CLK>, 2368 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2369 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2370 clock-names = "aux", 2371 "clkref", 2372 "ref", 2373 "com_aux", 2374 "pipe"; 2375 2376 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2377 2378 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2379 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2380 reset-names = "phy", 2381 "phy_phy"; 2382 2383 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2384 2385 #clock-cells = <0>; 2386 #phy-cells = <0>; 2387 2388 status = "disabled"; 2389 }; 2390 2391 mdss_dp3_phy: phy@faac00 { 2392 compatible = "qcom,glymur-dp-phy"; 2393 reg = <0x0 0x00faac00 0x0 0x1d0>, 2394 <0x0 0x00faa400 0x0 0x128>, 2395 <0x0 0x00faa800 0x0 0x128>, 2396 <0x0 0x00faa000 0x0 0x358>; 2397 2398 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 2399 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2400 <&tcsr TCSR_EDP_CLKREF_EN>; 2401 clock-names = "aux", 2402 "cfg_ahb", 2403 "ref"; 2404 2405 power-domains = <&rpmhpd RPMHPD_MX>; 2406 2407 #clock-cells = <1>; 2408 #phy-cells = <0>; 2409 2410 status = "disabled"; 2411 }; 2412 2413 usb_0_hsphy: phy@fd3000 { 2414 compatible = "qcom,glymur-m31-eusb2-phy", 2415 "qcom,sm8750-m31-eusb2-phy"; 2416 2417 reg = <0x0 0x00fd3000 0x0 0x29c>; 2418 #phy-cells = <0>; 2419 2420 clocks = <&rpmhcc RPMH_CXO_CLK>; 2421 clock-names = "ref"; 2422 2423 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2424 2425 status = "disabled"; 2426 }; 2427 2428 usb_0_qmpphy: phy@fd5000 { 2429 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2430 reg = <0x0 0x00fd5000 0x0 0x8000>; 2431 2432 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2433 <&rpmhcc RPMH_CXO_CLK>, 2434 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2435 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2436 clock-names = "aux", 2437 "ref", 2438 "com_aux", 2439 "usb3_pipe"; 2440 2441 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2442 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2443 2444 reset-names = "phy", 2445 "common"; 2446 2447 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2448 2449 #clock-cells = <1>; 2450 #phy-cells = <1>; 2451 2452 mode-switch; 2453 orientation-switch; 2454 2455 status = "disabled"; 2456 2457 ports { 2458 #address-cells = <1>; 2459 #size-cells = <0>; 2460 2461 port@0 { 2462 reg = <0>; 2463 2464 usb_0_qmpphy_out: endpoint { 2465 }; 2466 }; 2467 2468 port@1 { 2469 reg = <1>; 2470 2471 usb_0_qmpphy_usb_ss_in: endpoint { 2472 remote-endpoint = <&usb_0_dwc3_ss>; 2473 }; 2474 }; 2475 2476 port@2 { 2477 reg = <2>; 2478 2479 usb_dp_qmpphy_dp_in: endpoint { 2480 remote-endpoint = <&mdss_dp0_out>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 usb_1_hsphy: phy@fdd000 { 2487 compatible = "qcom,glymur-m31-eusb2-phy", 2488 "qcom,sm8750-m31-eusb2-phy"; 2489 2490 reg = <0x0 0x00fdd000 0x0 0x29c>; 2491 #phy-cells = <0>; 2492 2493 clocks = <&rpmhcc RPMH_CXO_CLK>; 2494 clock-names = "ref"; 2495 2496 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2497 2498 status = "disabled"; 2499 }; 2500 2501 usb_1_qmpphy: phy@fde000 { 2502 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2503 reg = <0x0 0x00fde000 0x0 0x8000>; 2504 2505 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2506 <&rpmhcc RPMH_CXO_CLK>, 2507 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2508 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, 2509 <&tcsr TCSR_USB4_1_CLKREF_EN>; 2510 clock-names = "aux", 2511 "ref", 2512 "com_aux", 2513 "usb3_pipe", 2514 "clkref"; 2515 2516 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2517 2518 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2519 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2520 reset-names = "phy", 2521 "common"; 2522 2523 #clock-cells = <1>; 2524 #phy-cells = <1>; 2525 2526 mode-switch; 2527 orientation-switch; 2528 2529 status = "disabled"; 2530 2531 ports { 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 2535 port@0 { 2536 reg = <0>; 2537 2538 usb_1_qmpphy_out: endpoint { 2539 }; 2540 }; 2541 2542 port@1 { 2543 reg = <1>; 2544 2545 usb_1_qmpphy_usb_ss_in: endpoint { 2546 remote-endpoint = <&usb_1_dwc3_ss>; 2547 }; 2548 }; 2549 2550 port@2 { 2551 reg = <2>; 2552 2553 usb_1_qmpphy_dp_in: endpoint { 2554 remote-endpoint = <&mdss_dp1_out>; 2555 }; 2556 }; 2557 }; 2558 }; 2559 2560 2561 /* cluster0 */ 2562 bwmon_cluster0: pmu@100c400 { 2563 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2564 reg = <0x0 0x0100c400 0x0 0x600>; 2565 2566 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2567 2568 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2569 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2570 2571 operating-points-v2 = <&cpu_bwmon_opp_table>; 2572 2573 cpu_bwmon_opp_table: opp-table { 2574 compatible = "operating-points-v2"; 2575 2576 opp-0 { 2577 opp-peak-kBps = <800000>; 2578 }; 2579 2580 opp-1 { 2581 opp-peak-kBps = <2188800>; 2582 }; 2583 2584 opp-2 { 2585 opp-peak-kBps = <5414400>; 2586 }; 2587 2588 opp-3 { 2589 opp-peak-kBps = <6220800>; 2590 }; 2591 2592 opp-4 { 2593 opp-peak-kBps = <6835200>; 2594 }; 2595 2596 opp-5 { 2597 opp-peak-kBps = <8371200>; 2598 }; 2599 2600 opp-6 { 2601 opp-peak-kBps = <10944000>; 2602 }; 2603 2604 opp-7 { 2605 opp-peak-kBps = <12748800>; 2606 }; 2607 2608 opp-8 { 2609 opp-peak-kBps = <14745600>; 2610 }; 2611 2612 opp-9 { 2613 opp-peak-kBps = <16896000>; 2614 }; 2615 2616 opp-10 { 2617 opp-peak-kBps = <19046400>; 2618 }; 2619 2620 opp-11 { 2621 opp-peak-kBps = <21332000>; 2622 }; 2623 }; 2624 }; 2625 2626 /* cluster1 */ 2627 bwmon_cluster1: pmu@100d400 { 2628 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2629 reg = <0x0 0x0100d400 0x0 0x600>; 2630 2631 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2632 2633 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2634 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2635 2636 operating-points-v2 = <&cpu_bwmon_opp_table>; 2637 }; 2638 2639 /* cluster2 */ 2640 bwmon_cluster2: pmu@100e400 { 2641 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2642 reg = <0x0 0x0100e400 0x0 0x600>; 2643 2644 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2645 2646 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2647 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2648 2649 operating-points-v2 = <&cpu_bwmon_opp_table>; 2650 }; 2651 cnoc_main: interconnect@1500000 { 2652 compatible = "qcom,glymur-cnoc-main"; 2653 reg = <0x0 0x01500000 0x0 0x17080>; 2654 qcom,bcm-voters = <&apps_bcm_voter>; 2655 #interconnect-cells = <2>; 2656 }; 2657 2658 config_noc: interconnect@1600000 { 2659 compatible = "qcom,glymur-cnoc-cfg"; 2660 reg = <0x0 0x01600000 0x0 0x6600>; 2661 qcom,bcm-voters = <&apps_bcm_voter>; 2662 #interconnect-cells = <2>; 2663 }; 2664 2665 system_noc: interconnect@1680000 { 2666 compatible = "qcom,glymur-system-noc"; 2667 reg = <0x0 0x01680000 0x0 0x1c080>; 2668 qcom,bcm-voters = <&apps_bcm_voter>; 2669 #interconnect-cells = <2>; 2670 }; 2671 2672 pcie_west_anoc: interconnect@16c0000 { 2673 compatible = "qcom,glymur-pcie-west-anoc"; 2674 reg = <0x0 0x016c0000 0x0 0xf580>; 2675 qcom,bcm-voters = <&apps_bcm_voter>; 2676 #interconnect-cells = <2>; 2677 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2678 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2679 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2680 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2681 }; 2682 2683 pcie_east_anoc: interconnect@16d0000 { 2684 compatible = "qcom,glymur-pcie-east-anoc"; 2685 reg = <0x0 0x016d0000 0x0 0xf300>; 2686 qcom,bcm-voters = <&apps_bcm_voter>; 2687 #interconnect-cells = <2>; 2688 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2689 }; 2690 2691 aggre1_noc: interconnect@16e0000 { 2692 compatible = "qcom,glymur-aggre1-noc"; 2693 reg = <0x0 0x016e0000 0x0 0x14400>; 2694 qcom,bcm-voters = <&apps_bcm_voter>; 2695 #interconnect-cells = <2>; 2696 }; 2697 2698 aggre2_noc: interconnect@1720000 { 2699 compatible = "qcom,glymur-aggre2-noc"; 2700 reg = <0x0 0x01720000 0x0 0x14400>; 2701 qcom,bcm-voters = <&apps_bcm_voter>; 2702 #interconnect-cells = <2>; 2703 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2704 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2705 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2706 }; 2707 2708 aggre3_noc: interconnect@1700000 { 2709 compatible = "qcom,glymur-aggre3-noc"; 2710 reg = <0x0 0x01700000 0x0 0x1d400>; 2711 qcom,bcm-voters = <&apps_bcm_voter>; 2712 #interconnect-cells = <2>; 2713 }; 2714 2715 aggre4_noc: interconnect@1740000 { 2716 compatible = "qcom,glymur-aggre4-noc"; 2717 reg = <0x0 0x01740000 0x0 0x14400>; 2718 qcom,bcm-voters = <&apps_bcm_voter>; 2719 #interconnect-cells = <2>; 2720 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2721 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2722 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2723 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2724 }; 2725 2726 mmss_noc: interconnect@1780000 { 2727 compatible = "qcom,glymur-mmss-noc"; 2728 reg = <0x0 0x01780000 0x0 0x5b800>; 2729 qcom,bcm-voters = <&apps_bcm_voter>; 2730 #interconnect-cells = <2>; 2731 }; 2732 2733 pcie_east_slv_noc: interconnect@1900000 { 2734 compatible = "qcom,glymur-pcie-east-slv-noc"; 2735 reg = <0x0 0x01900000 0x0 0xe080>; 2736 qcom,bcm-voters = <&apps_bcm_voter>; 2737 #interconnect-cells = <2>; 2738 }; 2739 2740 pcie_west_slv_noc: interconnect@1920000 { 2741 compatible = "qcom,glymur-pcie-west-slv-noc"; 2742 reg = <0x0 0x01920000 0x0 0xf180>; 2743 qcom,bcm-voters = <&apps_bcm_voter>; 2744 #interconnect-cells = <2>; 2745 }; 2746 2747 pcie4: pci@1bf0000 { 2748 device_type = "pci"; 2749 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2750 reg = <0x0 0x01bf0000 0x0 0x3000>, 2751 <0x0 0x78000000 0x0 0xf20>, 2752 <0x0 0x78000f40 0x0 0xa8>, 2753 <0x0 0x78001000 0x0 0x4000>, 2754 <0x0 0x78005000 0x0 0x100000>, 2755 <0x0 0x01bf3000 0x0 0x1000>; 2756 reg-names = "parf", 2757 "dbi", 2758 "elbi", 2759 "atu", 2760 "config", 2761 "mhi"; 2762 #address-cells = <3>; 2763 #size-cells = <2>; 2764 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2765 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2766 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2767 bus-range = <0x00 0xff>; 2768 2769 dma-coherent; 2770 2771 linux,pci-domain = <4>; 2772 num-lanes = <2>; 2773 2774 operating-points-v2 = <&pcie4_opp_table>; 2775 2776 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2777 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2778 2779 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2788 interrupt-names = "msi0", 2789 "msi1", 2790 "msi2", 2791 "msi3", 2792 "msi4", 2793 "msi5", 2794 "msi6", 2795 "msi7", 2796 "global"; 2797 2798 #interrupt-cells = <1>; 2799 interrupt-map-mask = <0 0 0 0x7>; 2800 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 2801 <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 2802 <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 2803 <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; 2804 2805 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2806 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2807 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2808 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2809 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2810 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2811 clock-names = "aux", 2812 "cfg", 2813 "bus_master", 2814 "bus_slave", 2815 "slave_q2a", 2816 "noc_aggr"; 2817 2818 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2819 assigned-clock-rates = <19200000>; 2820 2821 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2822 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2823 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2824 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2825 interconnect-names = "pcie-mem", 2826 "cpu-pcie"; 2827 2828 resets = <&gcc GCC_PCIE_4_BCR>, 2829 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2830 reset-names = "pci", 2831 "link_down"; 2832 2833 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2834 2835 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2836 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2837 2838 status = "disabled"; 2839 2840 pcie4_opp_table: opp-table { 2841 compatible = "operating-points-v2"; 2842 2843 /* GEN 1 x1 */ 2844 opp-2500000-1 { 2845 opp-hz = /bits/ 64 <2500000>; 2846 required-opps = <&rpmhpd_opp_low_svs>; 2847 opp-peak-kBps = <250000 1>; 2848 opp-level = <1>; 2849 }; 2850 2851 /* GEN 1 x2 */ 2852 opp-5000000-1 { 2853 opp-hz = /bits/ 64 <5000000>; 2854 required-opps = <&rpmhpd_opp_low_svs>; 2855 opp-peak-kBps = <500000 1>; 2856 opp-level = <1>; 2857 }; 2858 2859 /* GEN 2 x1 */ 2860 opp-5000000-2 { 2861 opp-hz = /bits/ 64 <5000000>; 2862 required-opps = <&rpmhpd_opp_low_svs>; 2863 opp-peak-kBps = <500000 1>; 2864 opp-level = <2>; 2865 }; 2866 2867 /* GEN 2 x2 */ 2868 opp-10000000-2 { 2869 opp-hz = /bits/ 64 <10000000>; 2870 required-opps = <&rpmhpd_opp_low_svs>; 2871 opp-peak-kBps = <1000000 1>; 2872 opp-level = <2>; 2873 }; 2874 2875 /* GEN 3 x1 */ 2876 opp-8000000-3 { 2877 opp-hz = /bits/ 64 <8000000>; 2878 required-opps = <&rpmhpd_opp_low_svs>; 2879 opp-peak-kBps = <984500 1>; 2880 opp-level = <3>; 2881 }; 2882 2883 /* GEN 3 x2 */ 2884 opp-16000000-3 { 2885 opp-hz = /bits/ 64 <16000000>; 2886 required-opps = <&rpmhpd_opp_low_svs>; 2887 opp-peak-kBps = <1969000 1>; 2888 opp-level = <3>; 2889 }; 2890 2891 /* GEN 4 x1 */ 2892 opp-16000000-4 { 2893 opp-hz = /bits/ 64 <16000000>; 2894 required-opps = <&rpmhpd_opp_low_svs>; 2895 opp-peak-kBps = <1969000 1>; 2896 opp-level = <4>; 2897 }; 2898 2899 /* GEN 4 x2 */ 2900 opp-32000000-4 { 2901 opp-hz = /bits/ 64 <32000000>; 2902 required-opps = <&rpmhpd_opp_low_svs>; 2903 opp-peak-kBps = <3938000 1>; 2904 opp-level = <4>; 2905 }; 2906 2907 }; 2908 2909 pcie4_port0: pcie@0 { 2910 device_type = "pci"; 2911 reg = <0x0 0x0 0x0 0x0 0x0>; 2912 bus-range = <0x01 0xff>; 2913 2914 phys = <&pcie4_phy>; 2915 2916 #address-cells = <3>; 2917 #size-cells = <2>; 2918 ranges; 2919 }; 2920 }; 2921 2922 pcie4_phy: phy@1bf6000 { 2923 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 2924 reg = <0x0 0x01bf6000 0x0 0x2000>; 2925 2926 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 2927 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2928 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 2929 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2930 <&gcc GCC_PCIE_4_PIPE_CLK>, 2931 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 2932 clock-names = "aux", 2933 "cfg_ahb", 2934 "ref", 2935 "rchng", 2936 "pipe", 2937 "pipediv2"; 2938 2939 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 2940 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 2941 reset-names = "phy", 2942 "phy_nocsr"; 2943 2944 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2945 assigned-clock-rates = <100000000>; 2946 2947 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2948 2949 #clock-cells = <0>; 2950 clock-output-names = "pcie4_pipe_clk"; 2951 2952 #phy-cells = <0>; 2953 2954 status = "disabled"; 2955 }; 2956 2957 pcie5: pci@1b40000 { 2958 device_type = "pci"; 2959 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2960 reg = <0x0 0x01b40000 0x0 0x3000>, 2961 <0x0 0x7a000000 0x0 0xf20>, 2962 <0x0 0x7a000f40 0x0 0xa8>, 2963 <0x0 0x7a001000 0x0 0x4000>, 2964 <0x0 0x7a100000 0x0 0x100000>, 2965 <0x0 0x01b43000 0x0 0x1000>; 2966 reg-names = "parf", 2967 "dbi", 2968 "elbi", 2969 "atu", 2970 "config", 2971 "mhi"; 2972 #address-cells = <3>; 2973 #size-cells = <2>; 2974 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 2975 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 2976 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 2977 bus-range = <0x00 0xff>; 2978 2979 dma-coherent; 2980 2981 linux,pci-domain = <5>; 2982 num-lanes = <4>; 2983 2984 operating-points-v2 = <&pcie5_opp_table>; 2985 2986 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 2987 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 2988 2989 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2991 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 2992 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 2993 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 2994 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2995 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2996 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 2997 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 2998 interrupt-names = "msi0", 2999 "msi1", 3000 "msi2", 3001 "msi3", 3002 "msi4", 3003 "msi5", 3004 "msi6", 3005 "msi7", 3006 "global"; 3007 3008 #interrupt-cells = <1>; 3009 interrupt-map-mask = <0 0 0 0x7>; 3010 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 3011 <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 3012 <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 3013 <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; 3014 3015 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3016 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3017 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3018 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3019 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3020 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 3021 clock-names = "aux", 3022 "cfg", 3023 "bus_master", 3024 "bus_slave", 3025 "slave_q2a", 3026 "noc_aggr"; 3027 3028 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3029 assigned-clock-rates = <19200000>; 3030 3031 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3032 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3033 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3034 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3035 interconnect-names = "pcie-mem", 3036 "cpu-pcie"; 3037 3038 resets = <&gcc GCC_PCIE_5_BCR>, 3039 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3040 reset-names = "pci", 3041 "link_down"; 3042 3043 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3044 3045 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3046 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3047 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3048 3049 status = "disabled"; 3050 3051 pcie5_opp_table: opp-table { 3052 compatible = "operating-points-v2"; 3053 3054 /* GEN 1 x1 */ 3055 opp-2500000-1 { 3056 opp-hz = /bits/ 64 <2500000>; 3057 required-opps = <&rpmhpd_opp_low_svs>; 3058 opp-peak-kBps = <250000 1>; 3059 opp-level = <1>; 3060 }; 3061 3062 /* GEN 1 x2 */ 3063 opp-5000000-1 { 3064 opp-hz = /bits/ 64 <5000000>; 3065 required-opps = <&rpmhpd_opp_low_svs>; 3066 opp-peak-kBps = <500000 1>; 3067 opp-level = <1>; 3068 }; 3069 3070 /* GEN 1 x4 */ 3071 opp-10000000-1 { 3072 opp-hz = /bits/ 64 <10000000>; 3073 required-opps = <&rpmhpd_opp_low_svs>; 3074 opp-peak-kBps = <1000000 1>; 3075 opp-level = <1>; 3076 }; 3077 3078 /* GEN 2 x1 */ 3079 opp-5000000-2 { 3080 opp-hz = /bits/ 64 <5000000>; 3081 required-opps = <&rpmhpd_opp_low_svs>; 3082 opp-peak-kBps = <500000 1>; 3083 opp-level = <2>; 3084 }; 3085 3086 /* GEN 2 x2 */ 3087 opp-10000000-2 { 3088 opp-hz = /bits/ 64 <10000000>; 3089 required-opps = <&rpmhpd_opp_low_svs>; 3090 opp-peak-kBps = <1000000 1>; 3091 opp-level = <2>; 3092 }; 3093 3094 /* GEN 2 x4 */ 3095 opp-20000000-2 { 3096 opp-hz = /bits/ 64 <20000000>; 3097 required-opps = <&rpmhpd_opp_low_svs>; 3098 opp-peak-kBps = <2000000 1>; 3099 opp-level = <2>; 3100 }; 3101 3102 /* GEN 3 x1 */ 3103 opp-8000000-3 { 3104 opp-hz = /bits/ 64 <8000000>; 3105 required-opps = <&rpmhpd_opp_low_svs>; 3106 opp-peak-kBps = <984500 1>; 3107 opp-level = <3>; 3108 }; 3109 3110 /* GEN 3 x2 */ 3111 opp-16000000-3 { 3112 opp-hz = /bits/ 64 <16000000>; 3113 required-opps = <&rpmhpd_opp_low_svs>; 3114 opp-peak-kBps = <1969000 1>; 3115 opp-level = <3>; 3116 }; 3117 3118 /* GEN 3 x4 */ 3119 opp-32000000-3 { 3120 opp-hz = /bits/ 64 <32000000>; 3121 required-opps = <&rpmhpd_opp_low_svs>; 3122 opp-peak-kBps = <3938000 1>; 3123 opp-level = <3>; 3124 }; 3125 3126 /* GEN 4 x1 */ 3127 opp-16000000-4 { 3128 opp-hz = /bits/ 64 <16000000>; 3129 required-opps = <&rpmhpd_opp_svs>; 3130 opp-peak-kBps = <1969000 1>; 3131 opp-level = <4>; 3132 }; 3133 3134 /* GEN 4 x2 */ 3135 opp-32000000-4 { 3136 opp-hz = /bits/ 64 <32000000>; 3137 required-opps = <&rpmhpd_opp_svs>; 3138 opp-peak-kBps = <3938000 1>; 3139 opp-level = <4>; 3140 }; 3141 3142 /* GEN 4 x4 */ 3143 opp-64000000-4 { 3144 opp-hz = /bits/ 64 <64000000>; 3145 required-opps = <&rpmhpd_opp_svs>; 3146 opp-peak-kBps = <7876000 1>; 3147 opp-level = <4>; 3148 }; 3149 3150 /* GEN 5 x1 */ 3151 opp-32000000-5 { 3152 opp-hz = /bits/ 64 <32000000>; 3153 required-opps = <&rpmhpd_opp_nom>; 3154 opp-peak-kBps = <3938000 1>; 3155 opp-level = <5>; 3156 }; 3157 3158 /* GEN 5 x2 */ 3159 opp-64000000-5 { 3160 opp-hz = /bits/ 64 <64000000>; 3161 required-opps = <&rpmhpd_opp_nom>; 3162 opp-peak-kBps = <7876000 1>; 3163 opp-level = <5>; 3164 }; 3165 3166 /* GEN 5 x4 */ 3167 opp-128000000-5 { 3168 opp-hz = /bits/ 64 <128000000>; 3169 required-opps = <&rpmhpd_opp_nom>; 3170 opp-peak-kBps = <15753000 1>; 3171 opp-level = <5>; 3172 }; 3173 }; 3174 3175 pcie5_port0: pcie@0 { 3176 device_type = "pci"; 3177 reg = <0x0 0x0 0x0 0x0 0x0>; 3178 bus-range = <0x01 0xff>; 3179 3180 phys = <&pcie5_phy>; 3181 3182 #address-cells = <3>; 3183 #size-cells = <2>; 3184 ranges; 3185 }; 3186 }; 3187 3188 pcie5_phy: phy@1b50000 { 3189 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3190 reg = <0x0 0x01b50000 0x0 0x10000>; 3191 3192 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3193 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3194 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3195 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3196 <&gcc GCC_PCIE_5_PIPE_CLK>, 3197 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3198 clock-names = "aux", 3199 "cfg_ahb", 3200 "ref", 3201 "rchng", 3202 "pipe", 3203 "pipediv2"; 3204 3205 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3206 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3207 reset-names = "phy", 3208 "phy_nocsr"; 3209 3210 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3211 assigned-clock-rates = <100000000>; 3212 3213 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3214 3215 #clock-cells = <0>; 3216 clock-output-names = "pcie5_pipe_clk"; 3217 3218 #phy-cells = <0>; 3219 3220 status = "disabled"; 3221 }; 3222 3223 pcie6: pci@1c00000 { 3224 device_type = "pci"; 3225 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3226 reg = <0x0 0x01c00000 0x0 0x3000>, 3227 <0x0 0x7e000000 0x0 0xf20>, 3228 <0x0 0x7e000f40 0x0 0xa8>, 3229 <0x0 0x7e001000 0x0 0x4000>, 3230 <0x0 0x7e100000 0x0 0x100000>, 3231 <0x0 0x01c03000 0x0 0x1000>; 3232 reg-names = "parf", 3233 "dbi", 3234 "elbi", 3235 "atu", 3236 "config", 3237 "mhi"; 3238 #address-cells = <3>; 3239 #size-cells = <2>; 3240 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3241 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3242 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3243 bus-range = <0x00 0xff>; 3244 3245 dma-coherent; 3246 3247 linux,pci-domain = <6>; 3248 num-lanes = <2>; 3249 3250 operating-points-v2 = <&pcie6_opp_table>; 3251 3252 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3253 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3254 3255 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3264 interrupt-names = "msi0", 3265 "msi1", 3266 "msi2", 3267 "msi3", 3268 "msi4", 3269 "msi5", 3270 "msi6", 3271 "msi7", 3272 "global"; 3273 3274 #interrupt-cells = <1>; 3275 interrupt-map-mask = <0 0 0 0x7>; 3276 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 3277 <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 3278 <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 3279 <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 3280 3281 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3282 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3283 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3284 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3285 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3286 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3287 clock-names = "aux", 3288 "cfg", 3289 "bus_master", 3290 "bus_slave", 3291 "slave_q2a", 3292 "noc_aggr"; 3293 3294 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3295 assigned-clock-rates = <19200000>; 3296 3297 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3298 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3299 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3300 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3301 interconnect-names = "pcie-mem", 3302 "cpu-pcie"; 3303 3304 resets = <&gcc GCC_PCIE_6_BCR>, 3305 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3306 reset-names = "pci", 3307 "link_down"; 3308 3309 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3310 3311 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3312 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3313 3314 status = "disabled"; 3315 3316 pcie6_opp_table: opp-table { 3317 compatible = "operating-points-v2"; 3318 3319 /* GEN 1 x1 */ 3320 opp-2500000-1 { 3321 opp-hz = /bits/ 64 <2500000>; 3322 required-opps = <&rpmhpd_opp_low_svs>; 3323 opp-peak-kBps = <250000 1>; 3324 opp-level = <1>; 3325 }; 3326 3327 /* GEN 1 x2 */ 3328 opp-5000000-1 { 3329 opp-hz = /bits/ 64 <5000000>; 3330 required-opps = <&rpmhpd_opp_low_svs>; 3331 opp-peak-kBps = <500000 1>; 3332 opp-level = <1>; 3333 }; 3334 3335 /* GEN 2 x1 */ 3336 opp-5000000-2 { 3337 opp-hz = /bits/ 64 <5000000>; 3338 required-opps = <&rpmhpd_opp_low_svs>; 3339 opp-peak-kBps = <500000 1>; 3340 opp-level = <2>; 3341 }; 3342 3343 /* GEN 2 x2 */ 3344 opp-10000000-2 { 3345 opp-hz = /bits/ 64 <10000000>; 3346 required-opps = <&rpmhpd_opp_low_svs>; 3347 opp-peak-kBps = <1000000 1>; 3348 opp-level = <2>; 3349 }; 3350 3351 /* GEN 3 x1 */ 3352 opp-8000000-3 { 3353 opp-hz = /bits/ 64 <8000000>; 3354 required-opps = <&rpmhpd_opp_low_svs>; 3355 opp-peak-kBps = <984500 1>; 3356 opp-level = <3>; 3357 }; 3358 3359 /* GEN 3 x2 */ 3360 opp-16000000-3 { 3361 opp-hz = /bits/ 64 <16000000>; 3362 required-opps = <&rpmhpd_opp_low_svs>; 3363 opp-peak-kBps = <1969000 1>; 3364 opp-level = <3>; 3365 }; 3366 3367 /* GEN 4 x1 */ 3368 opp-16000000-4 { 3369 opp-hz = /bits/ 64 <16000000>; 3370 required-opps = <&rpmhpd_opp_low_svs>; 3371 opp-peak-kBps = <1969000 1>; 3372 opp-level = <4>; 3373 }; 3374 3375 /* GEN 4 x2 */ 3376 opp-32000000-4 { 3377 opp-hz = /bits/ 64 <32000000>; 3378 required-opps = <&rpmhpd_opp_low_svs>; 3379 opp-peak-kBps = <3938000 1>; 3380 opp-level = <4>; 3381 }; 3382 3383 }; 3384 3385 pcie6_port0: pcie@0 { 3386 device_type = "pci"; 3387 reg = <0x0 0x0 0x0 0x0 0x0>; 3388 bus-range = <0x01 0xff>; 3389 3390 phys = <&pcie6_phy>; 3391 3392 #address-cells = <3>; 3393 #size-cells = <2>; 3394 ranges; 3395 }; 3396 }; 3397 3398 pcie6_phy: phy@1c06000 { 3399 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3400 reg = <0x0 0x01c06000 0x0 0x2000>; 3401 3402 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3403 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3404 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3405 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3406 <&gcc GCC_PCIE_6_PIPE_CLK>, 3407 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3408 clock-names = "aux", 3409 "cfg_ahb", 3410 "ref", 3411 "rchng", 3412 "pipe", 3413 "pipediv2"; 3414 3415 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3416 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3417 reset-names = "phy", 3418 "phy_nocsr"; 3419 3420 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3421 assigned-clock-rates = <100000000>; 3422 3423 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3424 3425 #clock-cells = <0>; 3426 clock-output-names = "pcie6_pipe_clk"; 3427 3428 #phy-cells = <0>; 3429 3430 status = "disabled"; 3431 }; 3432 3433 pcie3b: pci@1b80000 { 3434 device_type = "pci"; 3435 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3436 reg = <0x0 0x01b80000 0x0 0x3000>, 3437 <0x0 0x74000000 0x0 0xf20>, 3438 <0x0 0x74000f40 0x0 0xa8>, 3439 <0x0 0x74001000 0x0 0x4000>, 3440 <0x0 0x74100000 0x0 0x100000>, 3441 <0x0 0x01b83000 0x0 0x1000>; 3442 reg-names = "parf", 3443 "dbi", 3444 "elbi", 3445 "atu", 3446 "config", 3447 "mhi"; 3448 #address-cells = <3>; 3449 #size-cells = <2>; 3450 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3451 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3452 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3453 bus-range = <0x00 0xff>; 3454 3455 dma-coherent; 3456 3457 linux,pci-domain = <7>; 3458 num-lanes = <4>; 3459 3460 operating-points-v2 = <&pcie3b_opp_table>; 3461 3462 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3463 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3464 3465 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3474 interrupt-names = "msi0", 3475 "msi1", 3476 "msi2", 3477 "msi3", 3478 "msi4", 3479 "msi5", 3480 "msi6", 3481 "msi7", 3482 "global"; 3483 3484 #interrupt-cells = <1>; 3485 interrupt-map-mask = <0 0 0 0x7>; 3486 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, 3487 <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 3488 <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, 3489 <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 3490 3491 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3492 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3493 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3494 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3495 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3496 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3497 clock-names = "aux", 3498 "cfg", 3499 "bus_master", 3500 "bus_slave", 3501 "slave_q2a", 3502 "noc_aggr"; 3503 3504 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3505 assigned-clock-rates = <19200000>; 3506 3507 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3508 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3509 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3510 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3511 interconnect-names = "pcie-mem", 3512 "cpu-pcie"; 3513 3514 resets = <&gcc GCC_PCIE_3B_BCR>, 3515 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3516 reset-names = "pci", 3517 "link_down"; 3518 3519 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3520 3521 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3522 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3523 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3524 3525 status = "disabled"; 3526 3527 pcie3b_opp_table: opp-table { 3528 compatible = "operating-points-v2"; 3529 3530 /* GEN 1 x1 */ 3531 opp-2500000-1 { 3532 opp-hz = /bits/ 64 <2500000>; 3533 required-opps = <&rpmhpd_opp_low_svs>; 3534 opp-peak-kBps = <250000 1>; 3535 opp-level = <1>; 3536 }; 3537 3538 /* GEN 1 x2 */ 3539 opp-5000000-1 { 3540 opp-hz = /bits/ 64 <5000000>; 3541 required-opps = <&rpmhpd_opp_low_svs>; 3542 opp-peak-kBps = <500000 1>; 3543 opp-level = <1>; 3544 }; 3545 3546 /* GEN 1 x4 */ 3547 opp-10000000-1 { 3548 opp-hz = /bits/ 64 <10000000>; 3549 required-opps = <&rpmhpd_opp_low_svs>; 3550 opp-peak-kBps = <1000000 1>; 3551 opp-level = <1>; 3552 }; 3553 3554 /* GEN 2 x1 */ 3555 opp-5000000-2 { 3556 opp-hz = /bits/ 64 <5000000>; 3557 required-opps = <&rpmhpd_opp_low_svs>; 3558 opp-peak-kBps = <500000 1>; 3559 opp-level = <2>; 3560 }; 3561 3562 /* GEN 2 x2 */ 3563 opp-10000000-2 { 3564 opp-hz = /bits/ 64 <10000000>; 3565 required-opps = <&rpmhpd_opp_low_svs>; 3566 opp-peak-kBps = <1000000 1>; 3567 opp-level = <2>; 3568 }; 3569 3570 /* GEN 2 x4 */ 3571 opp-20000000-2 { 3572 opp-hz = /bits/ 64 <20000000>; 3573 required-opps = <&rpmhpd_opp_low_svs>; 3574 opp-peak-kBps = <2000000 1>; 3575 opp-level = <2>; 3576 }; 3577 3578 /* GEN 3 x1 */ 3579 opp-8000000-3 { 3580 opp-hz = /bits/ 64 <8000000>; 3581 required-opps = <&rpmhpd_opp_low_svs>; 3582 opp-peak-kBps = <984500 1>; 3583 opp-level = <3>; 3584 }; 3585 3586 /* GEN 3 x2 */ 3587 opp-16000000-3 { 3588 opp-hz = /bits/ 64 <16000000>; 3589 required-opps = <&rpmhpd_opp_low_svs>; 3590 opp-peak-kBps = <1969000 1>; 3591 opp-level = <3>; 3592 }; 3593 3594 /* GEN 3 x4 */ 3595 opp-32000000-3 { 3596 opp-hz = /bits/ 64 <32000000>; 3597 required-opps = <&rpmhpd_opp_low_svs>; 3598 opp-peak-kBps = <3938000 1>; 3599 opp-level = <3>; 3600 }; 3601 3602 /* GEN 4 x1 */ 3603 opp-16000000-4 { 3604 opp-hz = /bits/ 64 <16000000>; 3605 required-opps = <&rpmhpd_opp_svs>; 3606 opp-peak-kBps = <1969000 1>; 3607 opp-level = <4>; 3608 }; 3609 3610 /* GEN 4 x2 */ 3611 opp-32000000-4 { 3612 opp-hz = /bits/ 64 <32000000>; 3613 required-opps = <&rpmhpd_opp_svs>; 3614 opp-peak-kBps = <3938000 1>; 3615 opp-level = <4>; 3616 }; 3617 3618 /* GEN 4 x4 */ 3619 opp-64000000-4 { 3620 opp-hz = /bits/ 64 <64000000>; 3621 required-opps = <&rpmhpd_opp_svs>; 3622 opp-peak-kBps = <7876000 1>; 3623 opp-level = <4>; 3624 }; 3625 3626 /* GEN 5 x1 */ 3627 opp-32000000-5 { 3628 opp-hz = /bits/ 64 <32000000>; 3629 required-opps = <&rpmhpd_opp_nom>; 3630 opp-peak-kBps = <3938000 1>; 3631 opp-level = <5>; 3632 }; 3633 3634 /* GEN 5 x2 */ 3635 opp-64000000-5 { 3636 opp-hz = /bits/ 64 <64000000>; 3637 required-opps = <&rpmhpd_opp_nom>; 3638 opp-peak-kBps = <7876000 1>; 3639 opp-level = <5>; 3640 }; 3641 3642 /* GEN 5 x4 */ 3643 opp-128000000-5 { 3644 opp-hz = /bits/ 64 <128000000>; 3645 required-opps = <&rpmhpd_opp_nom>; 3646 opp-peak-kBps = <15753000 1>; 3647 opp-level = <5>; 3648 }; 3649 }; 3650 3651 pcie3b_port0: pcie@0 { 3652 device_type = "pci"; 3653 reg = <0x0 0x0 0x0 0x0 0x0>; 3654 bus-range = <0x01 0xff>; 3655 3656 phys = <&pcie3b_phy>; 3657 3658 #address-cells = <3>; 3659 #size-cells = <2>; 3660 ranges; 3661 }; 3662 }; 3663 3664 pcie3b_phy: phy@f10000 { 3665 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3666 reg = <0x0 0x00f10000 0x0 0x10000>; 3667 3668 clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 3669 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3670 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 3671 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 3672 <&gcc GCC_PCIE_3B_PIPE_CLK>, 3673 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 3674 clock-names = "aux", 3675 "cfg_ahb", 3676 "ref", 3677 "rchng", 3678 "pipe", 3679 "pipediv2"; 3680 3681 resets = <&gcc GCC_PCIE_3B_PHY_BCR>, 3682 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 3683 reset-names = "phy", 3684 "phy_nocsr"; 3685 3686 assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 3687 assigned-clock-rates = <100000000>; 3688 3689 power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; 3690 3691 #clock-cells = <0>; 3692 clock-output-names = "pcie3b_pipe_clk"; 3693 3694 #phy-cells = <0>; 3695 3696 status = "disabled"; 3697 }; 3698 3699 cryptobam: dma-controller@1dc4000 { 3700 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3701 reg = <0x0 0x01dc4000 0x0 0x28000>; 3702 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3703 #dma-cells = <1>; 3704 iommus = <&apps_smmu 0x80 0x0>, 3705 <&apps_smmu 0x81 0x0>; 3706 qcom,ee = <0>; 3707 qcom,controlled-remotely; 3708 num-channels = <20>; 3709 qcom,num-ees = <4>; 3710 }; 3711 3712 crypto: crypto@1dfa000 { 3713 compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; 3714 reg = <0x0 0x01dfa000 0x0 0x6000>; 3715 dmas = <&cryptobam 4>, <&cryptobam 5>; 3716 dma-names = "rx", 3717 "tx"; 3718 iommus = <&apps_smmu 0x80 0x0>, 3719 <&apps_smmu 0x81 0x0>; 3720 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 3721 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3722 interconnect-names = "memory"; 3723 }; 3724 3725 tcsr_mutex: hwlock@1f40000 { 3726 compatible = "qcom,tcsr-mutex"; 3727 reg = <0x0 0x01f40000 0x0 0x20000>; 3728 3729 #hwlock-cells = <1>; 3730 }; 3731 3732 tcsr: clock-controller@1fd5000 { 3733 compatible = "qcom,glymur-tcsr", 3734 "syscon"; 3735 reg = <0x0 0x1fd5000 0x0 0x21000>; 3736 clocks = <&rpmhcc RPMH_CXO_CLK>; 3737 #clock-cells = <1>; 3738 #reset-cells = <1>; 3739 }; 3740 3741 hsc_noc: interconnect@2000000 { 3742 compatible = "qcom,glymur-hscnoc"; 3743 reg = <0x0 0x02000000 0x0 0x93a080>; 3744 qcom,bcm-voters = <&apps_bcm_voter>; 3745 #interconnect-cells = <2>; 3746 }; 3747 3748 gxclkctl: clock-controller@3d64000 { 3749 compatible = "qcom,glymur-gxclkctl"; 3750 reg = <0x0 0x03d64000 0x0 0x6000>; 3751 3752 power-domains = <&rpmhpd RPMHPD_GFX>, 3753 <&rpmhpd RPMHPD_GMXC>, 3754 <&gpucc GPU_CC_CX_GDSC>; 3755 3756 #power-domain-cells = <1>; 3757 }; 3758 3759 gpucc: clock-controller@3d90000 { 3760 compatible = "qcom,glymur-gpucc"; 3761 reg = <0x0 0x03d90000 0x0 0x9800>; 3762 clocks = <&rpmhcc RPMH_CXO_CLK>, 3763 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3764 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3765 3766 power-domains = <&rpmhpd RPMHPD_MX>, 3767 <&rpmhpd RPMHPD_CX>; 3768 required-opps = <&rpmhpd_opp_low_svs>, 3769 <&rpmhpd_opp_low_svs>; 3770 3771 #clock-cells = <1>; 3772 #reset-cells = <1>; 3773 #power-domain-cells = <1>; 3774 }; 3775 3776 ipcc: mailbox@3e04000 { 3777 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 3778 reg = <0x0 0x03e04000 0x0 0x1000>; 3779 3780 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3781 interrupt-controller; 3782 #interrupt-cells = <3>; 3783 3784 #mbox-cells = <2>; 3785 }; 3786 3787 remoteproc_adsp: remoteproc@6800000 { 3788 compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; 3789 reg = <0x0 0x06800000 0x0 0x10000>; 3790 3791 iommus = <&apps_smmu 0x1000 0x0>; 3792 3793 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3794 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3795 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3796 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3797 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 3798 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 3799 interrupt-names = "wdog", 3800 "fatal", 3801 "ready", 3802 "handover", 3803 "stop-ack", 3804 "shutdown-ack"; 3805 3806 clocks = <&rpmhcc RPMH_CXO_CLK>; 3807 clock-names = "xo"; 3808 3809 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 3810 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3811 3812 power-domains = <&rpmhpd RPMHPD_LCX>, 3813 <&rpmhpd RPMHPD_LMX>; 3814 power-domain-names = "lcx", 3815 "lmx"; 3816 3817 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3818 3819 qcom,qmp = <&aoss_qmp>; 3820 3821 qcom,smem-states = <&smp2p_adsp_out 0>; 3822 qcom,smem-state-names = "stop"; 3823 3824 status = "disabled"; 3825 3826 remoteproc_adsp_glink: glink-edge { 3827 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 3828 IPCC_MPROC_SIGNAL_GLINK_QMP 3829 IRQ_TYPE_EDGE_RISING>; 3830 3831 mboxes = <&ipcc IPCC_MPROC_LPASS 3832 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3833 3834 qcom,remote-pid = <2>; 3835 3836 label = "lpass"; 3837 3838 fastrpc { 3839 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 3840 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3841 label = "adsp"; 3842 #address-cells = <1>; 3843 #size-cells = <0>; 3844 3845 compute-cb@3 { 3846 compatible = "qcom,fastrpc-compute-cb"; 3847 reg = <3>; 3848 3849 iommus = <&apps_smmu 0x1003 0x80>, 3850 <&apps_smmu 0x1063 0x20>; 3851 dma-coherent; 3852 }; 3853 3854 compute-cb@4 { 3855 compatible = "qcom,fastrpc-compute-cb"; 3856 reg = <4>; 3857 3858 iommus = <&apps_smmu 0x1004 0x80>, 3859 <&apps_smmu 0x1064 0x20>; 3860 dma-coherent; 3861 }; 3862 3863 compute-cb@5 { 3864 compatible = "qcom,fastrpc-compute-cb"; 3865 reg = <5>; 3866 3867 iommus = <&apps_smmu 0x1005 0x80>, 3868 <&apps_smmu 0x1065 0x20>; 3869 dma-coherent; 3870 }; 3871 3872 compute-cb@6 { 3873 compatible = "qcom,fastrpc-compute-cb"; 3874 reg = <6>; 3875 3876 iommus = <&apps_smmu 0x1006 0x80>, 3877 <&apps_smmu 0x1066 0x20>; 3878 dma-coherent; 3879 }; 3880 3881 compute-cb@7 { 3882 compatible = "qcom,fastrpc-compute-cb"; 3883 reg = <7>; 3884 3885 iommus = <&apps_smmu 0x1007 0x40>, 3886 <&apps_smmu 0x1067 0x0>, 3887 <&apps_smmu 0x1087 0x0>; 3888 dma-coherent; 3889 }; 3890 3891 compute-cb@8 { 3892 compatible = "qcom,fastrpc-compute-cb"; 3893 reg = <8>; 3894 3895 iommus = <&apps_smmu 0x1008 0x80>, 3896 <&apps_smmu 0x1068 0x20>; 3897 dma-coherent; 3898 }; 3899 }; 3900 }; 3901 }; 3902 3903 lpass_lpiaon_noc: interconnect@7400000 { 3904 compatible = "qcom,glymur-lpass-lpiaon-noc"; 3905 reg = <0x0 0x07400000 0x0 0x19080>; 3906 qcom,bcm-voters = <&apps_bcm_voter>; 3907 #interconnect-cells = <2>; 3908 }; 3909 3910 lpass_lpicx_noc: interconnect@7420000 { 3911 compatible = "qcom,glymur-lpass-lpicx-noc"; 3912 reg = <0x0 0x07420000 0x0 0x44080>; 3913 qcom,bcm-voters = <&apps_bcm_voter>; 3914 #interconnect-cells = <2>; 3915 }; 3916 3917 lpass_ag_noc: interconnect@7e40000 { 3918 compatible = "qcom,glymur-lpass-ag-noc"; 3919 reg = <0x0 0x07e40000 0x0 0xe080>; 3920 qcom,bcm-voters = <&apps_bcm_voter>; 3921 #interconnect-cells = <2>; 3922 }; 3923 3924 usb_2_hsphy: phy@88e0000 { 3925 compatible = "qcom,glymur-m31-eusb2-phy", 3926 "qcom,sm8750-m31-eusb2-phy"; 3927 3928 reg = <0x0 0x088e0000 0x0 0x29c>; 3929 #phy-cells = <0>; 3930 3931 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 3932 clock-names = "ref"; 3933 3934 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3935 3936 status = "disabled"; 3937 }; 3938 3939 usb_2_qmpphy: phy@88e1000 { 3940 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 3941 reg = <0x0 0x088e1000 0x0 0x8000>; 3942 3943 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3944 <&rpmhcc RPMH_CXO_CLK>, 3945 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3946 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, 3947 <&tcsr TCSR_USB4_2_CLKREF_EN>; 3948 clock-names = "aux", 3949 "ref", 3950 "com_aux", 3951 "usb3_pipe", 3952 "clkref"; 3953 3954 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3955 3956 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3957 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 3958 reset-names = "phy", 3959 "common"; 3960 3961 #clock-cells = <1>; 3962 #phy-cells = <1>; 3963 3964 mode-switch; 3965 orientation-switch; 3966 3967 status = "disabled"; 3968 3969 ports { 3970 #address-cells = <1>; 3971 #size-cells = <0>; 3972 3973 port@0 { 3974 reg = <0>; 3975 3976 usb_2_qmpphy_out: endpoint { 3977 }; 3978 }; 3979 3980 port@1 { 3981 reg = <1>; 3982 3983 usb_2_qmpphy_usb_ss_in: endpoint { 3984 remote-endpoint = <&usb_2_dwc3_ss>; 3985 }; 3986 }; 3987 3988 port@2 { 3989 reg = <2>; 3990 3991 usb_2_qmpphy_dp_in: endpoint { 3992 remote-endpoint = <&mdss_dp2_out>; 3993 }; 3994 }; 3995 }; 3996 }; 3997 3998 usb_0: usb@a600000 { 3999 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4000 reg = <0x0 0x0a600000 0x0 0xfc100>; 4001 4002 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4003 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4004 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4005 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4006 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4007 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4008 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4009 clock-names = "cfg_noc", 4010 "core", 4011 "iface", 4012 "sleep", 4013 "mock_utmi", 4014 "noc_aggr_north", 4015 "noc_aggr_south"; 4016 4017 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 4018 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4019 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 4020 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4021 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 4022 interrupt-names = "dwc_usb3", 4023 "pwr_event", 4024 "dp_hs_phy_irq", 4025 "dm_hs_phy_irq", 4026 "ss_phy_irq"; 4027 4028 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4029 resets = <&gcc GCC_USB30_PRIM_BCR>; 4030 4031 iommus = <&apps_smmu 0x1420 0x0>; 4032 phys = <&usb_0_hsphy>, 4033 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4034 phy-names = "usb2-phy", 4035 "usb3-phy"; 4036 4037 snps,hird-threshold = /bits/ 8 <0x0>; 4038 snps,dis-u1-entry-quirk; 4039 snps,dis-u2-entry-quirk; 4040 snps,is-utmi-l1-suspend; 4041 snps,usb3_lpm_capable; 4042 snps,has-lpm-erratum; 4043 tx-fifo-resize; 4044 snps,dis_u2_susphy_quirk; 4045 snps,dis_enblslpm_quirk; 4046 4047 usb-role-switch; 4048 4049 status = "disabled"; 4050 4051 ports { 4052 #address-cells = <1>; 4053 #size-cells = <0>; 4054 4055 port@0 { 4056 reg = <0>; 4057 4058 usb_0_dwc3_hs: endpoint { 4059 }; 4060 }; 4061 4062 port@1 { 4063 reg = <1>; 4064 4065 usb_0_dwc3_ss: endpoint { 4066 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4067 }; 4068 }; 4069 }; 4070 }; 4071 4072 usb_1: usb@a800000 { 4073 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4074 reg = <0x0 0x0a800000 0x0 0xfc100>; 4075 4076 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4077 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4078 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4079 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4080 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4081 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4082 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4083 clock-names = "cfg_noc", 4084 "core", 4085 "iface", 4086 "sleep", 4087 "mock_utmi", 4088 "noc_aggr_north", 4089 "noc_aggr_south"; 4090 4091 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 4092 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 4093 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 4094 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 4095 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 4096 interrupt-names = "dwc_usb3", 4097 "pwr_event", 4098 "dp_hs_phy_irq", 4099 "dm_hs_phy_irq", 4100 "ss_phy_irq"; 4101 4102 resets = <&gcc GCC_USB30_SEC_BCR>; 4103 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4104 4105 iommus = <&apps_smmu 0x1460 0x0>; 4106 4107 phys = <&usb_1_hsphy>, 4108 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4109 phy-names = "usb2-phy", 4110 "usb3-phy"; 4111 4112 snps,hird-threshold = /bits/ 8 <0x0>; 4113 snps,dis-u1-entry-quirk; 4114 snps,dis-u2-entry-quirk; 4115 snps,is-utmi-l1-suspend; 4116 snps,usb3_lpm_capable; 4117 snps,has-lpm-erratum; 4118 tx-fifo-resize; 4119 snps,dis_u2_susphy_quirk; 4120 snps,dis_enblslpm_quirk; 4121 4122 usb-role-switch; 4123 4124 status = "disabled"; 4125 4126 ports { 4127 #address-cells = <1>; 4128 #size-cells = <0>; 4129 4130 port@0 { 4131 reg = <0>; 4132 4133 usb_1_dwc3_hs: endpoint { 4134 }; 4135 }; 4136 4137 port@1 { 4138 reg = <1>; 4139 4140 usb_1_dwc3_ss: endpoint { 4141 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4142 }; 4143 }; 4144 }; 4145 }; 4146 4147 usb_2: usb@a000000 { 4148 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4149 reg = <0x0 0x0a000000 0x0 0xfc100>; 4150 4151 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4152 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4153 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4154 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4155 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4156 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4157 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4158 clock-names = "cfg_noc", 4159 "core", 4160 "iface", 4161 "sleep", 4162 "mock_utmi", 4163 "noc_aggr_north", 4164 "noc_aggr_south"; 4165 4166 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 4167 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4168 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 4169 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 4170 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 4171 interrupt-names = "dwc_usb3", 4172 "pwr_event", 4173 "dp_hs_phy_irq", 4174 "dm_hs_phy_irq", 4175 "ss_phy_irq"; 4176 4177 resets = <&gcc GCC_USB30_TERT_BCR>; 4178 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4179 4180 iommus = <&apps_smmu 0x420 0x0>; 4181 4182 phys = <&usb_2_hsphy>, 4183 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 4184 phy-names = "usb2-phy", 4185 "usb3-phy"; 4186 4187 snps,hird-threshold = /bits/ 8 <0x0>; 4188 snps,dis-u1-entry-quirk; 4189 snps,dis-u2-entry-quirk; 4190 snps,is-utmi-l1-suspend; 4191 snps,usb3_lpm_capable; 4192 snps,has-lpm-erratum; 4193 tx-fifo-resize; 4194 snps,dis_u2_susphy_quirk; 4195 snps,dis_enblslpm_quirk; 4196 4197 usb-role-switch; 4198 4199 status = "disabled"; 4200 4201 ports { 4202 #address-cells = <1>; 4203 #size-cells = <0>; 4204 4205 port@0 { 4206 reg = <0>; 4207 4208 usb_2_dwc3_hs: endpoint { 4209 }; 4210 }; 4211 4212 port@1 { 4213 reg = <1>; 4214 4215 usb_2_dwc3_ss: endpoint { 4216 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 4217 }; 4218 }; 4219 }; 4220 }; 4221 4222 usb_hs: usb@a200000 { 4223 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4224 reg = <0x0 0x0a200000 0x0 0xfc100>; 4225 4226 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4227 <&gcc GCC_USB20_MASTER_CLK>, 4228 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4229 <&gcc GCC_USB20_SLEEP_CLK>, 4230 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4231 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4232 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4233 clock-names = "cfg_noc", 4234 "core", 4235 "iface", 4236 "sleep", 4237 "mock_utmi", 4238 "noc_aggr_north", 4239 "noc_aggr_south"; 4240 4241 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4242 <&gcc GCC_USB20_MASTER_CLK>; 4243 assigned-clock-rates = <19200000>, <200000000>; 4244 4245 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4246 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 4247 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 4248 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4249 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 4250 interrupt-names = "dwc_usb3", 4251 "pwr_event", 4252 "dp_hs_phy_irq", 4253 "dm_hs_phy_irq", 4254 "hs_phy_irq"; 4255 4256 resets = <&gcc GCC_USB20_PRIM_BCR>; 4257 4258 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4259 required-opps = <&rpmhpd_opp_nom>; 4260 4261 iommus = <&apps_smmu 0x0ce0 0x0>; 4262 4263 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4264 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4265 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4266 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4267 interconnect-names = "usb-ddr", 4268 "apps-usb"; 4269 4270 phys = <&usb_hs_phy>; 4271 phy-names = "usb2-phy"; 4272 4273 snps,hird-threshold = /bits/ 8 <0x0>; 4274 snps,dis-u1-entry-quirk; 4275 snps,dis-u2-entry-quirk; 4276 snps,is-utmi-l1-suspend; 4277 snps,usb3_lpm_capable; 4278 snps,has-lpm-erratum; 4279 tx-fifo-resize; 4280 snps,dis_u2_susphy_quirk; 4281 snps,dis_enblslpm_quirk; 4282 4283 dr_mode = "host"; 4284 4285 maximum-speed = "high-speed"; 4286 4287 status = "disabled"; 4288 }; 4289 4290 usb_mp: usb@a400000 { 4291 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 4292 reg = <0x0 0x0a400000 0x0 0xfc100>; 4293 4294 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4295 <&gcc GCC_USB30_MP_MASTER_CLK>, 4296 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4297 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4298 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4299 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4300 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4301 clock-names = "cfg_noc", 4302 "core", 4303 "iface", 4304 "sleep", 4305 "mock_utmi", 4306 "noc_aggr_north", 4307 "noc_aggr_south"; 4308 4309 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4310 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4311 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4312 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 4313 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4314 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 4315 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 4316 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 4317 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 4318 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 4319 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 4320 interrupt-names = "dwc_usb3", 4321 "pwr_event_1", 4322 "pwr_event_2", 4323 "hs_phy_1", 4324 "hs_phy_2", 4325 "dp_hs_phy_1", 4326 "dm_hs_phy_1", 4327 "dp_hs_phy_2", 4328 "dm_hs_phy_2", 4329 "ss_phy_1", 4330 "ss_phy_2"; 4331 4332 resets = <&gcc GCC_USB30_MP_BCR>; 4333 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4334 4335 iommus = <&apps_smmu 0xda0 0x0>; 4336 4337 phys = <&usb_mp_hsphy0>, 4338 <&usb_mp_qmpphy0>, 4339 <&usb_mp_hsphy1>, 4340 <&usb_mp_qmpphy1>; 4341 phy-names = "usb2-0", 4342 "usb3-0", 4343 "usb2-1", 4344 "usb3-1"; 4345 4346 snps,hird-threshold = /bits/ 8 <0x0>; 4347 snps,dis-u1-entry-quirk; 4348 snps,dis-u2-entry-quirk; 4349 snps,is-utmi-l1-suspend; 4350 snps,usb3_lpm_capable; 4351 snps,has-lpm-erratum; 4352 tx-fifo-resize; 4353 snps,dis_u2_susphy_quirk; 4354 snps,dis_enblslpm_quirk; 4355 4356 dr_mode = "host"; 4357 4358 status = "disabled"; 4359 }; 4360 4361 mdss: display-subsystem@ae00000 { 4362 compatible = "qcom,glymur-mdss"; 4363 reg = <0x0 0x0ae00000 0x0 0x1000>; 4364 reg-names = "mdss"; 4365 4366 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4367 4368 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4369 <&gcc GCC_DISP_HF_AXI_CLK>, 4370 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4371 4372 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4373 4374 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4376 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4377 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4378 interconnect-names = "mdp0-mem", 4379 "cpu-cfg"; 4380 4381 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4382 4383 iommus = <&apps_smmu 0x1de0 0x2>; 4384 4385 interrupt-controller; 4386 #interrupt-cells = <1>; 4387 4388 #address-cells = <2>; 4389 #size-cells = <2>; 4390 ranges; 4391 4392 status = "disabled"; 4393 4394 mdss_mdp: display-controller@ae01000 { 4395 compatible = "qcom,glymur-dpu"; 4396 reg = <0x0 0x0ae01000 0x0 0x93000>, 4397 <0x0 0x0aeb0000 0x0 0x3000>; 4398 reg-names = "mdp", 4399 "vbif"; 4400 4401 interrupts-extended = <&mdss 0>; 4402 4403 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4404 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4405 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4406 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4407 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4408 clock-names = "nrt_bus", 4409 "iface", 4410 "lut", 4411 "core", 4412 "vsync"; 4413 4414 operating-points-v2 = <&mdp_opp_table>; 4415 4416 power-domains = <&rpmhpd RPMHPD_MMCX>; 4417 4418 ports { 4419 #address-cells = <1>; 4420 #size-cells = <0>; 4421 4422 port@0 { 4423 reg = <0>; 4424 4425 dpu_intf0_out: endpoint { 4426 remote-endpoint = <&mdss_dp0_in>; 4427 }; 4428 }; 4429 4430 port@4 { 4431 reg = <4>; 4432 4433 mdss_intf4_out: endpoint { 4434 remote-endpoint = <&mdss_dp1_in>; 4435 }; 4436 }; 4437 4438 port@5 { 4439 reg = <5>; 4440 4441 mdss_intf5_out: endpoint { 4442 remote-endpoint = <&mdss_dp3_in>; 4443 }; 4444 }; 4445 4446 port@6 { 4447 reg = <6>; 4448 4449 mdss_intf6_out: endpoint { 4450 remote-endpoint = <&mdss_dp2_in>; 4451 }; 4452 }; 4453 }; 4454 4455 mdp_opp_table: opp-table { 4456 compatible = "operating-points-v2"; 4457 4458 opp-156000000 { 4459 opp-hz = /bits/ 64 <156000000>; 4460 required-opps = <&rpmhpd_opp_low_svs_d1>; 4461 }; 4462 4463 opp-205000000 { 4464 opp-hz = /bits/ 64 <205000000>; 4465 required-opps = <&rpmhpd_opp_low_svs>; 4466 }; 4467 4468 opp-337000000 { 4469 opp-hz = /bits/ 64 <337000000>; 4470 required-opps = <&rpmhpd_opp_svs>; 4471 }; 4472 4473 opp-417000000 { 4474 opp-hz = /bits/ 64 <417000000>; 4475 required-opps = <&rpmhpd_opp_svs_l1>; 4476 }; 4477 4478 opp-532000000 { 4479 opp-hz = /bits/ 64 <532000000>; 4480 required-opps = <&rpmhpd_opp_nom>; 4481 }; 4482 4483 opp-600000000 { 4484 opp-hz = /bits/ 64 <600000000>; 4485 required-opps = <&rpmhpd_opp_nom_l1>; 4486 }; 4487 4488 opp-660000000 { 4489 opp-hz = /bits/ 64 <660000000>; 4490 required-opps = <&rpmhpd_opp_turbo>; 4491 }; 4492 4493 opp-717000000 { 4494 opp-hz = /bits/ 64 <717000000>; 4495 required-opps = <&rpmhpd_opp_turbo_l1>; 4496 }; 4497 }; 4498 }; 4499 4500 mdss_dp0: displayport-controller@af54000 { 4501 compatible = "qcom,glymur-dp"; 4502 reg = <0x0 0xaf54000 0x0 0x200>, 4503 <0x0 0xaf54200 0x0 0x200>, 4504 <0x0 0xaf55000 0x0 0xc00>, 4505 <0x0 0xaf56000 0x0 0x400>, 4506 <0x0 0xaf57000 0x0 0x400>, 4507 <0x0 0xaf58000 0x0 0x400>, 4508 <0x0 0xaf59000 0x0 0x400>, 4509 <0x0 0xaf5a000 0x0 0x600>, 4510 <0x0 0xaf5b000 0x0 0x600>; 4511 4512 interrupts-extended = <&mdss 12>; 4513 4514 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4515 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4516 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4517 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4518 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4519 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4520 clock-names = "core_iface", 4521 "core_aux", 4522 "ctrl_link", 4523 "ctrl_link_iface", 4524 "stream_pixel", 4525 "stream_1_pixel"; 4526 4527 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4528 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4529 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4530 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4531 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4532 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4533 4534 operating-points-v2 = <&mdss_dp0_opp_table>; 4535 4536 power-domains = <&rpmhpd RPMHPD_MMCX>; 4537 4538 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4539 phy-names = "dp"; 4540 4541 #sound-dai-cells = <0>; 4542 4543 status = "disabled"; 4544 4545 ports { 4546 #address-cells = <1>; 4547 #size-cells = <0>; 4548 4549 port@0 { 4550 reg = <0>; 4551 4552 mdss_dp0_in: endpoint { 4553 remote-endpoint = <&dpu_intf0_out>; 4554 }; 4555 }; 4556 4557 port@1 { 4558 reg = <1>; 4559 4560 mdss_dp0_out: endpoint { 4561 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 4562 }; 4563 }; 4564 }; 4565 4566 mdss_dp0_opp_table: opp-table { 4567 compatible = "operating-points-v2"; 4568 4569 opp-270000000 { 4570 opp-hz = /bits/ 64 <270000000>; 4571 required-opps = <&rpmhpd_opp_low_svs>; 4572 }; 4573 4574 opp-540000000 { 4575 opp-hz = /bits/ 64 <540000000>; 4576 required-opps = <&rpmhpd_opp_svs>; 4577 }; 4578 4579 opp-675000000 { 4580 opp-hz = /bits/ 64 <675000000>; 4581 required-opps = <&rpmhpd_opp_svs_l1>; 4582 }; 4583 4584 opp-810000000 { 4585 opp-hz = /bits/ 64 <810000000>; 4586 required-opps = <&rpmhpd_opp_nom>; 4587 }; 4588 }; 4589 }; 4590 4591 mdss_dp1: displayport-controller@af5c000 { 4592 compatible = "qcom,glymur-dp"; 4593 reg = <0x0 0xaf5c000 0x0 0x200>, 4594 <0x0 0xaf5c200 0x0 0x200>, 4595 <0x0 0xaf5d000 0x0 0xc00>, 4596 <0x0 0xaf5e000 0x0 0x400>, 4597 <0x0 0xaf5f000 0x0 0x400>, 4598 <0x0 0xaf60000 0x0 0x400>, 4599 <0x0 0xaf61000 0x0 0x400>, 4600 <0x0 0xaf62000 0x0 0x600>, 4601 <0x0 0xaf63000 0x0 0x600>; 4602 4603 interrupts-extended = <&mdss 13>; 4604 4605 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4606 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4607 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4608 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4609 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 4610 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 4611 clock-names = "core_iface", 4612 "core_aux", 4613 "ctrl_link", 4614 "ctrl_link_iface", 4615 "stream_pixel", 4616 "stream_1_pixel"; 4617 4618 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4619 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 4620 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 4621 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4622 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4623 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4624 4625 operating-points-v2 = <&mdss_dp0_opp_table>; 4626 4627 power-domains = <&rpmhpd RPMHPD_MMCX>; 4628 4629 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4630 phy-names = "dp"; 4631 4632 #sound-dai-cells = <0>; 4633 4634 status = "disabled"; 4635 4636 ports { 4637 #address-cells = <1>; 4638 #size-cells = <0>; 4639 4640 port@0 { 4641 reg = <0>; 4642 4643 mdss_dp1_in: endpoint { 4644 remote-endpoint = <&mdss_intf4_out>; 4645 }; 4646 }; 4647 4648 port@1 { 4649 reg = <1>; 4650 4651 mdss_dp1_out: endpoint { 4652 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4653 }; 4654 }; 4655 }; 4656 }; 4657 4658 mdss_dp2: displayport-controller@af64000 { 4659 compatible = "qcom,glymur-dp"; 4660 reg = <0x0 0x0af64000 0x0 0x200>, 4661 <0x0 0x0af64200 0x0 0x200>, 4662 <0x0 0x0af65000 0x0 0xc00>, 4663 <0x0 0x0af66000 0x0 0x400>, 4664 <0x0 0x0af67000 0x0 0x400>, 4665 <0x0 0x0af68000 0x0 0x400>, 4666 <0x0 0x0af69000 0x0 0x400>, 4667 <0x0 0x0af6a000 0x0 0x600>, 4668 <0x0 0x0af6b000 0x0 0x600>; 4669 4670 interrupts-extended = <&mdss 14>; 4671 4672 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4673 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4674 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4675 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4676 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 4677 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 4678 clock-names = "core_iface", 4679 "core_aux", 4680 "ctrl_link", 4681 "ctrl_link_iface", 4682 "stream_pixel", 4683 "stream_1_pixel"; 4684 4685 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4686 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 4687 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 4688 assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4689 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4690 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4691 4692 operating-points-v2 = <&mdss_dp0_opp_table>; 4693 4694 power-domains = <&rpmhpd RPMHPD_MMCX>; 4695 4696 phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; 4697 phy-names = "dp"; 4698 4699 #sound-dai-cells = <0>; 4700 4701 status = "disabled"; 4702 4703 ports { 4704 #address-cells = <1>; 4705 #size-cells = <0>; 4706 4707 port@0 { 4708 reg = <0>; 4709 mdss_dp2_in: endpoint { 4710 remote-endpoint = <&mdss_intf6_out>; 4711 }; 4712 }; 4713 4714 port@1 { 4715 reg = <1>; 4716 4717 mdss_dp2_out: endpoint { 4718 remote-endpoint = <&usb_2_qmpphy_dp_in>; 4719 }; 4720 }; 4721 }; 4722 }; 4723 4724 mdss_dp3: displayport-controller@af6c000 { 4725 compatible = "qcom,glymur-dp"; 4726 reg = <0x0 0x0af6c000 0x0 0x200>, 4727 <0x0 0x0af6c200 0x0 0x200>, 4728 <0x0 0x0af6d000 0x0 0xc00>, 4729 <0x0 0x0af6e000 0x0 0x400>, 4730 <0x0 0x0af6f000 0x0 0x400>, 4731 <0x0 0x0af70000 0x0 0x400>, 4732 <0x0 0x0af71000 0x0 0x400>, 4733 <0x0 0x0af72000 0x0 0x600>, 4734 <0x0 0x0af73000 0x0 0x600>; 4735 4736 interrupts-extended = <&mdss 15>; 4737 4738 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4739 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4740 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4741 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4742 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4743 clock-names = "core_iface", 4744 "core_aux", 4745 "ctrl_link", 4746 "ctrl_link_iface", 4747 "stream_pixel"; 4748 4749 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4750 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4751 assigned-clock-parents = <&mdss_dp3_phy 0>, 4752 <&mdss_dp3_phy 1>; 4753 4754 operating-points-v2 = <&mdss_dp0_opp_table>; 4755 4756 power-domains = <&rpmhpd RPMHPD_MMCX>; 4757 4758 phys = <&mdss_dp3_phy>; 4759 phy-names = "dp"; 4760 4761 #sound-dai-cells = <0>; 4762 4763 status = "disabled"; 4764 4765 ports { 4766 #address-cells = <1>; 4767 #size-cells = <0>; 4768 4769 port@0 { 4770 reg = <0>; 4771 4772 mdss_dp3_in: endpoint { 4773 remote-endpoint = <&mdss_intf5_out>; 4774 }; 4775 }; 4776 4777 port@1 { 4778 reg = <1>; 4779 4780 mdss_dp3_out: endpoint { 4781 }; 4782 }; 4783 }; 4784 }; 4785 }; 4786 4787 videocc: clock-controller@aaf0000 { 4788 compatible = "qcom,glymur-videocc"; 4789 reg = <0x0 0x0aaf0000 0x0 0x10000>; 4790 clocks = <&rpmhcc RPMH_CXO_CLK>, 4791 <&rpmhcc RPMH_CXO_CLK_A>; 4792 4793 power-domains = <&rpmhpd RPMHPD_MMCX>, 4794 <&rpmhpd RPMHPD_MXC>; 4795 required-opps = <&rpmhpd_opp_low_svs>, 4796 <&rpmhpd_opp_low_svs>; 4797 4798 #clock-cells = <1>; 4799 #reset-cells = <1>; 4800 #power-domain-cells = <1>; 4801 }; 4802 4803 dispcc: clock-controller@af00000 { 4804 compatible = "qcom,glymur-dispcc"; 4805 reg = <0x0 0x0af00000 0x0 0x20000>; 4806 clocks = <&rpmhcc RPMH_CXO_CLK>, 4807 <&sleep_clk>, 4808 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4809 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4810 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4811 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4812 <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 4813 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4814 <&mdss_dp3_phy 0>, /* dp3 */ 4815 <&mdss_dp3_phy 1>, 4816 <0>, /* dsi0 */ 4817 <0>, 4818 <0>, /* dsi1 */ 4819 <0>, 4820 <0>, 4821 <0>, 4822 <0>, 4823 <0>; 4824 power-domains = <&rpmhpd RPMHPD_MMCX>; 4825 required-opps = <&rpmhpd_opp_low_svs>; 4826 #clock-cells = <1>; 4827 #reset-cells = <1>; 4828 #power-domain-cells = <1>; 4829 }; 4830 4831 pdc: interrupt-controller@b220000 { 4832 compatible = "qcom,glymur-pdc", "qcom,pdc"; 4833 reg = <0x0 0x0b220000 0x0 0x10000>; 4834 qcom,pdc-ranges = <0 745 51>, 4835 <51 527 47>, 4836 <98 609 32>, 4837 <130 717 12>, 4838 <142 251 5>, 4839 <147 796 16>, 4840 <171 4104 36>; 4841 #interrupt-cells = <2>; 4842 interrupt-parent = <&intc>; 4843 interrupt-controller; 4844 }; 4845 4846 tsens0: thermal-sensor@c22c000 { 4847 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4848 reg = <0x0 0x0c22c000 0x0 0x1000>, 4849 <0x0 0x0c222000 0x0 0x1000>; 4850 4851 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 4852 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 4853 interrupt-names = "uplow", 4854 "critical"; 4855 4856 #qcom,sensors = <13>; 4857 4858 #thermal-sensor-cells = <1>; 4859 }; 4860 4861 tsens1: thermal-sensor@c22d000 { 4862 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4863 reg = <0x0 0x0c22d000 0x0 0x1000>, 4864 <0x0 0x0c223000 0x0 0x1000>; 4865 4866 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 4868 interrupt-names = "uplow", 4869 "critical"; 4870 4871 #qcom,sensors = <9>; 4872 4873 #thermal-sensor-cells = <1>; 4874 }; 4875 4876 tsens2: thermal-sensor@c22e000 { 4877 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4878 reg = <0x0 0x0c22e000 0x0 0x1000>, 4879 <0x0 0x0c224000 0x0 0x1000>; 4880 4881 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 4882 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 4883 interrupt-names = "uplow", 4884 "critical"; 4885 4886 #qcom,sensors = <13>; 4887 4888 #thermal-sensor-cells = <1>; 4889 }; 4890 4891 tsens3: thermal-sensor@c22f000 { 4892 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4893 reg = <0x0 0x0c22f000 0x0 0x1000>, 4894 <0x0 0x0c225000 0x0 0x1000>; 4895 4896 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 4897 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 4898 interrupt-names = "uplow", 4899 "critical"; 4900 4901 #qcom,sensors = <8>; 4902 4903 #thermal-sensor-cells = <1>; 4904 }; 4905 4906 tsens4: thermal-sensor@c230000 { 4907 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4908 reg = <0x0 0x0c230000 0x0 0x1000>, 4909 <0x0 0x0c226000 0x0 0x1000>; 4910 4911 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4912 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4913 interrupt-names = "uplow", 4914 "critical"; 4915 4916 #qcom,sensors = <13>; 4917 4918 #thermal-sensor-cells = <1>; 4919 }; 4920 4921 tsens5: thermal-sensor@c231000 { 4922 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4923 reg = <0x0 0x0c231000 0x0 0x1000>, 4924 <0x0 0x0c227000 0x0 0x1000>; 4925 4926 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 4927 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 4928 interrupt-names = "uplow", 4929 "critical"; 4930 4931 #qcom,sensors = <8>; 4932 4933 #thermal-sensor-cells = <1>; 4934 }; 4935 4936 tsens6: thermal-sensor@c232000 { 4937 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4938 reg = <0x0 0x0c232000 0x0 0x1000>, 4939 <0x0 0x0c228000 0x0 0x1000>; 4940 4941 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 4943 interrupt-names = "uplow", 4944 "critical"; 4945 4946 #qcom,sensors = <13>; 4947 4948 #thermal-sensor-cells = <1>; 4949 }; 4950 4951 tsens7: thermal-sensor@c233000 { 4952 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4953 reg = <0x0 0x0c233000 0x0 0x1000>, 4954 <0x0 0x0c229000 0x0 0x1000>; 4955 4956 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 4957 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 4958 interrupt-names = "uplow", 4959 "critical"; 4960 4961 #qcom,sensors = <15>; 4962 4963 #thermal-sensor-cells = <1>; 4964 }; 4965 4966 aoss_qmp: power-management@c300000 { 4967 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 4968 reg = <0x0 0x0c300000 0x0 0x400>; 4969 interrupt-parent = <&ipcc>; 4970 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4971 IRQ_TYPE_EDGE_RISING>; 4972 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4973 4974 #clock-cells = <0>; 4975 }; 4976 4977 sram@c30f000 { 4978 compatible = "qcom,rpmh-stats"; 4979 reg = <0x0 0x0c30f000 0x0 0x400>; 4980 }; 4981 4982 arbiter@c400000 { 4983 compatible = "qcom,glymur-spmi-pmic-arb"; 4984 reg = <0x0 0x0c400000 0x0 0x3000>, 4985 <0x0 0x0c900000 0x0 0x400000>, 4986 <0x0 0x0c4c0000 0x0 0x400000>, 4987 <0x0 0x0c403000 0x0 0x8000>; 4988 reg-names = "core", 4989 "chnls", 4990 "obsrvr", 4991 "chnl_map"; 4992 #address-cells = <2>; 4993 #size-cells = <2>; 4994 ranges; 4995 qcom,channel = <0>; 4996 qcom,ee = <0>; 4997 4998 spmi_bus0: spmi@c426000 { 4999 reg = <0x0 0x0c426000 0x0 0x4000>, 5000 <0x0 0x0c8c0000 0x0 0x10000>, 5001 <0x0 0x0c42a000 0x0 0x8000>; 5002 reg-names = "cnfg", 5003 "intr", 5004 "chnl_owner"; 5005 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5006 interrupt-names = "periph_irq"; 5007 interrupt-controller; 5008 #interrupt-cells = <4>; 5009 #address-cells = <2>; 5010 #size-cells = <0>; 5011 }; 5012 5013 spmi_bus1: spmi@c437000 { 5014 reg = <0x0 0x0c437000 0x0 0x4000>, 5015 <0x0 0x0c8d0000 0x0 0x10000>, 5016 <0x0 0x0c43b000 0x0 0x8000>; 5017 reg-names = "cnfg", 5018 "intr", 5019 "chnl_owner"; 5020 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5021 interrupt-names = "periph_irq"; 5022 interrupt-controller; 5023 #interrupt-cells = <4>; 5024 #address-cells = <2>; 5025 #size-cells = <0>; 5026 }; 5027 5028 spmi_bus2: spmi@c48000 { 5029 reg = <0x0 0x0c448000 0x0 0x4000>, 5030 <0x0 0x0c8e0000 0x0 0x10000>, 5031 <0x0 0x0c44c000 0x0 0x8000>; 5032 reg-names = "cnfg", 5033 "intr", 5034 "chnl_owner"; 5035 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 5036 interrupt-names = "periph_irq"; 5037 interrupt-controller; 5038 #interrupt-cells = <4>; 5039 #address-cells = <2>; 5040 #size-cells = <0>; 5041 }; 5042 }; 5043 5044 tlmm: pinctrl@f100000 { 5045 compatible = "qcom,glymur-tlmm"; 5046 reg = <0x0 0x0f100000 0x0 0xf00000>; 5047 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5048 gpio-controller; 5049 #gpio-cells = <2>; 5050 interrupt-controller; 5051 #interrupt-cells = <2>; 5052 gpio-ranges = <&tlmm 0 0 249>; 5053 wakeup-parent = <&pdc>; 5054 5055 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5056 /* SDA, SCL */ 5057 pins = "gpio0", "gpio1"; 5058 function = "qup0_se0"; 5059 drive-strength = <2>; 5060 bias-pull-up = <2200>; 5061 }; 5062 5063 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5064 /* SDA, SCL */ 5065 pins = "gpio4", "gpio5"; 5066 function = "qup0_se1"; 5067 drive-strength = <2>; 5068 bias-pull-up = <2200>; 5069 }; 5070 5071 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5072 /* SDA, SCL */ 5073 pins = "gpio8", "gpio9"; 5074 function = "qup0_se2"; 5075 drive-strength = <2>; 5076 bias-pull-up = <2200>; 5077 }; 5078 5079 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5080 /* SDA, SCL */ 5081 pins = "gpio12", "gpio13"; 5082 function = "qup0_se3"; 5083 drive-strength = <2>; 5084 bias-pull-up = <2200>; 5085 }; 5086 5087 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5088 /* SDA, SCL */ 5089 pins = "gpio16", "gpio17"; 5090 function = "qup0_se4"; 5091 drive-strength = <2>; 5092 bias-pull-up = <2200>; 5093 }; 5094 5095 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5096 /* SDA, SCL */ 5097 pins = "gpio20", "gpio21"; 5098 function = "qup0_se5"; 5099 drive-strength = <2>; 5100 bias-pull-up = <2200>; 5101 }; 5102 5103 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5104 /* SDA, SCL */ 5105 pins = "gpio6", "gpio7"; 5106 function = "qup0_se6"; 5107 drive-strength = <2>; 5108 bias-pull-up = <2200>; 5109 }; 5110 5111 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5112 /* SDA, SCL */ 5113 pins = "gpio14", "gpio15"; 5114 function = "qup0_se7"; 5115 drive-strength = <2>; 5116 bias-pull-up = <2200>; 5117 }; 5118 5119 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5120 /* SDA, SCL */ 5121 pins = "gpio32", "gpio33"; 5122 function = "qup1_se0"; 5123 drive-strength = <2>; 5124 bias-pull-up = <2200>; 5125 }; 5126 5127 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5128 /* SDA, SCL */ 5129 pins = "gpio36", "gpio37"; 5130 function = "qup1_se1"; 5131 drive-strength = <2>; 5132 bias-pull-up = <2200>; 5133 }; 5134 5135 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5136 /* SDA, SCL */ 5137 pins = "gpio40", "gpio41"; 5138 function = "qup1_se2"; 5139 drive-strength = <2>; 5140 bias-pull-up = <2200>; 5141 }; 5142 5143 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5144 /* SDA, SCL */ 5145 pins = "gpio44", "gpio45"; 5146 function = "qup1_se3"; 5147 drive-strength = <2>; 5148 bias-pull-up = <2200>; 5149 }; 5150 5151 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5152 /* SDA, SCL */ 5153 pins = "gpio48", "gpio49"; 5154 function = "qup1_se4"; 5155 drive-strength = <2>; 5156 bias-pull-up = <2200>; 5157 }; 5158 5159 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5160 /* SDA, SCL */ 5161 pins = "gpio52", "gpio53"; 5162 function = "qup1_se5"; 5163 drive-strength = <2>; 5164 bias-pull-up = <2200>; 5165 }; 5166 5167 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5168 /* SDA, SCL */ 5169 pins = "gpio56", "gpio57"; 5170 function = "qup1_se6"; 5171 drive-strength = <2>; 5172 bias-pull-up = <2200>; 5173 }; 5174 5175 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5176 /* SDA, SCL */ 5177 pins = "gpio54", "gpio55"; 5178 function = "qup1_se7"; 5179 drive-strength = <2>; 5180 bias-pull-up = <2200>; 5181 }; 5182 5183 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5184 /* SDA, SCL */ 5185 pins = "gpio64", "gpio65"; 5186 function = "qup2_se0"; 5187 drive-strength = <2>; 5188 bias-pull-up = <2200>; 5189 }; 5190 5191 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5192 /* SDA, SCL */ 5193 pins = "gpio68", "gpio69"; 5194 function = "qup2_se1"; 5195 drive-strength = <2>; 5196 bias-pull-up = <2200>; 5197 }; 5198 5199 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5200 /* SDA, SCL */ 5201 pins = "gpio72", "gpio73"; 5202 function = "qup2_se2"; 5203 drive-strength = <2>; 5204 bias-pull-up = <2200>; 5205 }; 5206 5207 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5208 /* SDA, SCL */ 5209 pins = "gpio76", "gpio77"; 5210 function = "qup2_se3"; 5211 drive-strength = <2>; 5212 bias-pull-up = <2200>; 5213 }; 5214 5215 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5216 /* SDA, SCL */ 5217 pins = "gpio80", "gpio81"; 5218 function = "qup2_se4"; 5219 drive-strength = <2>; 5220 bias-pull-up = <2200>; 5221 }; 5222 5223 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5224 /* SDA, SCL */ 5225 pins = "gpio84", "gpio85"; 5226 function = "qup2_se5"; 5227 drive-strength = <2>; 5228 bias-pull-up = <2200>; 5229 }; 5230 5231 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5232 /* SDA, SCL */ 5233 pins = "gpio88", "gpio89"; 5234 function = "qup2_se6"; 5235 drive-strength = <2>; 5236 bias-pull-up = <2200>; 5237 }; 5238 5239 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5240 /* SDA, SCL */ 5241 pins = "gpio80", "gpio81"; 5242 function = "qup2_se7"; 5243 drive-strength = <2>; 5244 bias-pull-up = <2200>; 5245 }; 5246 5247 qup_spi0_cs: qup-spi0-cs-state { 5248 pins = "gpio3"; 5249 function = "qup0_se0"; 5250 drive-strength = <6>; 5251 bias-disable; 5252 }; 5253 5254 qup_spi0_data_clk: qup-spi0-data-clk-state { 5255 /* MISO, MOSI, CLK */ 5256 pins = "gpio0", "gpio1", "gpio2"; 5257 function = "qup0_se0"; 5258 drive-strength = <6>; 5259 bias-disable; 5260 }; 5261 5262 qup_spi1_cs: qup-spi1-cs-state { 5263 pins = "gpio7"; 5264 function = "qup0_se1"; 5265 drive-strength = <6>; 5266 bias-disable; 5267 }; 5268 5269 qup_spi1_data_clk: qup-spi1-data-clk-state { 5270 /* MISO, MOSI, CLK */ 5271 pins = "gpio4", "gpio5", "gpio6"; 5272 function = "qup0_se1"; 5273 drive-strength = <6>; 5274 bias-disable; 5275 }; 5276 5277 qup_spi2_cs: qup-spi2-cs-state { 5278 pins = "gpio11"; 5279 function = "qup0_se2"; 5280 drive-strength = <6>; 5281 bias-disable; 5282 }; 5283 5284 qup_spi2_data_clk: qup-spi2-data-clk-state { 5285 /* MISO, MOSI, CLK */ 5286 pins = "gpio8", "gpio9", "gpio10"; 5287 function = "qup0_se2"; 5288 drive-strength = <6>; 5289 bias-disable; 5290 }; 5291 5292 qup_spi3_cs: qup-spi3-cs-state { 5293 pins = "gpio15"; 5294 function = "qup0_se3"; 5295 drive-strength = <6>; 5296 bias-disable; 5297 }; 5298 5299 qup_spi3_data_clk: qup-spi3-data-clk-state { 5300 /* MISO, MOSI, CLK */ 5301 pins = "gpio12", "gpio13", "gpio14"; 5302 function = "qup0_se3"; 5303 drive-strength = <6>; 5304 bias-disable; 5305 }; 5306 5307 qup_spi4_cs: qup-spi4-cs-state { 5308 pins = "gpio19"; 5309 function = "qup0_se4"; 5310 drive-strength = <6>; 5311 bias-disable; 5312 }; 5313 5314 qup_spi4_data_clk: qup-spi4-data-clk-state { 5315 /* MISO, MOSI, CLK */ 5316 pins = "gpio16", "gpio17", "gpio18"; 5317 function = "qup0_se4"; 5318 drive-strength = <6>; 5319 bias-disable; 5320 }; 5321 5322 qup_spi5_cs: qup-spi5-cs-state { 5323 pins = "gpio23"; 5324 function = "qup0_se5"; 5325 drive-strength = <6>; 5326 bias-disable; 5327 }; 5328 5329 qup_spi5_data_clk: qup-spi5-data-clk-state { 5330 /* MISO, MOSI, CLK */ 5331 pins = "gpio20", "gpio21", "gpio22"; 5332 function = "qup0_se5"; 5333 drive-strength = <6>; 5334 bias-disable; 5335 }; 5336 5337 qup_spi6_cs: qup-spi6-cs-state { 5338 pins = "gpio5"; 5339 function = "qup0_se6"; 5340 drive-strength = <6>; 5341 bias-disable; 5342 }; 5343 5344 qup_spi6_data_clk: qup-spi6-data-clk-state { 5345 /* MISO, MOSI, CLK */ 5346 pins = "gpio6", "gpio7", "gpio4"; 5347 function = "qup0_se6"; 5348 drive-strength = <6>; 5349 bias-disable; 5350 }; 5351 5352 qup_spi7_cs: qup-spi7-cs-state { 5353 pins = "gpio13"; 5354 function = "qup0_se7"; 5355 drive-strength = <6>; 5356 bias-disable; 5357 }; 5358 5359 qup_spi7_data_clk: qup-spi7-data-clk-state { 5360 /* MISO, MOSI, CLK */ 5361 pins = "gpio14", "gpio15", "gpio12"; 5362 function = "qup0_se7"; 5363 drive-strength = <6>; 5364 bias-disable; 5365 }; 5366 5367 qup_spi8_cs: qup-spi8-cs-state { 5368 pins = "gpio35"; 5369 function = "qup1_se0"; 5370 drive-strength = <6>; 5371 bias-disable; 5372 }; 5373 5374 qup_spi8_data_clk: qup-spi8-data-clk-state { 5375 /* MISO, MOSI, CLK */ 5376 pins = "gpio32", "gpio33", "gpio34"; 5377 function = "qup1_se0"; 5378 drive-strength = <6>; 5379 bias-disable; 5380 }; 5381 5382 qup_spi9_cs: qup-spi9-cs-state { 5383 pins = "gpio39"; 5384 function = "qup1_se1"; 5385 drive-strength = <6>; 5386 bias-disable; 5387 }; 5388 5389 qup_spi9_data_clk: qup-spi9-data-clk-state { 5390 /* MISO, MOSI, CLK */ 5391 pins = "gpio36", "gpio37", "gpio38"; 5392 function = "qup1_se1"; 5393 drive-strength = <6>; 5394 bias-disable; 5395 }; 5396 5397 qup_spi10_cs: qup-spi10-cs-state { 5398 pins = "gpio43"; 5399 function = "qup1_se2"; 5400 drive-strength = <6>; 5401 bias-disable; 5402 }; 5403 5404 qup_spi10_data_clk: qup-spi10-data-clk-state { 5405 /* MISO, MOSI, CLK */ 5406 pins = "gpio40", "gpio41", "gpio42"; 5407 function = "qup1_se2"; 5408 drive-strength = <6>; 5409 bias-disable; 5410 }; 5411 5412 qup_spi11_cs: qup-spi11-cs-state { 5413 pins = "gpio47"; 5414 function = "qup1_se3"; 5415 drive-strength = <6>; 5416 bias-disable; 5417 }; 5418 5419 qup_spi11_data_clk: qup-spi11-data-clk-state { 5420 pins = "gpio44", "gpio45", "gpio46"; 5421 function = "qup1_se3"; 5422 drive-strength = <6>; 5423 bias-disable; 5424 }; 5425 5426 qup_spi12_cs: qup-spi12-cs-state { 5427 pins = "gpio51"; 5428 function = "qup1_se4"; 5429 drive-strength = <6>; 5430 bias-disable; 5431 }; 5432 5433 qup_spi12_data_clk: qup-spi12-data-clk-state { 5434 /* MISO, MOSI, CLK */ 5435 pins = "gpio48", "gpio49", "gpio50"; 5436 function = "qup1_se4"; 5437 drive-strength = <6>; 5438 bias-disable; 5439 }; 5440 5441 qup_spi13_cs: qup-spi13-cs-state { 5442 pins = "gpio55"; 5443 function = "qup1_se5"; 5444 drive-strength = <6>; 5445 bias-disable; 5446 }; 5447 5448 qup_spi13_data_clk: qup-spi13-data-clk-state { 5449 /* MISO, MOSI, CLK */ 5450 pins = "gpio52", "gpio53", "gpio54"; 5451 function = "qup1_se5"; 5452 drive-strength = <6>; 5453 bias-disable; 5454 }; 5455 5456 qup_spi14_cs: qup-spi14-cs-state { 5457 pins = "gpio59"; 5458 function = "qup1_se6"; 5459 drive-strength = <6>; 5460 bias-disable; 5461 }; 5462 5463 qup_spi14_data_clk: qup-spi14-data-clk-state { 5464 /* MISO, MOSI, CLK */ 5465 pins = "gpio56", "gpio57", "gpio58"; 5466 function = "qup1_se6"; 5467 drive-strength = <6>; 5468 bias-disable; 5469 }; 5470 5471 qup_spi15_cs: qup-spi15-cs-state { 5472 pins = "gpio53"; 5473 function = "qup1_se7"; 5474 drive-strength = <6>; 5475 bias-disable; 5476 }; 5477 5478 qup_spi15_data_clk: qup-spi15-data-clk-state { 5479 /* MISO, MOSI, CLK */ 5480 pins = "gpio54", "gpio55", "gpio52"; 5481 function = "qup1_se7"; 5482 drive-strength = <6>; 5483 bias-disable; 5484 }; 5485 5486 qup_spi16_cs: qup-spi16-cs-state { 5487 pins = "gpio67"; 5488 function = "qup2_se0"; 5489 drive-strength = <6>; 5490 bias-disable; 5491 }; 5492 5493 qup_spi16_data_clk: qup-spi16-data-clk-state { 5494 /* MISO, MOSI, CLK */ 5495 pins = "gpio64", "gpio65", "gpio66"; 5496 function = "qup2_se0"; 5497 drive-strength = <6>; 5498 bias-disable; 5499 }; 5500 5501 qup_spi17_cs: qup-spi17-cs-state { 5502 pins = "gpio71"; 5503 function = "qup2_se1"; 5504 drive-strength = <6>; 5505 bias-disable; 5506 }; 5507 5508 qup_spi17_data_clk: qup-spi17-data-clk-state { 5509 /* MISO, MOSI, CLK */ 5510 pins = "gpio68", "gpio69", "gpio70"; 5511 function = "qup2_se1"; 5512 drive-strength = <6>; 5513 bias-disable; 5514 }; 5515 5516 qup_spi18_cs: qup-spi18-cs-state { 5517 pins = "gpio75"; 5518 function = "qup2_se2"; 5519 drive-strength = <6>; 5520 bias-disable; 5521 }; 5522 5523 qup_spi18_data_clk: qup-spi18-data-clk-state { 5524 /* MISO, MOSI, CLK */ 5525 pins = "gpio72", "gpio73", "gpio74"; 5526 function = "qup2_se2"; 5527 drive-strength = <6>; 5528 bias-disable; 5529 }; 5530 5531 qup_spi19_cs: qup-spi19-cs-state { 5532 pins = "gpio79"; 5533 function = "qup2_se3"; 5534 drive-strength = <6>; 5535 bias-disable; 5536 }; 5537 5538 qup_spi19_data_clk: qup-spi19-data-clk-state { 5539 /* MISO, MOSI, CLK */ 5540 pins = "gpio76", "gpio77", "gpio78"; 5541 function = "qup2_se3"; 5542 drive-strength = <6>; 5543 bias-disable; 5544 }; 5545 5546 qup_spi20_cs: qup-spi20-cs-state { 5547 pins = "gpio83"; 5548 function = "qup2_se4"; 5549 drive-strength = <6>; 5550 bias-disable; 5551 }; 5552 5553 qup_spi20_data_clk: qup-spi20-data-clk-state { 5554 /* MISO, MOSI, CLK */ 5555 pins = "gpio80", "gpio81", "gpio82"; 5556 function = "qup2_se4"; 5557 drive-strength = <6>; 5558 bias-disable; 5559 }; 5560 5561 qup_spi21_cs: qup-spi21-cs-state { 5562 pins = "gpio87"; 5563 function = "qup2_se5"; 5564 drive-strength = <6>; 5565 bias-disable; 5566 }; 5567 5568 qup_spi21_data_clk: qup-spi21-data-clk-state { 5569 /* MISO, MOSI, CLK */ 5570 pins = "gpio84", "gpio85", "gpio86"; 5571 function = "qup2_se5"; 5572 drive-strength = <6>; 5573 bias-disable; 5574 }; 5575 5576 qup_spi22_cs: qup-spi22-cs-state { 5577 pins = "gpio91"; 5578 function = "qup2_se6"; 5579 drive-strength = <6>; 5580 bias-disable; 5581 }; 5582 5583 qup_spi22_data_clk: qup-spi22-data-clk-state { 5584 /* MISO, MOSI, CLK */ 5585 pins = "gpio88", "gpio89", "gpio90"; 5586 function = "qup2_se6"; 5587 drive-strength = <6>; 5588 bias-disable; 5589 }; 5590 5591 qup_spi23_cs: qup-spi23-cs-state { 5592 pins = "gpio83"; 5593 function = "qup2_se7"; 5594 drive-strength = <6>; 5595 bias-disable; 5596 }; 5597 5598 qup_spi23_data_clk: qup-spi23-data-clk-state { 5599 /* MISO, MOSI, CLK */ 5600 pins = "gpio80", "gpio81", "gpio82"; 5601 function = "qup2_se7"; 5602 drive-strength = <6>; 5603 bias-disable; 5604 }; 5605 5606 qup_uart2_default: qup-uart2-default-state { 5607 tx-pins { 5608 pins = "gpio10"; 5609 function = "qup0_se2"; 5610 drive-strength = <2>; 5611 bias-disable; 5612 }; 5613 5614 rx-pins { 5615 pins = "gpio11"; 5616 function = "qup0_se2"; 5617 drive-strength = <2>; 5618 bias-disable; 5619 }; 5620 }; 5621 5622 qup_uart14_default: qup-uart14-default-state { 5623 cts-pins { 5624 pins = "gpio56"; 5625 function = "qup1_se6"; 5626 drive-strength = <2>; 5627 bias-disable; 5628 }; 5629 5630 rts-pins { 5631 pins = "gpio57"; 5632 function = "qup1_se6"; 5633 drive-strength = <2>; 5634 bias-disable; 5635 }; 5636 5637 tx-pins { 5638 pins = "gpio58"; 5639 function = "qup1_se6"; 5640 drive-strength = <2>; 5641 bias-disable; 5642 }; 5643 5644 rx-pins { 5645 pins = "gpio59"; 5646 function = "qup1_se6"; 5647 drive-strength = <2>; 5648 bias-disable; 5649 }; 5650 }; 5651 5652 qup_uart19_default: qup-uart19-default-state { 5653 cts-pins { 5654 pins = "gpio76"; 5655 function = "qup2_se3"; 5656 drive-strength = <2>; 5657 bias-disable; 5658 }; 5659 5660 rts-pins { 5661 pins = "gpio77"; 5662 function = "qup2_se3"; 5663 drive-strength = <2>; 5664 bias-disable; 5665 }; 5666 5667 tx-pins { 5668 pins = "gpio78"; 5669 function = "qup2_se3"; 5670 drive-strength = <2>; 5671 bias-disable; 5672 }; 5673 5674 rx-pins { 5675 pins = "gpio79"; 5676 function = "qup2_se3"; 5677 drive-strength = <2>; 5678 bias-disable; 5679 }; 5680 }; 5681 5682 qup_uart21_default: qup-uart21-default-state { 5683 tx-pins { 5684 pins = "gpio86"; 5685 function = "qup2_se5"; 5686 drive-strength = <2>; 5687 bias-disable; 5688 }; 5689 5690 rx-pins { 5691 pins = "gpio87"; 5692 function = "qup2_se5"; 5693 drive-strength = <2>; 5694 bias-disable; 5695 }; 5696 }; 5697 5698 qup_uart22_default: qup-uart22-default-state { 5699 tx-pins { 5700 pins = "gpio90"; 5701 function = "qup2_se6"; 5702 drive-strength = <2>; 5703 bias-disable; 5704 }; 5705 5706 rx-pins { 5707 pins = "gpio91"; 5708 function = "qup2_se6"; 5709 drive-strength = <2>; 5710 bias-disable; 5711 }; 5712 }; 5713 }; 5714 5715 apps_smmu: iommu@15000000 { 5716 compatible = "qcom,glymur-smmu-500", 5717 "qcom,smmu-500", 5718 "arm,mmu-500"; 5719 reg = <0x0 0x15000000 0x0 0x100000>; 5720 5721 #iommu-cells = <2>; 5722 #global-interrupts = <1>; 5723 5724 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5738 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5739 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5740 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5741 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5742 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5743 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5744 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5745 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5746 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5747 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5748 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5749 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5751 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5752 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5753 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5754 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5755 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5756 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5757 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5760 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5761 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5762 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5764 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5767 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5768 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5769 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5770 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5771 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5772 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5773 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5774 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5775 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5776 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5777 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5778 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5779 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5780 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5781 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5782 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5783 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5784 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5785 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5786 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5787 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5788 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5789 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5790 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5791 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5792 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5793 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5794 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5795 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5796 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5797 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5798 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5799 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5800 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5801 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5802 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5803 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5804 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5805 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5806 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5807 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5808 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5809 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5810 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5811 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5815 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5816 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5817 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5818 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5820 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5821 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5822 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 5823 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 5824 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 5827 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 5828 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 5829 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 5831 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 5832 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 5833 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 5834 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 5835 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 5836 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 5837 5838 dma-coherent; 5839 }; 5840 5841 pcie_smmu: iommu@15480000 { 5842 compatible = "arm,smmu-v3"; 5843 reg = <0x0 0x15480000 0x0 0x20000>; 5844 interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>, 5845 <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>, 5846 <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>; 5847 interrupt-names = "eventq", "cmdq-sync", "gerror"; 5848 dma-coherent; 5849 #iommu-cells = <1>; 5850 }; 5851 5852 intc: interrupt-controller@17000000 { 5853 compatible = "arm,gic-v3"; 5854 reg = <0x0 0x17000000 0x0 0x10000>, 5855 <0x0 0x17080000 0x0 0x480000>; 5856 5857 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5858 5859 #interrupt-cells = <3>; 5860 interrupt-controller; 5861 5862 #address-cells = <2>; 5863 #size-cells = <2>; 5864 ranges; 5865 5866 gic_its: msi-controller@17040000 { 5867 compatible = "arm,gic-v3-its"; 5868 reg = <0x0 0x17040000 0x0 0x40000>; 5869 5870 msi-controller; 5871 #msi-cells = <1>; 5872 }; 5873 }; 5874 5875 watchdog@17600000 { 5876 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 5877 reg = <0x0 0x17600000 0x0 0x1000>; 5878 clocks = <&sleep_clk>; 5879 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5880 }; 5881 5882 pdp0_mbox: mailbox@17610000 { 5883 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 5884 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 5885 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 5886 #mbox-cells = <1>; 5887 }; 5888 5889 timer@17810000 { 5890 compatible = "arm,armv7-timer-mem"; 5891 reg = <0x0 0x17810000 0x0 0x1000>; 5892 #address-cells = <2>; 5893 #size-cells = <1>; 5894 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 5895 5896 frame@17811000 { 5897 reg = <0x0 0x17811000 0x1000>, 5898 <0x0 0x17812000 0x1000>; 5899 5900 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5902 5903 frame-number = <0>; 5904 }; 5905 5906 frame@17813000 { 5907 reg = <0x0 0x17813000 0x1000>; 5908 5909 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5910 5911 frame-number = <1>; 5912 5913 status = "disabled"; 5914 }; 5915 5916 frame@17815000 { 5917 reg = <0x0 0x17815000 0x1000>; 5918 5919 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5920 5921 frame-number = <2>; 5922 5923 status = "disabled"; 5924 }; 5925 5926 frame@17817000 { 5927 reg = <0x0 0x17817000 0x1000>; 5928 5929 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5930 5931 frame-number = <3>; 5932 5933 status = "disabled"; 5934 }; 5935 5936 frame@17819000 { 5937 reg = <0x0 0x17819000 0x1000>; 5938 5939 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5940 5941 frame-number = <4>; 5942 5943 status = "disabled"; 5944 }; 5945 5946 frame@1781b000 { 5947 reg = <0x0 0x1781b000 0x1000>; 5948 5949 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5950 5951 frame-number = <5>; 5952 5953 status = "disabled"; 5954 }; 5955 5956 frame@1781d000 { 5957 reg = <0x0 0x1781d000 0x1000>; 5958 5959 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5960 5961 frame-number = <6>; 5962 5963 status = "disabled"; 5964 }; 5965 }; 5966 5967 apps_rsc: rsc@18900000 { 5968 compatible = "qcom,rpmh-rsc"; 5969 label = "apps_rsc"; 5970 reg = <0x0 0x18900000 0x0 0x10000>, 5971 <0x0 0x18910000 0x0 0x10000>, 5972 <0x0 0x18920000 0x0 0x10000>; 5973 reg-names = "drv-0", 5974 "drv-1", 5975 "drv-2"; 5976 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5977 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5978 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5979 qcom,tcs-offset = <0xd00>; 5980 qcom,drv-id = <2>; 5981 qcom,tcs-config = <ACTIVE_TCS 2>, 5982 <SLEEP_TCS 3>, 5983 <WAKE_TCS 3>, 5984 <CONTROL_TCS 0>; 5985 power-domains = <&system_pd>; 5986 5987 apps_bcm_voter: bcm-voter { 5988 compatible = "qcom,bcm-voter"; 5989 }; 5990 5991 rpmhcc: clock-controller { 5992 compatible = "qcom,glymur-rpmh-clk"; 5993 5994 clocks = <&xo_board>; 5995 clock-names = "xo"; 5996 5997 #clock-cells = <1>; 5998 }; 5999 6000 rpmhpd: power-controller { 6001 compatible = "qcom,glymur-rpmhpd"; 6002 6003 operating-points-v2 = <&rpmhpd_opp_table>; 6004 6005 #power-domain-cells = <1>; 6006 6007 rpmhpd_opp_table: opp-table { 6008 compatible = "operating-points-v2"; 6009 6010 rpmhpd_opp_ret: opp-16 { 6011 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6012 }; 6013 6014 rpmhpd_opp_min_svs: opp-48 { 6015 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6016 }; 6017 6018 rpmhpd_opp_low_svs_d2: opp-52 { 6019 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 6020 }; 6021 6022 rpmhpd_opp_low_svs_d1: opp-56 { 6023 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 6024 }; 6025 6026 rpmhpd_opp_low_svs_d0: opp-60 { 6027 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 6028 }; 6029 6030 rpmhpd_opp_low_svs: opp-64 { 6031 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6032 }; 6033 6034 rpmhpd_opp_low_svs_l1: opp-80 { 6035 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 6036 }; 6037 6038 rpmhpd_opp_svs: opp-128 { 6039 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6040 }; 6041 6042 rpmhpd_opp_svs_l0: opp-144 { 6043 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 6044 }; 6045 6046 rpmhpd_opp_svs_l1: opp-192 { 6047 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6048 }; 6049 6050 rpmhpd_opp_nom: opp-256 { 6051 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6052 }; 6053 6054 rpmhpd_opp_nom_l1: opp-320 { 6055 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6056 }; 6057 6058 rpmhpd_opp_nom_l2: opp-336 { 6059 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6060 }; 6061 6062 rpmhpd_opp_turbo: opp-384 { 6063 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6064 }; 6065 6066 rpmhpd_opp_turbo_l1: opp-416 { 6067 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6068 }; 6069 }; 6070 }; 6071 }; 6072 6073 nsi_noc: interconnect@1d600000 { 6074 compatible = "qcom,glymur-nsinoc"; 6075 reg = <0x0 0x1d600000 0x0 0x14080>; 6076 qcom,bcm-voters = <&apps_bcm_voter>; 6077 #interconnect-cells = <2>; 6078 }; 6079 6080 oobm_ss_noc: interconnect@1f300000 { 6081 compatible = "qcom,glymur-oobm-ss-noc"; 6082 reg = <0x0 0x1f300000 0x0 0x49a00>; 6083 qcom,bcm-voters = <&apps_bcm_voter>; 6084 #interconnect-cells = <2>; 6085 }; 6086 6087 system-cache-controller@21800000 { 6088 compatible = "qcom,glymur-llcc"; 6089 reg = <0x0 0x21800000 0x0 0x100000>, 6090 <0x0 0x21a00000 0x0 0x100000>, 6091 <0x0 0x21c00000 0x0 0x100000>, 6092 <0x0 0x21e00000 0x0 0x100000>, 6093 <0x0 0x22800000 0x0 0x100000>, 6094 <0x0 0x22a00000 0x0 0x100000>, 6095 <0x0 0x22c00000 0x0 0x100000>, 6096 <0x0 0x22e00000 0x0 0x100000>, 6097 <0x0 0x23800000 0x0 0x100000>, 6098 <0x0 0x23a00000 0x0 0x100000>, 6099 <0x0 0x23c00000 0x0 0x100000>, 6100 <0x0 0x23e00000 0x0 0x100000>, 6101 <0x0 0x20400000 0x0 0x100000>, 6102 <0x0 0x20600000 0x0 0x100000>; 6103 reg-names = "llcc0_base", 6104 "llcc1_base", 6105 "llcc2_base", 6106 "llcc3_base", 6107 "llcc4_base", 6108 "llcc5_base", 6109 "llcc6_base", 6110 "llcc7_base", 6111 "llcc8_base", 6112 "llcc9_base", 6113 "llcc10_base", 6114 "llcc11_base", 6115 "llcc_broadcast_base", 6116 "llcc_broadcast_and_base"; 6117 6118 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 6119 }; 6120 6121 remoteproc_cdsp: remoteproc@32300000 { 6122 compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; 6123 reg = <0x0 0x32300000 0x0 0x10000>; 6124 6125 iommus = <&apps_smmu 0x2400 0x400>; 6126 6127 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6128 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 6129 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 6130 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 6131 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 6132 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 6133 interrupt-names = "wdog", 6134 "fatal", 6135 "ready", 6136 "handover", 6137 "stop-ack", 6138 "shutdown-ack"; 6139 6140 clocks = <&rpmhcc RPMH_CXO_CLK>; 6141 clock-names = "xo"; 6142 6143 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 6144 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6145 6146 power-domains = <&rpmhpd RPMHPD_CX>, 6147 <&rpmhpd RPMHPD_MXC>, 6148 <&rpmhpd RPMHPD_NSP>; 6149 power-domain-names = "cx", 6150 "mxc", 6151 "nsp"; 6152 6153 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 6154 qcom,qmp = <&aoss_qmp>; 6155 qcom,smem-states = <&smp2p_cdsp_out 0>; 6156 qcom,smem-state-names = "stop"; 6157 6158 status = "disabled"; 6159 6160 glink-edge { 6161 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 6162 IPCC_MPROC_SIGNAL_GLINK_QMP 6163 IRQ_TYPE_EDGE_RISING>; 6164 mboxes = <&ipcc IPCC_MPROC_CDSP 6165 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6166 qcom,remote-pid = <5>; 6167 label = "cdsp"; 6168 6169 fastrpc { 6170 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 6171 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6172 label = "cdsp"; 6173 #address-cells = <1>; 6174 #size-cells = <0>; 6175 6176 compute-cb@1 { 6177 compatible = "qcom,fastrpc-compute-cb"; 6178 reg = <1>; 6179 6180 iommus = <&apps_smmu 0x2401 0x440>, 6181 <&apps_smmu 0x1961 0x0>, 6182 <&apps_smmu 0x19c1 0x0>; 6183 dma-coherent; 6184 }; 6185 6186 compute-cb@2 { 6187 compatible = "qcom,fastrpc-compute-cb"; 6188 reg = <2>; 6189 6190 iommus = <&apps_smmu 0x2402 0x440>, 6191 <&apps_smmu 0x1962 0x0>, 6192 <&apps_smmu 0x19c2 0x0>; 6193 dma-coherent; 6194 }; 6195 6196 compute-cb@3 { 6197 compatible = "qcom,fastrpc-compute-cb"; 6198 reg = <3>; 6199 6200 iommus = <&apps_smmu 0x2403 0x440>, 6201 <&apps_smmu 0x1963 0x0>, 6202 <&apps_smmu 0x19c3 0x0>; 6203 dma-coherent; 6204 }; 6205 6206 compute-cb@4 { 6207 compatible = "qcom,fastrpc-compute-cb"; 6208 reg = <4>; 6209 6210 iommus = <&apps_smmu 0x2404 0x440>, 6211 <&apps_smmu 0x1964 0x0>, 6212 <&apps_smmu 0x19c4 0x0>; 6213 dma-coherent; 6214 }; 6215 6216 compute-cb@5 { 6217 compatible = "qcom,fastrpc-compute-cb"; 6218 reg = <5>; 6219 6220 iommus = <&apps_smmu 0x2405 0x440>, 6221 <&apps_smmu 0x1965 0x0>, 6222 <&apps_smmu 0x19c5 0x0>; 6223 dma-coherent; 6224 }; 6225 6226 compute-cb@6 { 6227 compatible = "qcom,fastrpc-compute-cb"; 6228 reg = <6>; 6229 6230 iommus = <&apps_smmu 0x2406 0x440>, 6231 <&apps_smmu 0x1966 0x0>, 6232 <&apps_smmu 0x19c6 0x0>; 6233 dma-coherent; 6234 }; 6235 6236 compute-cb@7 { 6237 compatible = "qcom,fastrpc-compute-cb"; 6238 reg = <7>; 6239 6240 iommus = <&apps_smmu 0x2407 0x440>, 6241 <&apps_smmu 0x1967 0x0>, 6242 <&apps_smmu 0x19c7 0x0>; 6243 dma-coherent; 6244 }; 6245 6246 compute-cb@8 { 6247 compatible = "qcom,fastrpc-compute-cb"; 6248 reg = <8>; 6249 6250 iommus = <&apps_smmu 0x2408 0x440>, 6251 <&apps_smmu 0x1968 0x0>, 6252 <&apps_smmu 0x19c8 0x0>; 6253 dma-coherent; 6254 }; 6255 6256 /* note: compute-cb@9 is secure */ 6257 6258 compute-cb@10 { 6259 compatible = "qcom,fastrpc-compute-cb"; 6260 reg = <10>; 6261 6262 iommus = <&apps_smmu 0x240c 0x440>, 6263 <&apps_smmu 0x196c 0x0>, 6264 <&apps_smmu 0x19cc 0x0>; 6265 dma-coherent; 6266 }; 6267 6268 compute-cb@11 { 6269 compatible = "qcom,fastrpc-compute-cb"; 6270 reg = <11>; 6271 6272 iommus = <&apps_smmu 0x240d 0x440>, 6273 <&apps_smmu 0x196d 0x0>, 6274 <&apps_smmu 0x19cd 0x0>; 6275 dma-coherent; 6276 }; 6277 6278 compute-cb@12 { 6279 compatible = "qcom,fastrpc-compute-cb"; 6280 reg = <12>; 6281 6282 iommus = <&apps_smmu 0x240e 0x440>, 6283 <&apps_smmu 0x196e 0x0>, 6284 <&apps_smmu 0x19ce 0x0>; 6285 dma-coherent; 6286 }; 6287 }; 6288 }; 6289 }; 6290 6291 nsp_noc: interconnect@320c0000 { 6292 compatible = "qcom,glymur-nsp-noc"; 6293 reg = <0x0 0x320c0000 0x0 0x21280>; 6294 qcom,bcm-voters = <&apps_bcm_voter>; 6295 #interconnect-cells = <2>; 6296 }; 6297 6298 imem: sram@81e08600 { 6299 compatible = "mmio-sram"; 6300 reg = <0x0 0x81e08600 0x0 0x300>; 6301 6302 #address-cells = <1>; 6303 #size-cells = <1>; 6304 ranges = <0x0 0x0 0x81e08600 0x300>; 6305 6306 cpu_scp_lpri0: scp-sram-section@0 { 6307 compatible = "arm,scmi-shmem"; 6308 reg = <0x0 0x180>; 6309 }; 6310 6311 cpu_scp_lpri1: scp-sram-section@180 { 6312 compatible = "arm,scmi-shmem"; 6313 reg = <0x180 0x180>; 6314 }; 6315 }; 6316 }; 6317 6318 timer { 6319 compatible = "arm,armv8-timer"; 6320 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6321 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6322 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6323 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 6324 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 6325 }; 6326 6327 thermal_zones: thermal-zones { 6328 aoss-0-thermal { 6329 thermal-sensors = <&tsens0 0>; 6330 6331 trips { 6332 aoss-0-critical { 6333 temperature = <115000>; 6334 hysteresis = <1000>; 6335 type = "critical"; 6336 }; 6337 }; 6338 }; 6339 6340 cpu-0-0-0-thermal { 6341 thermal-sensors = <&tsens0 1>; 6342 6343 trips { 6344 cpu-0-0-0-critical { 6345 temperature = <115000>; 6346 hysteresis = <1000>; 6347 type = "critical"; 6348 }; 6349 }; 6350 }; 6351 6352 cpu-0-0-1-thermal { 6353 thermal-sensors = <&tsens0 2>; 6354 6355 trips { 6356 cpu-0-0-1-critical { 6357 temperature = <115000>; 6358 hysteresis = <1000>; 6359 type = "critical"; 6360 }; 6361 }; 6362 }; 6363 6364 cpu-0-1-0-thermal { 6365 thermal-sensors = <&tsens0 3>; 6366 6367 trips { 6368 cpu-0-1-0-critical { 6369 temperature = <115000>; 6370 hysteresis = <1000>; 6371 type = "critical"; 6372 }; 6373 }; 6374 }; 6375 6376 cpu-0-1-1-thermal { 6377 thermal-sensors = <&tsens0 4>; 6378 6379 trips { 6380 cpu-0-1-1-critical { 6381 temperature = <115000>; 6382 hysteresis = <1000>; 6383 type = "critical"; 6384 }; 6385 }; 6386 }; 6387 6388 cpu-0-2-0-thermal { 6389 thermal-sensors = <&tsens0 5>; 6390 6391 trips { 6392 cpu-0-2-0-critical { 6393 temperature = <115000>; 6394 hysteresis = <1000>; 6395 type = "critical"; 6396 }; 6397 }; 6398 }; 6399 6400 cpu-0-2-1-thermal { 6401 thermal-sensors = <&tsens0 6>; 6402 6403 trips { 6404 cpu-0-2-1-critical { 6405 temperature = <115000>; 6406 hysteresis = <1000>; 6407 type = "critical"; 6408 }; 6409 }; 6410 }; 6411 6412 cpu-0-3-0-thermal { 6413 thermal-sensors = <&tsens0 7>; 6414 6415 trips { 6416 cpu-0-3-0-critical { 6417 temperature = <115000>; 6418 hysteresis = <1000>; 6419 type = "critical"; 6420 }; 6421 }; 6422 }; 6423 6424 cpu-0-3-1-thermal { 6425 thermal-sensors = <&tsens0 8>; 6426 6427 trips { 6428 cpu-0-3-1-critical { 6429 temperature = <115000>; 6430 hysteresis = <1000>; 6431 type = "critical"; 6432 }; 6433 }; 6434 }; 6435 6436 cpu-0-4-0-thermal { 6437 thermal-sensors = <&tsens0 9>; 6438 6439 trips { 6440 cpu-0-4-0-critical { 6441 temperature = <115000>; 6442 hysteresis = <1000>; 6443 type = "critical"; 6444 }; 6445 }; 6446 }; 6447 6448 cpu-0-4-1-thermal { 6449 thermal-sensors = <&tsens0 10>; 6450 6451 trips { 6452 cpu-0-4-1-critical { 6453 temperature = <115000>; 6454 hysteresis = <1000>; 6455 type = "critical"; 6456 }; 6457 }; 6458 }; 6459 6460 cpu-0-5-0-thermal { 6461 thermal-sensors = <&tsens0 11>; 6462 6463 trips { 6464 cpu-0-5-0-critical { 6465 temperature = <115000>; 6466 hysteresis = <1000>; 6467 type = "critical"; 6468 }; 6469 }; 6470 }; 6471 6472 cpu-0-5-1-thermal { 6473 thermal-sensors = <&tsens0 12>; 6474 6475 trips { 6476 cpu-0-5-1-critical { 6477 temperature = <115000>; 6478 hysteresis = <1000>; 6479 type = "critical"; 6480 }; 6481 }; 6482 }; 6483 6484 aoss-1-thermal { 6485 thermal-sensors = <&tsens1 0>; 6486 6487 trips { 6488 aoss-1-critical { 6489 temperature = <115000>; 6490 hysteresis = <1000>; 6491 type = "critical"; 6492 }; 6493 }; 6494 }; 6495 6496 cpullc-0-0-thermal { 6497 thermal-sensors = <&tsens1 1>; 6498 6499 trips { 6500 cpullc-0-0-critical { 6501 temperature = <115000>; 6502 hysteresis = <1000>; 6503 type = "critical"; 6504 }; 6505 }; 6506 }; 6507 6508 cpullc-0-1-thermal { 6509 thermal-sensors = <&tsens1 2>; 6510 6511 trips { 6512 cpullc-0-1-critical { 6513 temperature = <115000>; 6514 hysteresis = <1000>; 6515 type = "critical"; 6516 }; 6517 }; 6518 }; 6519 6520 qmx-0-0-thermal { 6521 thermal-sensors = <&tsens1 3>; 6522 6523 trips { 6524 qmx-0-0-critical { 6525 temperature = <115000>; 6526 hysteresis = <1000>; 6527 type = "critical"; 6528 }; 6529 }; 6530 }; 6531 6532 qmx-0-1-thermal { 6533 thermal-sensors = <&tsens1 4>; 6534 6535 trips { 6536 qmx-0-1-critical { 6537 temperature = <115000>; 6538 hysteresis = <1000>; 6539 type = "critical"; 6540 }; 6541 }; 6542 }; 6543 6544 qmx-0-2-thermal { 6545 thermal-sensors = <&tsens1 5>; 6546 6547 trips { 6548 qmx-0-2-critical { 6549 temperature = <115000>; 6550 hysteresis = <1000>; 6551 type = "critical"; 6552 }; 6553 }; 6554 }; 6555 6556 ddr-0-thermal { 6557 thermal-sensors = <&tsens1 6>; 6558 6559 trips { 6560 ddr-0-critical { 6561 temperature = <115000>; 6562 hysteresis = <1000>; 6563 type = "critical"; 6564 }; 6565 }; 6566 }; 6567 6568 thermal_video_0: video-0-thermal { 6569 thermal-sensors = <&tsens1 7>; 6570 6571 trips { 6572 video-0-critical { 6573 temperature = <115000>; 6574 hysteresis = <1000>; 6575 type = "critical"; 6576 }; 6577 }; 6578 }; 6579 6580 thermal_video_1: video-1-thermal { 6581 thermal-sensors = <&tsens1 8>; 6582 6583 trips { 6584 video-1-critical { 6585 temperature = <115000>; 6586 hysteresis = <1000>; 6587 type = "critical"; 6588 }; 6589 }; 6590 }; 6591 6592 aoss-2-thermal { 6593 thermal-sensors = <&tsens2 0>; 6594 6595 trips { 6596 aoss-2-critical { 6597 temperature = <115000>; 6598 hysteresis = <1000>; 6599 type = "critical"; 6600 }; 6601 }; 6602 }; 6603 6604 cpu-1-0-0-thermal { 6605 thermal-sensors = <&tsens2 1>; 6606 6607 trips { 6608 cpu-1-0-0-critical { 6609 temperature = <115000>; 6610 hysteresis = <1000>; 6611 type = "critical"; 6612 }; 6613 }; 6614 }; 6615 6616 cpu-1-0-1-thermal { 6617 thermal-sensors = <&tsens2 2>; 6618 6619 trips { 6620 cpu-1-0-1-critical { 6621 temperature = <115000>; 6622 hysteresis = <1000>; 6623 type = "critical"; 6624 }; 6625 }; 6626 }; 6627 6628 cpu-1-1-0-thermal { 6629 thermal-sensors = <&tsens2 3>; 6630 6631 trips { 6632 cpu-1-1-0-critical { 6633 temperature = <115000>; 6634 hysteresis = <1000>; 6635 type = "critical"; 6636 }; 6637 }; 6638 }; 6639 6640 cpu-1-1-1-thermal { 6641 thermal-sensors = <&tsens2 4>; 6642 6643 trips { 6644 cpu-1-1-1-critical { 6645 temperature = <115000>; 6646 hysteresis = <1000>; 6647 type = "critical"; 6648 }; 6649 }; 6650 }; 6651 6652 cpu-1-2-0-thermal { 6653 thermal-sensors = <&tsens2 5>; 6654 6655 trips { 6656 cpu-1-2-0-critical { 6657 temperature = <115000>; 6658 hysteresis = <1000>; 6659 type = "critical"; 6660 }; 6661 }; 6662 }; 6663 6664 cpu-1-2-1-thermal { 6665 thermal-sensors = <&tsens2 6>; 6666 6667 trips { 6668 cpu-1-2-1-critical { 6669 temperature = <115000>; 6670 hysteresis = <1000>; 6671 type = "critical"; 6672 }; 6673 }; 6674 }; 6675 6676 cpu-1-3-0-thermal { 6677 thermal-sensors = <&tsens2 7>; 6678 6679 trips { 6680 cpu-1-3-0-critical { 6681 temperature = <115000>; 6682 hysteresis = <1000>; 6683 type = "critical"; 6684 }; 6685 }; 6686 }; 6687 6688 cpu-1-3-1-thermal { 6689 thermal-sensors = <&tsens2 8>; 6690 6691 trips { 6692 cpu-1-3-1-critical { 6693 temperature = <115000>; 6694 hysteresis = <1000>; 6695 type = "critical"; 6696 }; 6697 }; 6698 }; 6699 6700 cpu-1-4-0-thermal { 6701 thermal-sensors = <&tsens2 9>; 6702 6703 trips { 6704 cpu-1-4-0-critical { 6705 temperature = <115000>; 6706 hysteresis = <1000>; 6707 type = "critical"; 6708 }; 6709 }; 6710 }; 6711 6712 cpu-1-4-1-thermal { 6713 thermal-sensors = <&tsens2 10>; 6714 6715 trips { 6716 cpu-1-4-1-critical { 6717 temperature = <115000>; 6718 hysteresis = <1000>; 6719 type = "critical"; 6720 }; 6721 }; 6722 }; 6723 6724 cpu-1-5-0-thermal { 6725 thermal-sensors = <&tsens2 11>; 6726 6727 trips { 6728 cpu-1-5-0-critical { 6729 temperature = <115000>; 6730 hysteresis = <1000>; 6731 type = "critical"; 6732 }; 6733 }; 6734 }; 6735 6736 cpu-1-5-1-thermal { 6737 thermal-sensors = <&tsens2 12>; 6738 6739 trips { 6740 cpu-1-5-1-critical { 6741 temperature = <115000>; 6742 hysteresis = <1000>; 6743 type = "critical"; 6744 }; 6745 }; 6746 }; 6747 6748 aoss-3-thermal { 6749 thermal-sensors = <&tsens3 0>; 6750 6751 trips { 6752 aoss-3-critical { 6753 temperature = <115000>; 6754 hysteresis = <1000>; 6755 type = "critical"; 6756 }; 6757 }; 6758 }; 6759 6760 cpullc-1-0-thermal { 6761 thermal-sensors = <&tsens3 1>; 6762 6763 trips { 6764 cpullc-1-0-critical { 6765 temperature = <115000>; 6766 hysteresis = <1000>; 6767 type = "critical"; 6768 }; 6769 }; 6770 }; 6771 6772 cpullc-1-1-thermal { 6773 thermal-sensors = <&tsens3 2>; 6774 6775 trips { 6776 cpullc-1-1-critical { 6777 temperature = <115000>; 6778 hysteresis = <1000>; 6779 type = "critical"; 6780 }; 6781 }; 6782 }; 6783 6784 qmx-1-0-thermal { 6785 thermal-sensors = <&tsens3 3>; 6786 6787 trips { 6788 qmx-1-0-critical { 6789 temperature = <115000>; 6790 hysteresis = <1000>; 6791 type = "critical"; 6792 }; 6793 }; 6794 }; 6795 6796 qmx-1-1-thermal { 6797 thermal-sensors = <&tsens3 4>; 6798 6799 trips { 6800 qmx-1-1-critical { 6801 temperature = <115000>; 6802 hysteresis = <1000>; 6803 type = "critical"; 6804 }; 6805 }; 6806 }; 6807 6808 qmx-1-2-thermal { 6809 thermal-sensors = <&tsens3 5>; 6810 6811 trips { 6812 qmx-1-2-critical { 6813 temperature = <115000>; 6814 hysteresis = <1000>; 6815 type = "critical"; 6816 }; 6817 }; 6818 }; 6819 6820 qmx-1-3-thermal { 6821 thermal-sensors = <&tsens3 6>; 6822 6823 trips { 6824 qmx-1-3-critical { 6825 temperature = <115000>; 6826 hysteresis = <1000>; 6827 type = "critical"; 6828 }; 6829 }; 6830 }; 6831 6832 qmx-1-4-thermal { 6833 thermal-sensors = <&tsens3 7>; 6834 6835 trips { 6836 qmx-1-4-critical { 6837 temperature = <115000>; 6838 hysteresis = <1000>; 6839 type = "critical"; 6840 }; 6841 }; 6842 }; 6843 6844 aoss-4-thermal { 6845 thermal-sensors = <&tsens4 0>; 6846 6847 trips { 6848 aoss-4-critical { 6849 temperature = <115000>; 6850 hysteresis = <1000>; 6851 type = "critical"; 6852 }; 6853 }; 6854 }; 6855 6856 thermal_cpu_2_0_0: cpu-2-0-0-thermal { 6857 thermal-sensors = <&tsens4 1>; 6858 6859 trips { 6860 cpu-2-0-0-critical { 6861 temperature = <115000>; 6862 hysteresis = <1000>; 6863 type = "critical"; 6864 }; 6865 }; 6866 }; 6867 6868 thermal_cpu_2_0_1: cpu-2-0-1-thermal { 6869 thermal-sensors = <&tsens4 2>; 6870 6871 trips { 6872 cpu-2-0-1-critical { 6873 temperature = <115000>; 6874 hysteresis = <1000>; 6875 type = "critical"; 6876 }; 6877 }; 6878 }; 6879 6880 thermal_cpu_2_1_0: cpu-2-1-0-thermal { 6881 thermal-sensors = <&tsens4 3>; 6882 6883 trips { 6884 cpu-2-1-0-critical { 6885 temperature = <115000>; 6886 hysteresis = <1000>; 6887 type = "critical"; 6888 }; 6889 }; 6890 }; 6891 6892 thermal_cpu_2_1_1: cpu-2-1-1-thermal { 6893 thermal-sensors = <&tsens4 4>; 6894 6895 trips { 6896 cpu-2-1-1-critical { 6897 temperature = <115000>; 6898 hysteresis = <1000>; 6899 type = "critical"; 6900 }; 6901 }; 6902 }; 6903 6904 thermal_cpu_2_2_0: cpu-2-2-0-thermal { 6905 thermal-sensors = <&tsens4 5>; 6906 6907 trips { 6908 cpu-2-2-0-critical { 6909 temperature = <115000>; 6910 hysteresis = <1000>; 6911 type = "critical"; 6912 }; 6913 }; 6914 }; 6915 6916 thermal_cpu_2_2_1: cpu-2-2-1-thermal { 6917 thermal-sensors = <&tsens4 6>; 6918 6919 trips { 6920 cpu-2-2-1-critical { 6921 temperature = <115000>; 6922 hysteresis = <1000>; 6923 type = "critical"; 6924 }; 6925 }; 6926 }; 6927 6928 thermal_cpu_2_3_0: cpu-2-3-0-thermal { 6929 thermal-sensors = <&tsens4 7>; 6930 6931 trips { 6932 cpu-2-3-0-critical { 6933 temperature = <115000>; 6934 hysteresis = <1000>; 6935 type = "critical"; 6936 }; 6937 }; 6938 }; 6939 6940 thermal_cpu_2_3_1: cpu-2-3-1-thermal { 6941 thermal-sensors = <&tsens4 8>; 6942 6943 trips { 6944 cpu-2-3-1-critical { 6945 temperature = <115000>; 6946 hysteresis = <1000>; 6947 type = "critical"; 6948 }; 6949 }; 6950 }; 6951 6952 thermal_cpu_2_4_0: cpu-2-4-0-thermal { 6953 thermal-sensors = <&tsens4 9>; 6954 6955 trips { 6956 cpu-2-4-0-critical { 6957 temperature = <115000>; 6958 hysteresis = <1000>; 6959 type = "critical"; 6960 }; 6961 }; 6962 }; 6963 6964 thermal_cpu_2_4_1: cpu-2-4-1-thermal { 6965 thermal-sensors = <&tsens4 10>; 6966 6967 trips { 6968 cpu-2-4-1-critical { 6969 temperature = <115000>; 6970 hysteresis = <1000>; 6971 type = "critical"; 6972 }; 6973 }; 6974 }; 6975 6976 thermal_cpu_2_5_0: cpu-2-5-0-thermal { 6977 thermal-sensors = <&tsens4 11>; 6978 6979 trips { 6980 cpu-2-5-0-critical { 6981 temperature = <115000>; 6982 hysteresis = <1000>; 6983 type = "critical"; 6984 }; 6985 }; 6986 }; 6987 6988 thermal_cpu_2_5_1: cpu-2-5-1-thermal { 6989 thermal-sensors = <&tsens4 12>; 6990 6991 trips { 6992 cpu-2-5-1-critical { 6993 temperature = <115000>; 6994 hysteresis = <1000>; 6995 type = "critical"; 6996 }; 6997 }; 6998 }; 6999 7000 aoss-5-thermal { 7001 thermal-sensors = <&tsens5 0>; 7002 7003 trips { 7004 aoss-5-critical { 7005 temperature = <115000>; 7006 hysteresis = <1000>; 7007 type = "critical"; 7008 }; 7009 }; 7010 }; 7011 7012 thermal_cpullc_2_0: cpullc-2-0-thermal { 7013 thermal-sensors = <&tsens5 1>; 7014 7015 trips { 7016 cpullc-2-0-critical { 7017 temperature = <115000>; 7018 hysteresis = <1000>; 7019 type = "critical"; 7020 }; 7021 }; 7022 }; 7023 7024 thermal_cpuillc_2_1: cpuillc-2-1-thermal { 7025 thermal-sensors = <&tsens5 2>; 7026 7027 trips { 7028 cpullc-2-1-critical { 7029 temperature = <115000>; 7030 hysteresis = <1000>; 7031 type = "critical"; 7032 }; 7033 }; 7034 }; 7035 7036 thermal_qmx_2_0: qmx-2-0-thermal { 7037 thermal-sensors = <&tsens5 3>; 7038 7039 trips { 7040 qmx-2-0-critical { 7041 temperature = <115000>; 7042 hysteresis = <1000>; 7043 type = "critical"; 7044 }; 7045 }; 7046 }; 7047 7048 thermal_qmx_2_1: qmx-2-1-thermal { 7049 thermal-sensors = <&tsens5 4>; 7050 7051 trips { 7052 qmx-2-1-critical { 7053 temperature = <115000>; 7054 hysteresis = <1000>; 7055 type = "critical"; 7056 }; 7057 }; 7058 }; 7059 7060 thermal_qmx_2_2: qmx-2-2-thermal { 7061 thermal-sensors = <&tsens5 5>; 7062 7063 trips { 7064 qmx-2-2-critical { 7065 temperature = <115000>; 7066 hysteresis = <1000>; 7067 type = "critical"; 7068 }; 7069 }; 7070 }; 7071 7072 thermal_qmx_2_3: qmx-2-3-thermal { 7073 thermal-sensors = <&tsens5 6>; 7074 7075 trips { 7076 qmx-2-3-critical { 7077 temperature = <115000>; 7078 hysteresis = <1000>; 7079 type = "critical"; 7080 }; 7081 }; 7082 }; 7083 7084 thermal_qmx_2_4: qmx-2-4-thermal { 7085 thermal-sensors = <&tsens5 7>; 7086 7087 trips { 7088 qmx-2-4-critical { 7089 temperature = <115000>; 7090 hysteresis = <1000>; 7091 type = "critical"; 7092 }; 7093 }; 7094 }; 7095 7096 thermal_aoss_6: aoss-6-thermal { 7097 thermal-sensors = <&tsens6 0>; 7098 7099 trips { 7100 aoss-6-critical { 7101 temperature = <115000>; 7102 hysteresis = <1000>; 7103 type = "critical"; 7104 }; 7105 }; 7106 }; 7107 7108 thermal_nsphvx_0: nsphvx-0-thermal { 7109 thermal-sensors = <&tsens6 1>; 7110 7111 trips { 7112 nsphvx-0-critical { 7113 temperature = <115000>; 7114 hysteresis = <1000>; 7115 type = "critical"; 7116 }; 7117 }; 7118 }; 7119 7120 thermal_nsphvx_1: nsphvx-1-thermal { 7121 thermal-sensors = <&tsens6 2>; 7122 7123 trips { 7124 nsphvx-1-critical { 7125 temperature = <115000>; 7126 hysteresis = <1000>; 7127 type = "critical"; 7128 }; 7129 }; 7130 }; 7131 7132 thermal_nsphvx_2: nsphvx-2-thermal { 7133 thermal-sensors = <&tsens6 3>; 7134 7135 trips { 7136 nsphvx-2-critical { 7137 temperature = <115000>; 7138 hysteresis = <1000>; 7139 type = "critical"; 7140 }; 7141 }; 7142 }; 7143 7144 thermal_nsphvx_3: nsphvx-3-thermal { 7145 thermal-sensors = <&tsens6 4>; 7146 7147 trips { 7148 nsphvx-3-critical { 7149 temperature = <115000>; 7150 hysteresis = <1000>; 7151 type = "critical"; 7152 }; 7153 }; 7154 }; 7155 7156 thermal_nsphmx_0: nsphmx-0-thermal { 7157 thermal-sensors = <&tsens6 5>; 7158 7159 trips { 7160 nsphmx-0-critical { 7161 temperature = <115000>; 7162 hysteresis = <1000>; 7163 type = "critical"; 7164 }; 7165 }; 7166 }; 7167 7168 thermal_nsphmx_1: nsphmx-1-thermal { 7169 thermal-sensors = <&tsens6 6>; 7170 7171 trips { 7172 nsphmx-1-critical { 7173 temperature = <115000>; 7174 hysteresis = <1000>; 7175 type = "critical"; 7176 }; 7177 }; 7178 }; 7179 7180 thermal_nsphmx_2: nsphmx-2-thermal { 7181 thermal-sensors = <&tsens6 7>; 7182 7183 trips { 7184 nsphmx-2-critical { 7185 temperature = <115000>; 7186 hysteresis = <1000>; 7187 type = "critical"; 7188 }; 7189 }; 7190 }; 7191 7192 thermal_nsphmx_3: nsphmx-3-thermal { 7193 thermal-sensors = <&tsens6 8>; 7194 7195 trips { 7196 nsphmx-3-critical { 7197 temperature = <115000>; 7198 hysteresis = <1000>; 7199 type = "critical"; 7200 }; 7201 }; 7202 }; 7203 7204 thermal_camera_0: camera-0-thermal { 7205 thermal-sensors = <&tsens6 9>; 7206 7207 trips { 7208 camera-0-critical { 7209 temperature = <115000>; 7210 hysteresis = <1000>; 7211 type = "critical"; 7212 }; 7213 }; 7214 }; 7215 7216 thermal_camera_1: camera-1-thermal { 7217 thermal-sensors = <&tsens6 10>; 7218 7219 trips { 7220 camera-1-critical { 7221 temperature = <115000>; 7222 hysteresis = <1000>; 7223 type = "critical"; 7224 }; 7225 }; 7226 }; 7227 7228 thermal_ddr_1: ddr-1-thermal { 7229 thermal-sensors = <&tsens6 11>; 7230 7231 trips { 7232 ddr-1-critical { 7233 temperature = <115000>; 7234 hysteresis = <1000>; 7235 type = "critical"; 7236 }; 7237 }; 7238 }; 7239 7240 thermal_ddr_2: ddr-2-thermal { 7241 thermal-sensors = <&tsens6 12>; 7242 7243 trips { 7244 ddr-2-critical { 7245 temperature = <115000>; 7246 hysteresis = <1000>; 7247 type = "critical"; 7248 }; 7249 }; 7250 }; 7251 7252 thermal_aoss_7: aoss-7-thermal { 7253 thermal-sensors = <&tsens7 0>; 7254 7255 trips { 7256 aoss-7-critical { 7257 temperature = <115000>; 7258 hysteresis = <1000>; 7259 type = "critical"; 7260 }; 7261 }; 7262 }; 7263 7264 thermal_gpu_0_0: gpu-0-0-thermal { 7265 thermal-sensors = <&tsens7 1>; 7266 7267 trips { 7268 trip-point0 { 7269 temperature = <90000>; 7270 hysteresis = <5000>; 7271 type = "hot"; 7272 }; 7273 7274 gpu-0-0-critical { 7275 temperature = <115000>; 7276 hysteresis = <1000>; 7277 type = "critical"; 7278 }; 7279 }; 7280 }; 7281 7282 thermal_gpu_0_1: gpu-0-1-thermal { 7283 thermal-sensors = <&tsens7 2>; 7284 7285 trips { 7286 trip-point0 { 7287 temperature = <90000>; 7288 hysteresis = <5000>; 7289 type = "hot"; 7290 }; 7291 7292 gpu-0-1-critical { 7293 temperature = <115000>; 7294 hysteresis = <1000>; 7295 type = "critical"; 7296 }; 7297 }; 7298 }; 7299 7300 thermal_gpu_0_2: gpu-0-2-thermal { 7301 thermal-sensors = <&tsens7 3>; 7302 7303 trips { 7304 trip-point0 { 7305 temperature = <90000>; 7306 hysteresis = <5000>; 7307 type = "hot"; 7308 }; 7309 7310 gpu-0-2-critical { 7311 temperature = <115000>; 7312 hysteresis = <1000>; 7313 type = "critical"; 7314 }; 7315 }; 7316 }; 7317 7318 thermal_gpu_1_0: gpu-1-0-thermal { 7319 thermal-sensors = <&tsens7 4>; 7320 7321 trips { 7322 trip-point0 { 7323 temperature = <90000>; 7324 hysteresis = <5000>; 7325 type = "hot"; 7326 }; 7327 7328 gpu-1-0-critical { 7329 temperature = <115000>; 7330 hysteresis = <1000>; 7331 type = "critical"; 7332 }; 7333 }; 7334 }; 7335 7336 thermal_gpu_1_1: gpu-1-1-thermal { 7337 thermal-sensors = <&tsens7 5>; 7338 7339 trips { 7340 trip-point0 { 7341 temperature = <90000>; 7342 hysteresis = <5000>; 7343 type = "hot"; 7344 }; 7345 7346 gpu-1-1-critical { 7347 temperature = <115000>; 7348 hysteresis = <1000>; 7349 type = "critical"; 7350 }; 7351 }; 7352 }; 7353 7354 thermal_gpu_1_2: gpu-1-2-thermal { 7355 thermal-sensors = <&tsens7 6>; 7356 7357 trips { 7358 trip-point0 { 7359 temperature = <90000>; 7360 hysteresis = <5000>; 7361 type = "hot"; 7362 }; 7363 7364 gpu-1-2-critical { 7365 temperature = <115000>; 7366 hysteresis = <1000>; 7367 type = "critical"; 7368 }; 7369 }; 7370 }; 7371 7372 thermal_gpu_2_0: gpu-2-0-thermal { 7373 thermal-sensors = <&tsens7 7>; 7374 7375 trips { 7376 trip-point0 { 7377 temperature = <90000>; 7378 hysteresis = <5000>; 7379 type = "hot"; 7380 }; 7381 7382 gpu-2-0-critical { 7383 temperature = <115000>; 7384 hysteresis = <1000>; 7385 type = "critical"; 7386 }; 7387 }; 7388 }; 7389 7390 thermal_gpu_2_1: gpu-2-1-thermal { 7391 thermal-sensors = <&tsens7 8>; 7392 7393 trips { 7394 trip-point0 { 7395 temperature = <90000>; 7396 hysteresis = <5000>; 7397 type = "hot"; 7398 }; 7399 7400 gpu-2-1-critical { 7401 temperature = <115000>; 7402 hysteresis = <1000>; 7403 type = "critical"; 7404 }; 7405 }; 7406 }; 7407 7408 thermal_gpu_2_2: gpu-2-2-thermal { 7409 thermal-sensors = <&tsens7 9>; 7410 7411 trips { 7412 trip-point0 { 7413 temperature = <90000>; 7414 hysteresis = <5000>; 7415 type = "hot"; 7416 }; 7417 7418 gpu-2-2-critical { 7419 temperature = <115000>; 7420 hysteresis = <1000>; 7421 type = "critical"; 7422 }; 7423 }; 7424 }; 7425 7426 thermal_gpu_3_0: gpu-3-0-thermal { 7427 thermal-sensors = <&tsens7 10>; 7428 7429 trips { 7430 trip-point0 { 7431 temperature = <90000>; 7432 hysteresis = <5000>; 7433 type = "hot"; 7434 }; 7435 7436 gpu-3-0-critical { 7437 temperature = <115000>; 7438 hysteresis = <1000>; 7439 type = "critical"; 7440 }; 7441 }; 7442 }; 7443 7444 thermal_gpu_3_1: gpu-3-1-thermal { 7445 thermal-sensors = <&tsens7 11>; 7446 7447 trips { 7448 trip-point0 { 7449 temperature = <90000>; 7450 hysteresis = <5000>; 7451 type = "hot"; 7452 }; 7453 7454 gpu-3-1-critical { 7455 temperature = <115000>; 7456 hysteresis = <1000>; 7457 type = "critical"; 7458 }; 7459 }; 7460 }; 7461 7462 thermal_gpu_3_2: gpu-3-2-thermal { 7463 thermal-sensors = <&tsens7 12>; 7464 7465 trips { 7466 trip-point0 { 7467 temperature = <90000>; 7468 hysteresis = <5000>; 7469 type = "hot"; 7470 }; 7471 7472 gpu-3-2-critical { 7473 temperature = <115000>; 7474 hysteresis = <1000>; 7475 type = "critical"; 7476 }; 7477 }; 7478 }; 7479 7480 thermal_gpuss_0: gpuss-0-thermal { 7481 thermal-sensors = <&tsens7 13>; 7482 7483 trips { 7484 trip-point0 { 7485 temperature = <90000>; 7486 hysteresis = <5000>; 7487 type = "hot"; 7488 }; 7489 7490 gpuss-0-critical { 7491 temperature = <115000>; 7492 hysteresis = <1000>; 7493 type = "critical"; 7494 }; 7495 }; 7496 }; 7497 7498 thermal_gpuss_1: gpuss-1-thermal { 7499 thermal-sensors = <&tsens7 14>; 7500 7501 trips { 7502 trip-point0 { 7503 temperature = <90000>; 7504 hysteresis = <5000>; 7505 type = "hot"; 7506 }; 7507 7508 gpuss-1-critical { 7509 temperature = <115000>; 7510 hysteresis = <1000>; 7511 type = "critical"; 7512 }; 7513 }; 7514 }; 7515 }; 7516}; 7517