1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-dispcc.h> 7#include <dt-bindings/clock/qcom,glymur-gcc.h> 8#include <dt-bindings/clock/qcom,glymur-tcsr.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/spmi/spmi.h> 22 23#include "glymur-ipcc.h" 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "qcom,oryon-2-2"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 40 power-domain-names = "psci", "perf"; 41 next-level-cache = <&l2_0>; 42 43 l2_0: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 }; 48 }; 49 50 cpu1: cpu@100 { 51 device_type = "cpu"; 52 compatible = "qcom,oryon-2-2"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 56 power-domain-names = "psci", "perf"; 57 next-level-cache = <&l2_0>; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "qcom,oryon-2-2"; 63 reg = <0x0 0x200>; 64 enable-method = "psci"; 65 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 66 power-domain-names = "psci", "perf"; 67 next-level-cache = <&l2_0>; 68 }; 69 70 cpu3: cpu@300 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon-2-2"; 73 reg = <0x0 0x300>; 74 enable-method = "psci"; 75 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 76 power-domain-names = "psci", "perf"; 77 next-level-cache = <&l2_0>; 78 }; 79 80 cpu4: cpu@400 { 81 device_type = "cpu"; 82 compatible = "qcom,oryon-2-2"; 83 reg = <0x0 0x400>; 84 enable-method = "psci"; 85 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 86 power-domain-names = "psci", "perf"; 87 next-level-cache = <&l2_0>; 88 }; 89 90 cpu5: cpu@500 { 91 device_type = "cpu"; 92 compatible = "qcom,oryon-2-2"; 93 reg = <0x0 0x500>; 94 enable-method = "psci"; 95 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 96 power-domain-names = "psci", "perf"; 97 next-level-cache = <&l2_0>; 98 }; 99 100 cpu6: cpu@10000 { 101 device_type = "cpu"; 102 compatible = "qcom,oryon-2-1"; 103 reg = <0x0 0x10000>; 104 enable-method = "psci"; 105 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 106 power-domain-names = "psci", "perf"; 107 next-level-cache = <&l2_1>; 108 109 l2_1: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 }; 114 }; 115 116 cpu7: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "qcom,oryon-2-1"; 119 reg = <0x0 0x10100>; 120 enable-method = "psci"; 121 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 122 power-domain-names = "psci", "perf"; 123 next-level-cache = <&l2_1>; 124 }; 125 126 cpu8: cpu@10200 { 127 device_type = "cpu"; 128 compatible = "qcom,oryon-2-1"; 129 reg = <0x0 0x10200>; 130 enable-method = "psci"; 131 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 132 power-domain-names = "psci", "perf"; 133 next-level-cache = <&l2_1>; 134 }; 135 136 cpu9: cpu@10300 { 137 device_type = "cpu"; 138 compatible = "qcom,oryon-2-1"; 139 reg = <0x0 0x10300>; 140 enable-method = "psci"; 141 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 142 power-domain-names = "psci", "perf"; 143 next-level-cache = <&l2_1>; 144 }; 145 146 cpu10: cpu@10400 { 147 device_type = "cpu"; 148 compatible = "qcom,oryon-2-1"; 149 reg = <0x0 0x10400>; 150 enable-method = "psci"; 151 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 152 power-domain-names = "psci", "perf"; 153 next-level-cache = <&l2_1>; 154 }; 155 156 cpu11: cpu@10500 { 157 device_type = "cpu"; 158 compatible = "qcom,oryon-2-1"; 159 reg = <0x0 0x10500>; 160 enable-method = "psci"; 161 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 162 power-domain-names = "psci", "perf"; 163 next-level-cache = <&l2_1>; 164 }; 165 166 cpu12: cpu@20000 { 167 device_type = "cpu"; 168 compatible = "qcom,oryon-2-1"; 169 reg = <0x0 0x20000>; 170 enable-method = "psci"; 171 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 172 power-domain-names = "psci", "perf"; 173 next-level-cache = <&l2_2>; 174 175 l2_2: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 }; 180 }; 181 182 cpu13: cpu@20100 { 183 device_type = "cpu"; 184 compatible = "qcom,oryon-2-1"; 185 reg = <0x0 0x20100>; 186 enable-method = "psci"; 187 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 188 power-domain-names = "psci", "perf"; 189 next-level-cache = <&l2_2>; 190 }; 191 192 cpu14: cpu@20200 { 193 device_type = "cpu"; 194 compatible = "qcom,oryon-2-1"; 195 reg = <0x0 0x20200>; 196 enable-method = "psci"; 197 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 198 power-domain-names = "psci", "perf"; 199 next-level-cache = <&l2_2>; 200 }; 201 202 cpu15: cpu@20300 { 203 device_type = "cpu"; 204 compatible = "qcom,oryon-2-1"; 205 reg = <0x0 0x20300>; 206 enable-method = "psci"; 207 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 208 power-domain-names = "psci", "perf"; 209 next-level-cache = <&l2_2>; 210 }; 211 212 cpu16: cpu@20400 { 213 device_type = "cpu"; 214 compatible = "qcom,oryon-2-1"; 215 reg = <0x0 0x20400>; 216 enable-method = "psci"; 217 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 218 power-domain-names = "psci", "perf"; 219 next-level-cache = <&l2_2>; 220 }; 221 222 cpu17: cpu@20500 { 223 device_type = "cpu"; 224 compatible = "qcom,oryon-2-1"; 225 reg = <0x0 0x20500>; 226 enable-method = "psci"; 227 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 228 power-domain-names = "psci", "perf"; 229 next-level-cache = <&l2_2>; 230 }; 231 232 cpu-map { 233 cluster0 { 234 core0 { 235 cpu = <&cpu0>; 236 }; 237 238 core1 { 239 cpu = <&cpu1>; 240 }; 241 242 core2 { 243 cpu = <&cpu2>; 244 }; 245 246 core3 { 247 cpu = <&cpu3>; 248 }; 249 250 core4 { 251 cpu = <&cpu4>; 252 }; 253 254 core5 { 255 cpu = <&cpu5>; 256 }; 257 }; 258 259 cluster1 { 260 core0 { 261 cpu = <&cpu6>; 262 }; 263 264 core1 { 265 cpu = <&cpu7>; 266 }; 267 268 core2 { 269 cpu = <&cpu8>; 270 }; 271 272 core3 { 273 cpu = <&cpu9>; 274 }; 275 276 core4 { 277 cpu = <&cpu10>; 278 }; 279 280 core5 { 281 cpu = <&cpu11>; 282 }; 283 }; 284 285 cpu_map_cluster2: cluster2 { 286 core0 { 287 cpu = <&cpu12>; 288 }; 289 290 core1 { 291 cpu = <&cpu13>; 292 }; 293 294 core2 { 295 cpu = <&cpu14>; 296 }; 297 298 core3 { 299 cpu = <&cpu15>; 300 }; 301 302 core4 { 303 cpu = <&cpu16>; 304 }; 305 306 core5 { 307 cpu = <&cpu17>; 308 }; 309 }; 310 }; 311 312 idle-states { 313 entry-method = "psci"; 314 315 cpu_c4: cpu-sleep-0 { 316 compatible = "arm,idle-state"; 317 idle-state-name = "ret"; 318 arm,psci-suspend-param = <0x00000004>; 319 entry-latency-us = <180>; 320 exit-latency-us = <320>; 321 min-residency-us = <1000>; 322 }; 323 }; 324 325 domain-idle-states { 326 cluster_cl5: cluster-sleep-0 { 327 compatible = "domain-idle-state"; 328 arm,psci-suspend-param = <0x01000054>; 329 entry-latency-us = <2000>; 330 exit-latency-us = <2000>; 331 min-residency-us = <9000>; 332 }; 333 334 domain_ss3: domain-sleep-0 { 335 compatible = "domain-idle-state"; 336 arm,psci-suspend-param = <0x0200c354>; 337 entry-latency-us = <2800>; 338 exit-latency-us = <4400>; 339 min-residency-us = <10150>; 340 }; 341 }; 342 }; 343 344 firmware { 345 scm: scm { 346 compatible = "qcom,scm-glymur", "qcom,scm"; 347 qcom,dload-mode = <&tcsr 0x4000>; 348 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 349 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 350 }; 351 352 scmi { 353 compatible = "arm,scmi"; 354 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 355 mbox-names = "tx", "rx"; 356 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 357 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 scmi_perf: protocol@13 { 362 reg = <0x13>; 363 #power-domain-cells = <1>; 364 }; 365 }; 366 }; 367 368 clk_virt: interconnect-0 { 369 compatible = "qcom,glymur-clk-virt"; 370 #interconnect-cells = <2>; 371 qcom,bcm-voters = <&apps_bcm_voter>; 372 }; 373 374 mc_virt: interconnect-1 { 375 compatible = "qcom,glymur-mc-virt"; 376 #interconnect-cells = <2>; 377 qcom,bcm-voters = <&apps_bcm_voter>; 378 }; 379 380 pmu { 381 compatible = "arm,armv8-pmuv3"; 382 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 383 }; 384 385 psci { 386 compatible = "arm,psci-1.0"; 387 method = "smc"; 388 389 cpu_pd0: power-domain-cpu0 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster0_pd>; 392 domain-idle-states = <&cpu_c4>; 393 }; 394 395 cpu_pd1: power-domain-cpu1 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster0_pd>; 398 domain-idle-states = <&cpu_c4>; 399 }; 400 401 cpu_pd2: power-domain-cpu2 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster0_pd>; 404 domain-idle-states = <&cpu_c4>; 405 }; 406 407 cpu_pd3: power-domain-cpu3 { 408 #power-domain-cells = <0>; 409 power-domains = <&cluster0_pd>; 410 domain-idle-states = <&cpu_c4>; 411 }; 412 413 cpu_pd4: power-domain-cpu4 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster0_pd>; 416 domain-idle-states = <&cpu_c4>; 417 }; 418 419 cpu_pd5: power-domain-cpu5 { 420 #power-domain-cells = <0>; 421 power-domains = <&cluster0_pd>; 422 domain-idle-states = <&cpu_c4>; 423 }; 424 425 cpu_pd6: power-domain-cpu6 { 426 #power-domain-cells = <0>; 427 power-domains = <&cluster1_pd>; 428 domain-idle-states = <&cpu_c4>; 429 }; 430 431 cpu_pd7: power-domain-cpu7 { 432 #power-domain-cells = <0>; 433 power-domains = <&cluster1_pd>; 434 domain-idle-states = <&cpu_c4>; 435 }; 436 437 cpu_pd8: power-domain-cpu8 { 438 #power-domain-cells = <0>; 439 power-domains = <&cluster1_pd>; 440 domain-idle-states = <&cpu_c4>; 441 }; 442 443 cpu_pd9: power-domain-cpu9 { 444 #power-domain-cells = <0>; 445 power-domains = <&cluster1_pd>; 446 domain-idle-states = <&cpu_c4>; 447 }; 448 449 cpu_pd10: power-domain-cpu10 { 450 #power-domain-cells = <0>; 451 power-domains = <&cluster1_pd>; 452 domain-idle-states = <&cpu_c4>; 453 }; 454 455 cpu_pd11: power-domain-cpu11 { 456 #power-domain-cells = <0>; 457 power-domains = <&cluster1_pd>; 458 domain-idle-states = <&cpu_c4>; 459 }; 460 461 cpu_pd12: power-domain-cpu12 { 462 #power-domain-cells = <0>; 463 power-domains = <&cluster2_pd>; 464 domain-idle-states = <&cpu_c4>; 465 }; 466 467 cpu_pd13: power-domain-cpu13 { 468 #power-domain-cells = <0>; 469 power-domains = <&cluster2_pd>; 470 domain-idle-states = <&cpu_c4>; 471 }; 472 473 cpu_pd14: power-domain-cpu14 { 474 #power-domain-cells = <0>; 475 power-domains = <&cluster2_pd>; 476 domain-idle-states = <&cpu_c4>; 477 }; 478 479 cpu_pd15: power-domain-cpu15 { 480 #power-domain-cells = <0>; 481 power-domains = <&cluster2_pd>; 482 domain-idle-states = <&cpu_c4>; 483 }; 484 485 cpu_pd16: power-domain-cpu16 { 486 #power-domain-cells = <0>; 487 power-domains = <&cluster2_pd>; 488 domain-idle-states = <&cpu_c4>; 489 }; 490 491 cpu_pd17: power-domain-cpu17 { 492 #power-domain-cells = <0>; 493 power-domains = <&cluster2_pd>; 494 domain-idle-states = <&cpu_c4>; 495 }; 496 497 cluster0_pd: power-domain-cpu-cluster0 { 498 #power-domain-cells = <0>; 499 power-domains = <&system_pd>; 500 domain-idle-states = <&cluster_cl5>; 501 }; 502 503 cluster1_pd: power-domain-cpu-cluster1 { 504 #power-domain-cells = <0>; 505 power-domains = <&system_pd>; 506 domain-idle-states = <&cluster_cl5>; 507 }; 508 509 cluster2_pd: power-domain-cpu-cluster2 { 510 #power-domain-cells = <0>; 511 power-domains = <&system_pd>; 512 domain-idle-states = <&cluster_cl5>; 513 }; 514 515 system_pd: power-domain-system { 516 #power-domain-cells = <0>; 517 domain-idle-states = <&domain_ss3>; 518 }; 519 }; 520 521 reserved-memory { 522 #address-cells = <2>; 523 #size-cells = <2>; 524 ranges; 525 526 pdp_mem: pdp@81400000 { 527 reg = <0x0 0x81400000 0x0 0x100000>; 528 no-map; 529 }; 530 531 aop_cmd_db_mem: aop-cmd-db@81c60000 { 532 compatible = "qcom,cmd-db"; 533 reg = <0x0 0x81c60000 0x0 0x20000>; 534 no-map; 535 }; 536 537 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 538 reg = <0x0 0x81e00000 0x0 0x200000>; 539 no-map; 540 }; 541 542 oobdaretag_mem: oobdaretag@86e10000 { 543 reg = <0x0 0x86e10000 0x0 0x360000>; 544 no-map; 545 }; 546 547 oob_secure_mem: oob-secure@87170000 { 548 reg = <0x0 0x87170000 0x0 0xbc0000>; 549 no-map; 550 }; 551 552 oobdtbqc_mem: oobdtbqc@87d30000 { 553 reg = <0x0 0x87d30000 0x0 0x20000>; 554 no-map; 555 }; 556 557 oobdtboem_mem: oobdtboem@87d50000 { 558 reg = <0x0 0x87d50000 0x0 0x20000>; 559 no-map; 560 }; 561 562 oob_nonsecure_mem: oob-nonsecure@87e00000 { 563 reg = <0x0 0x87e00000 0x0 0xc00000>; 564 no-map; 565 }; 566 567 spss_region_mem: spss@88a00000 { 568 reg = <0x0 0x88a00000 0x0 0x400000>; 569 no-map; 570 }; 571 572 soccpdtb_mem: soccpdtb@892e0000 { 573 reg = <0x0 0x892e0000 0x0 0x20000>; 574 no-map; 575 }; 576 577 soccp_mem: soccp@89300000 { 578 reg = <0x0 0x89300000 0x0 0x400000>; 579 no-map; 580 }; 581 582 cvp_mem: cvp@89700000 { 583 reg = <0x0 0x89700000 0x0 0x700000>; 584 no-map; 585 }; 586 587 adspslpi_mem: adspslpi@89e00000 { 588 reg = <0x0 0x89e00000 0x0 0x3a00000>; 589 no-map; 590 }; 591 592 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 593 reg = <0x0 0x8d800000 0x0 0x80000>; 594 no-map; 595 }; 596 597 cdsp_mem: cdsp@8d900000 { 598 reg = <0x0 0x8d900000 0x0 0x4000000>; 599 no-map; 600 }; 601 602 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 603 reg = <0x0 0x91900000 0x0 0x80000>; 604 no-map; 605 }; 606 607 gpu_microcode_mem: gpu-microcode@919fe000 { 608 reg = <0x0 0x919fe000 0x0 0x2000>; 609 no-map; 610 }; 611 612 camera_mem: camera@91a00000 { 613 reg = <0x0 0x91a00000 0x0 0x800000>; 614 no-map; 615 }; 616 617 av1_encoder_mem: av1-encoder@92200000 { 618 reg = <0x0 0x92200000 0x0 0x700000>; 619 no-map; 620 }; 621 622 video_mem: video@92900000 { 623 reg = <0x0 0x92900000 0x0 0xc00000>; 624 no-map; 625 }; 626 627 smem_mem: smem@ffe00000 { 628 compatible = "qcom,smem"; 629 reg = <0x0 0xffe00000 0x0 0x200000>; 630 hwlocks = <&tcsr_mutex 3>; 631 no-map; 632 }; 633 }; 634 635 smp2p-adsp { 636 compatible = "qcom,smp2p"; 637 638 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 639 IPCC_MPROC_SIGNAL_SMP2P 640 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 643 644 qcom,smem = <443>, <429>; 645 qcom,local-pid = <0>; 646 qcom,remote-pid = <2>; 647 648 smp2p_adsp_out: master-kernel { 649 qcom,entry-name = "master-kernel"; 650 #qcom,smem-state-cells = <1>; 651 }; 652 653 smp2p_adsp_in: slave-kernel { 654 qcom,entry-name = "slave-kernel"; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 smp2p-cdsp { 661 compatible = "qcom,smp2p"; 662 663 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 664 IPCC_MPROC_SIGNAL_SMP2P 665 IRQ_TYPE_EDGE_RISING>; 666 667 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 668 669 qcom,smem = <94>, <432>; 670 qcom,local-pid = <0>; 671 qcom,remote-pid = <5>; 672 673 smp2p_cdsp_out: master-kernel { 674 qcom,entry-name = "master-kernel"; 675 #qcom,smem-state-cells = <1>; 676 }; 677 678 smp2p_cdsp_in: slave-kernel { 679 qcom,entry-name = "slave-kernel"; 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 }; 684 685 smp2p-soccp { 686 compatible = "qcom,smp2p"; 687 688 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 689 IPCC_MPROC_SIGNAL_SMP2P 690 IRQ_TYPE_EDGE_RISING>; 691 692 mboxes = <&ipcc IPCC_MPROC_SOCCP 693 IPCC_MPROC_SIGNAL_SMP2P>; 694 695 qcom,smem = <617>, <616>; 696 qcom,local-pid = <0>; 697 qcom,remote-pid = <19>; 698 699 soccp_smp2p_out: master-kernel { 700 qcom,entry-name = "master-kernel"; 701 #qcom,smem-state-cells = <1>; 702 }; 703 704 soccp_smp2p_in: slave-kernel { 705 qcom,entry-name = "slave-kernel"; 706 interrupt-controller; 707 #interrupt-cells = <2>; 708 }; 709 }; 710 711 soc: soc@0 { 712 compatible = "simple-bus"; 713 #address-cells = <2>; 714 #size-cells = <2>; 715 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 716 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 717 718 gcc: clock-controller@100000 { 719 compatible = "qcom,glymur-gcc"; 720 reg = <0x0 0x00100000 0x0 0x1f9000>; 721 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 722 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 723 <&sleep_clk>, /* Sleep */ 724 <0>, /* USB 0 Phy DP0 GMUX */ 725 <0>, /* USB 0 Phy DP1 GMUX */ 726 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 727 <0>, /* USB 0 Phy PIPEGMUX */ 728 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 729 <0>, /* USB 1 Phy DP0 GMUX 2 */ 730 <0>, /* USB 1 Phy DP1 GMUX 2 */ 731 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 732 <0>, /* USB 1 Phy PIPEGMUX */ 733 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 734 <0>, /* USB 2 Phy DP0 GMUX 2 */ 735 <0>, /* USB 2 Phy DP1 GMUX 2 */ 736 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 737 <0>, /* USB 2 Phy PIPEGMUX */ 738 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 739 <0>, /* PCIe 3a */ 740 <&pcie3b_phy>, /* PCIe 3b */ 741 <&pcie4_phy>, /* PCIe 4 */ 742 <&pcie5_phy>, /* PCIe 5 */ 743 <&pcie6_phy>, /* PCIe 6 */ 744 <0>, /* QUSB4 0 PHY RX 0 */ 745 <0>, /* QUSB4 0 PHY RX 1 */ 746 <0>, /* QUSB4 1 PHY RX 0 */ 747 <0>, /* QUSB4 1 PHY RX 1 */ 748 <0>, /* QUSB4 2 PHY RX 0 */ 749 <0>, /* QUSB4 2 PHY RX 1 */ 750 <0>, /* UFS PHY RX Symbol 0 */ 751 <0>, /* UFS PHY RX Symbol 1 */ 752 <0>, /* UFS PHY TX Symbol 0 */ 753 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 754 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 755 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 756 <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, 757 <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, 758 <0>, /* USB4 PHY 0 pcie pipe */ 759 <0>, /* USB4 PHY 0 Max pipe */ 760 <0>, /* USB4 PHY 1 pcie pipe */ 761 <0>, /* USB4 PHY 1 Max pipe */ 762 <0>, /* USB4 PHY 2 pcie */ 763 <0>; /* USB4 PHY 2 Max */ 764 #clock-cells = <1>; 765 #reset-cells = <1>; 766 #power-domain-cells = <1>; 767 }; 768 769 gpi_dma2: dma-controller@800000 { 770 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 771 reg = <0x0 0x00800000 0x0 0x60000>; 772 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 788 dma-channels = <16>; 789 dma-channel-mask = <0x3f>; 790 #dma-cells = <3>; 791 iommus = <&apps_smmu 0xd76 0x0>; 792 }; 793 794 qupv3_2: geniqup@8c0000 { 795 compatible = "qcom,geni-se-qup"; 796 reg = <0x0 0x008c0000 0x0 0x3000>; 797 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 798 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 799 clock-names = "m-ahb", 800 "s-ahb"; 801 iommus = <&apps_smmu 0xd63 0x0>; 802 #address-cells = <2>; 803 #size-cells = <2>; 804 ranges; 805 806 i2c16: i2c@880000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0x0 0x00880000 0x0 0x4000>; 809 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 811 clock-names = "se"; 812 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 813 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 814 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 815 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 816 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 817 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 818 interconnect-names = "qup-core", 819 "qup-config", 820 "qup-memory"; 821 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 822 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 823 dma-names = "tx", 824 "rx"; 825 pinctrl-0 = <&qup_i2c16_data_clk>; 826 pinctrl-names = "default"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 830 status = "disabled"; 831 }; 832 833 spi16: spi@880000 { 834 compatible = "qcom,geni-spi"; 835 reg = <0x0 0x00880000 0x0 0x4000>; 836 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 838 clock-names = "se"; 839 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 840 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 841 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 842 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 843 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 844 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 845 interconnect-names = "qup-core", 846 "qup-config", 847 "qup-memory"; 848 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 849 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 850 dma-names = "tx", 851 "rx"; 852 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 853 pinctrl-names = "default"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 857 status = "disabled"; 858 }; 859 860 i2c17: i2c@884000 { 861 compatible = "qcom,geni-i2c"; 862 reg = <0x0 0x00884000 0x0 0x4000>; 863 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 865 clock-names = "se"; 866 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 867 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 868 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 869 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 870 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 871 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 872 interconnect-names = "qup-core", 873 "qup-config", 874 "qup-memory"; 875 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 876 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 877 dma-names = "tx", 878 "rx"; 879 pinctrl-0 = <&qup_i2c17_data_clk>; 880 pinctrl-names = "default"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 884 status = "disabled"; 885 }; 886 887 spi17: spi@884000 { 888 compatible = "qcom,geni-spi"; 889 reg = <0x0 0x00884000 0x0 0x4000>; 890 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 892 clock-names = "se"; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 894 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 895 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 896 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 897 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 898 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 899 interconnect-names = "qup-core", 900 "qup-config", 901 "qup-memory"; 902 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 903 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 904 dma-names = "tx", 905 "rx"; 906 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 907 pinctrl-names = "default"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 status = "disabled"; 912 }; 913 914 i2c18: i2c@888000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0x0 0x00888000 0x0 0x4000>; 917 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 919 clock-names = "se"; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 924 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", 927 "qup-config", 928 "qup-memory"; 929 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 930 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 931 dma-names = "tx", 932 "rx"; 933 pinctrl-0 = <&qup_i2c18_data_clk>; 934 pinctrl-names = "default"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 938 status = "disabled"; 939 }; 940 941 spi18: spi@888000 { 942 compatible = "qcom,geni-spi"; 943 reg = <0x0 0x00888000 0x0 0x4000>; 944 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 946 clock-names = "se"; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 951 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", 954 "qup-config", 955 "qup-memory"; 956 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 957 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 958 dma-names = "tx", 959 "rx"; 960 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 961 pinctrl-names = "default"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 965 status = "disabled"; 966 }; 967 968 i2c19: i2c@88c000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0x0 0x0088c000 0x0 0x4000>; 971 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 973 clock-names = "se"; 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 975 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 976 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 977 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 978 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 979 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 980 interconnect-names = "qup-core", 981 "qup-config", 982 "qup-memory"; 983 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 984 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 985 dma-names = "tx", 986 "rx"; 987 pinctrl-0 = <&qup_i2c19_data_clk>; 988 pinctrl-names = "default"; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 992 status = "disabled"; 993 }; 994 995 spi19: spi@88c000 { 996 compatible = "qcom,geni-spi"; 997 reg = <0x0 0x0088c000 0x0 0x4000>; 998 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1000 clock-names = "se"; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1002 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1003 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1004 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1005 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1006 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1007 interconnect-names = "qup-core", 1008 "qup-config", 1009 "qup-memory"; 1010 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1011 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1012 dma-names = "tx", 1013 "rx"; 1014 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1015 pinctrl-names = "default"; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 1019 status = "disabled"; 1020 }; 1021 1022 uart19: serial@88c000 { 1023 compatible = "qcom,geni-uart"; 1024 reg = <0x0 0x0088c000 0x0 0x4000>; 1025 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1027 clock-names = "se"; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1030 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 pinctrl-0 = <&qup_uart19_default>; 1035 pinctrl-names = "default"; 1036 1037 status = "disabled"; 1038 }; 1039 1040 i2c20: i2c@890000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0x0 0x00890000 0x0 0x4000>; 1043 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1045 clock-names = "se"; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1047 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1048 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1049 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1050 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1052 interconnect-names = "qup-core", 1053 "qup-config", 1054 "qup-memory"; 1055 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1056 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1057 dma-names = "tx", 1058 "rx"; 1059 pinctrl-0 = <&qup_i2c20_data_clk>; 1060 pinctrl-names = "default"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 1064 status = "disabled"; 1065 }; 1066 1067 spi20: spi@890000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0x0 0x00890000 0x0 0x4000>; 1070 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1072 clock-names = "se"; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1074 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1075 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1076 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1077 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1078 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1079 interconnect-names = "qup-core", 1080 "qup-config", 1081 "qup-memory"; 1082 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1083 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1084 dma-names = "tx", 1085 "rx"; 1086 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1087 pinctrl-names = "default"; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 status = "disabled"; 1092 }; 1093 1094 i2c21: i2c@894000 { 1095 compatible = "qcom,geni-i2c"; 1096 reg = <0x0 0x00894000 0x0 0x4000>; 1097 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1099 clock-names = "se"; 1100 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1101 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1102 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1103 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1104 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1105 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1106 interconnect-names = "qup-core", 1107 "qup-config", 1108 "qup-memory"; 1109 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1110 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1111 dma-names = "tx", 1112 "rx"; 1113 pinctrl-0 = <&qup_i2c21_data_clk>; 1114 pinctrl-names = "default"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 1118 status = "disabled"; 1119 }; 1120 1121 spi21: spi@894000 { 1122 compatible = "qcom,geni-spi"; 1123 reg = <0x0 0x00894000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1126 clock-names = "se"; 1127 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1128 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1129 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1130 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1131 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1132 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", 1134 "qup-config", 1135 "qup-memory"; 1136 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1137 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1138 dma-names = "tx", 1139 "rx"; 1140 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1141 pinctrl-names = "default"; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 1145 status = "disabled"; 1146 }; 1147 1148 uart21: serial@894000 { 1149 compatible = "qcom,geni-debug-uart"; 1150 reg = <0x0 0x00894000 0x0 0x4000>; 1151 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1153 clock-names = "se"; 1154 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1155 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1157 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1158 interconnect-names = "qup-core", 1159 "qup-config"; 1160 pinctrl-0 = <&qup_uart21_default>; 1161 pinctrl-names = "default"; 1162 }; 1163 1164 i2c22: i2c@898000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0x0 0x00898000 0x0 0x4000>; 1167 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1169 clock-names = "se"; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1174 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", 1177 "qup-config", 1178 "qup-memory"; 1179 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1180 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1181 dma-names = "tx", 1182 "rx"; 1183 pinctrl-0 = <&qup_i2c22_data_clk>; 1184 pinctrl-names = "default"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 1188 status = "disabled"; 1189 }; 1190 1191 spi22: spi@898000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0x0 0x00898000 0x0 0x4000>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1196 clock-names = "se"; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1199 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1201 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1203 interconnect-names = "qup-core", 1204 "qup-config", 1205 "qup-memory"; 1206 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1207 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1208 dma-names = "tx", 1209 "rx"; 1210 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1211 pinctrl-names = "default"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 1215 status = "disabled"; 1216 }; 1217 1218 uart22: serial@898000 { 1219 compatible = "qcom,geni-uart"; 1220 reg = <0x0 0x00898000 0x0 0x4000>; 1221 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1223 clock-names = "se"; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1228 interconnect-names = "qup-core", 1229 "qup-config"; 1230 pinctrl-0 = <&qup_uart22_default>; 1231 pinctrl-names = "default"; 1232 1233 status = "disabled"; 1234 }; 1235 1236 i2c23: i2c@89c000 { 1237 compatible = "qcom,geni-i2c"; 1238 reg = <0x0 0x0089c000 0x0 0x4000>; 1239 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1241 clock-names = "se"; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1243 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1244 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1245 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1248 interconnect-names = "qup-core", 1249 "qup-config", 1250 "qup-memory"; 1251 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1252 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1253 dma-names = "tx", 1254 "rx"; 1255 pinctrl-0 = <&qup_i2c23_data_clk>; 1256 pinctrl-names = "default"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 1260 status = "disabled"; 1261 }; 1262 1263 spi23: spi@89c000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0x0 0x0089c000 0x0 0x4000>; 1266 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1268 clock-names = "se"; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1270 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1271 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1272 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1273 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1275 interconnect-names = "qup-core", 1276 "qup-config", 1277 "qup-memory"; 1278 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1279 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1280 dma-names = "tx", 1281 "rx"; 1282 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1283 pinctrl-names = "default"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 status = "disabled"; 1288 }; 1289 }; 1290 1291 gpi_dma1: dma-controller@a00000 { 1292 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1293 reg = <0x0 0x00a00000 0x0 0x60000>; 1294 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1310 dma-channels = <16>; 1311 dma-channel-mask = <0x3f>; 1312 #dma-cells = <3>; 1313 iommus = <&apps_smmu 0xcb6 0x0>; 1314 }; 1315 1316 qupv3_1: geniqup@ac0000 { 1317 compatible = "qcom,geni-se-qup"; 1318 reg = <0x0 0x00ac0000 0x0 0x3000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1320 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1321 clock-names = "m-ahb", 1322 "s-ahb"; 1323 iommus = <&apps_smmu 0xca3 0x0>; 1324 #address-cells = <2>; 1325 #size-cells = <2>; 1326 ranges; 1327 1328 i2c8: i2c@a80000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0x0 0x00a80000 0x0 0x4000>; 1331 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1333 clock-names = "se"; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1336 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1338 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1340 interconnect-names = "qup-core", 1341 "qup-config", 1342 "qup-memory"; 1343 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1344 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1345 dma-names = "tx", 1346 "rx"; 1347 pinctrl-0 = <&qup_i2c8_data_clk>; 1348 pinctrl-names = "default"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 1352 status = "disabled"; 1353 }; 1354 1355 spi8: spi@a80000 { 1356 compatible = "qcom,geni-spi"; 1357 reg = <0x0 0x00a80000 0x0 0x4000>; 1358 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1360 clock-names = "se"; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1362 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1363 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1364 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1365 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1366 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1367 interconnect-names = "qup-core", 1368 "qup-config", 1369 "qup-memory"; 1370 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1371 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1372 dma-names = "tx", 1373 "rx"; 1374 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1375 pinctrl-names = "default"; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 1379 status = "disabled"; 1380 }; 1381 1382 i2c9: i2c@a84000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0x0 0x00a84000 0x0 0x4000>; 1385 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1387 clock-names = "se"; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1389 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1390 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1391 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1392 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1393 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1394 interconnect-names = "qup-core", 1395 "qup-config", 1396 "qup-memory"; 1397 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1398 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1399 dma-names = "tx", 1400 "rx"; 1401 pinctrl-0 = <&qup_i2c9_data_clk>; 1402 pinctrl-names = "default"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 1406 status = "disabled"; 1407 }; 1408 1409 spi9: spi@a84000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0x0 0x00a84000 0x0 0x4000>; 1412 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1414 clock-names = "se"; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1416 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1417 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1418 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1419 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1420 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1421 interconnect-names = "qup-core", 1422 "qup-config", 1423 "qup-memory"; 1424 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1425 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1426 dma-names = "tx", 1427 "rx"; 1428 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1429 pinctrl-names = "default"; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 status = "disabled"; 1434 }; 1435 1436 i2c10: i2c@a88000 { 1437 compatible = "qcom,geni-i2c"; 1438 reg = <0x0 0x00a88000 0x0 0x4000>; 1439 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1441 clock-names = "se"; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1443 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1444 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1445 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1446 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1447 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1448 interconnect-names = "qup-core", 1449 "qup-config", 1450 "qup-memory"; 1451 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1452 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1453 dma-names = "tx", 1454 "rx"; 1455 pinctrl-0 = <&qup_i2c10_data_clk>; 1456 pinctrl-names = "default"; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 1460 status = "disabled"; 1461 }; 1462 1463 spi10: spi@a88000 { 1464 compatible = "qcom,geni-spi"; 1465 reg = <0x0 0x00a88000 0x0 0x4000>; 1466 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1468 clock-names = "se"; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1470 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1471 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1472 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1473 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1474 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1475 interconnect-names = "qup-core", 1476 "qup-config", 1477 "qup-memory"; 1478 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1479 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1480 dma-names = "tx", 1481 "rx"; 1482 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1483 pinctrl-names = "default"; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 1487 status = "disabled"; 1488 }; 1489 1490 i2c11: i2c@a8c000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0x0 0x00a8c000 0x0 0x4000>; 1493 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1495 clock-names = "se"; 1496 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1497 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1498 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1499 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1500 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1501 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1502 interconnect-names = "qup-core", 1503 "qup-config", 1504 "qup-memory"; 1505 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1506 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1507 dma-names = "tx", 1508 "rx"; 1509 pinctrl-0 = <&qup_i2c11_data_clk>; 1510 pinctrl-names = "default"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 1514 status = "disabled"; 1515 }; 1516 1517 spi11: spi@a8c000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0x0 0x00a8c000 0x0 0x4000>; 1520 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1522 clock-names = "se"; 1523 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1524 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1525 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1526 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1527 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1528 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1529 interconnect-names = "qup-core", 1530 "qup-config", 1531 "qup-memory"; 1532 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1533 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1534 dma-names = "tx", 1535 "rx"; 1536 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1537 pinctrl-names = "default"; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 status = "disabled"; 1542 }; 1543 1544 i2c12: i2c@a90000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0x0 0x00a90000 0x0 0x4000>; 1547 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1549 clock-names = "se"; 1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1552 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1554 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1555 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1556 interconnect-names = "qup-core", 1557 "qup-config", 1558 "qup-memory"; 1559 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1560 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1561 dma-names = "tx", 1562 "rx"; 1563 pinctrl-0 = <&qup_i2c12_data_clk>; 1564 pinctrl-names = "default"; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 1568 status = "disabled"; 1569 }; 1570 1571 spi12: spi@a90000 { 1572 compatible = "qcom,geni-spi"; 1573 reg = <0x0 0x00a90000 0x0 0x4000>; 1574 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1576 clock-names = "se"; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1578 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1579 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1580 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1581 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1582 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1583 interconnect-names = "qup-core", 1584 "qup-config", 1585 "qup-memory"; 1586 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1587 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1588 dma-names = "tx", 1589 "rx"; 1590 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1591 pinctrl-names = "default"; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 1595 status = "disabled"; 1596 }; 1597 1598 i2c13: i2c@a94000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0x0 0x00a94000 0x0 0x4000>; 1601 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1603 clock-names = "se"; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1605 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1606 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1607 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1608 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1610 interconnect-names = "qup-core", 1611 "qup-config", 1612 "qup-memory"; 1613 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1614 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1615 dma-names = "tx", 1616 "rx"; 1617 pinctrl-0 = <&qup_i2c13_data_clk>; 1618 pinctrl-names = "default"; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 status = "disabled"; 1623 }; 1624 1625 spi13: spi@a94000 { 1626 compatible = "qcom,geni-spi"; 1627 reg = <0x0 0x00a94000 0x0 0x4000>; 1628 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1630 clock-names = "se"; 1631 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1632 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1633 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1634 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1635 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1636 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1637 interconnect-names = "qup-core", 1638 "qup-config", 1639 "qup-memory"; 1640 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1641 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1642 dma-names = "tx", 1643 "rx"; 1644 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1645 pinctrl-names = "default"; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 i2c14: i2c@a98000 { 1653 compatible = "qcom,geni-i2c"; 1654 reg = <0x0 0x00a98000 0x0 0x4000>; 1655 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1657 clock-names = "se"; 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1659 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1660 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1661 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1662 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1663 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1664 interconnect-names = "qup-core", 1665 "qup-config", 1666 "qup-memory"; 1667 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1668 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1669 dma-names = "tx", 1670 "rx"; 1671 pinctrl-0 = <&qup_i2c14_data_clk>; 1672 pinctrl-names = "default"; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 1676 status = "disabled"; 1677 }; 1678 1679 spi14: spi@a98000 { 1680 compatible = "qcom,geni-spi"; 1681 reg = <0x0 0x00a98000 0x0 0x4000>; 1682 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1684 clock-names = "se"; 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1686 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1687 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1688 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1689 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1690 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1691 interconnect-names = "qup-core", 1692 "qup-config", 1693 "qup-memory"; 1694 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1695 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1696 dma-names = "tx", 1697 "rx"; 1698 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1699 pinctrl-names = "default"; 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 1703 status = "disabled"; 1704 }; 1705 1706 uart14: serial@a98000 { 1707 compatible = "qcom,geni-uart"; 1708 reg = <0x0 0x00a98000 0x0 0x4000>; 1709 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1710 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1711 clock-names = "se"; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1713 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1714 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1715 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1716 interconnect-names = "qup-core", 1717 "qup-config"; 1718 pinctrl-0 = <&qup_uart14_default>; 1719 pinctrl-names = "default"; 1720 1721 status = "disabled"; 1722 }; 1723 1724 i2c15: i2c@a9c000 { 1725 compatible = "qcom,geni-i2c"; 1726 reg = <0x0 0x00a9c000 0x0 0x4000>; 1727 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1728 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1729 clock-names = "se"; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1731 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1732 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1733 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1734 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1735 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1736 interconnect-names = "qup-core", 1737 "qup-config", 1738 "qup-memory"; 1739 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1740 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1741 dma-names = "tx", 1742 "rx"; 1743 pinctrl-0 = <&qup_i2c15_data_clk>; 1744 pinctrl-names = "default"; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 1748 status = "disabled"; 1749 }; 1750 1751 spi15: spi@a9c000 { 1752 compatible = "qcom,geni-spi"; 1753 reg = <0x0 0x00a9c000 0x0 0x4000>; 1754 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1755 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1756 clock-names = "se"; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1758 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1759 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1760 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1761 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1762 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1763 interconnect-names = "qup-core", 1764 "qup-config", 1765 "qup-memory"; 1766 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1767 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1768 dma-names = "tx", 1769 "rx"; 1770 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1771 pinctrl-names = "default"; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 1775 status = "disabled"; 1776 }; 1777 }; 1778 1779 gpi_dma0: dma-controller@b00000 { 1780 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1781 reg = <0x0 0x00b00000 0x0 0x60000>; 1782 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1798 dma-channels = <16>; 1799 dma-channel-mask = <0x3f>; 1800 #dma-cells = <3>; 1801 iommus = <&apps_smmu 0xd36 0x0>; 1802 }; 1803 1804 qupv3_0: geniqup@bc0000 { 1805 compatible = "qcom,geni-se-qup"; 1806 reg = <0x0 0x00bc0000 0x0 0x3000>; 1807 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1808 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1809 clock-names = "m-ahb", 1810 "s-ahb"; 1811 iommus = <&apps_smmu 0xd23 0x0>; 1812 #address-cells = <2>; 1813 #size-cells = <2>; 1814 ranges; 1815 1816 i2c0: i2c@b80000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0x0 0x00b80000 0x0 0x4000>; 1819 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1821 clock-names = "se"; 1822 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1823 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1824 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1825 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1826 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1827 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1828 interconnect-names = "qup-core", 1829 "qup-config", 1830 "qup-memory"; 1831 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1832 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1833 dma-names = "tx", 1834 "rx"; 1835 pinctrl-0 = <&qup_i2c0_data_clk>; 1836 pinctrl-names = "default"; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 1840 status = "disabled"; 1841 }; 1842 1843 spi0: spi@b80000 { 1844 compatible = "qcom,geni-spi"; 1845 reg = <0x0 0x00b80000 0x0 0x4000>; 1846 interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>; 1847 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1848 clock-names = "se"; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1851 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1852 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1853 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", 1856 "qup-config", 1857 "qup-memory"; 1858 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1859 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1860 dma-names = "tx", 1861 "rx"; 1862 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1863 pinctrl-names = "default"; 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 }; 1869 1870 i2c1: i2c@b84000 { 1871 compatible = "qcom,geni-i2c"; 1872 reg = <0x0 0x00b84000 0x0 0x4000>; 1873 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1875 clock-names = "se"; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1877 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1878 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1879 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1880 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1881 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1882 interconnect-names = "qup-core", 1883 "qup-config", 1884 "qup-memory"; 1885 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1886 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1887 dma-names = "tx", 1888 "rx"; 1889 pinctrl-0 = <&qup_i2c1_data_clk>; 1890 pinctrl-names = "default"; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 1894 status = "disabled"; 1895 }; 1896 1897 spi1: spi@b84000 { 1898 compatible = "qcom,geni-spi"; 1899 reg = <0x0 0x00b84000 0x0 0x4000>; 1900 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1901 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1902 clock-names = "se"; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1904 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1905 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1906 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1907 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1908 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1909 interconnect-names = "qup-core", 1910 "qup-config", 1911 "qup-memory"; 1912 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1913 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1914 dma-names = "tx", 1915 "rx"; 1916 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1917 pinctrl-names = "default"; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 1921 status = "disabled"; 1922 }; 1923 1924 i2c2: i2c@b88000 { 1925 compatible = "qcom,geni-i2c"; 1926 reg = <0x0 0x00b88000 0x0 0x4000>; 1927 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1929 clock-names = "se"; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1931 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1932 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1933 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1934 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1935 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1936 interconnect-names = "qup-core", 1937 "qup-config", 1938 "qup-memory"; 1939 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1940 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1941 dma-names = "tx", 1942 "rx"; 1943 pinctrl-0 = <&qup_i2c2_data_clk>; 1944 pinctrl-names = "default"; 1945 #address-cells = <1>; 1946 #size-cells = <0>; 1947 1948 status = "disabled"; 1949 }; 1950 1951 spi2: spi@b88000 { 1952 compatible = "qcom,geni-spi"; 1953 reg = <0x0 0x00b88000 0x0 0x4000>; 1954 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1956 clock-names = "se"; 1957 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1958 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1959 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1960 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1961 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1963 interconnect-names = "qup-core", 1964 "qup-config", 1965 "qup-memory"; 1966 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1967 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1968 dma-names = "tx", 1969 "rx"; 1970 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1971 pinctrl-names = "default"; 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 status = "disabled"; 1976 }; 1977 1978 uart2: serial@b88000 { 1979 compatible = "qcom,geni-uart"; 1980 reg = <0x0 0x00b88000 0x0 0x4000>; 1981 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1982 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1983 clock-names = "se"; 1984 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1985 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1986 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1987 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1988 interconnect-names = "qup-core", 1989 "qup-config"; 1990 pinctrl-0 = <&qup_uart2_default>; 1991 pinctrl-names = "default"; 1992 1993 status = "disabled"; 1994 }; 1995 1996 i2c3: i2c@b8c000 { 1997 compatible = "qcom,geni-i2c"; 1998 reg = <0x0 0x00b8c000 0x0 0x4000>; 1999 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2001 clock-names = "se"; 2002 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2003 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2004 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2005 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2006 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2007 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2008 interconnect-names = "qup-core", 2009 "qup-config", 2010 "qup-memory"; 2011 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2012 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2013 dma-names = "tx", 2014 "rx"; 2015 pinctrl-0 = <&qup_i2c3_data_clk>; 2016 pinctrl-names = "default"; 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 2020 status = "disabled"; 2021 }; 2022 2023 spi3: spi@b8c000 { 2024 compatible = "qcom,geni-spi"; 2025 reg = <0x0 0x00b8c000 0x0 0x4000>; 2026 interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>; 2027 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2028 clock-names = "se"; 2029 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2030 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2031 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2032 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2033 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2034 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2035 interconnect-names = "qup-core", 2036 "qup-config", 2037 "qup-memory"; 2038 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2039 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2040 dma-names = "tx", 2041 "rx"; 2042 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2043 pinctrl-names = "default"; 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 2047 status = "disabled"; 2048 }; 2049 2050 i2c4: i2c@b90000 { 2051 compatible = "qcom,geni-i2c"; 2052 reg = <0x0 0x00b90000 0x0 0x4000>; 2053 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2054 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2055 clock-names = "se"; 2056 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2057 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2058 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2059 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2060 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2062 interconnect-names = "qup-core", 2063 "qup-config", 2064 "qup-memory"; 2065 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2066 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2067 dma-names = "tx", 2068 "rx"; 2069 pinctrl-0 = <&qup_i2c4_data_clk>; 2070 pinctrl-names = "default"; 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 2074 status = "disabled"; 2075 }; 2076 2077 spi4: spi@b90000 { 2078 compatible = "qcom,geni-spi"; 2079 reg = <0x0 0x00b90000 0x0 0x4000>; 2080 interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>; 2081 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2082 clock-names = "se"; 2083 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2084 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2085 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2086 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2087 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2088 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2089 interconnect-names = "qup-core", 2090 "qup-config", 2091 "qup-memory"; 2092 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2093 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2094 dma-names = "tx", 2095 "rx"; 2096 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2097 pinctrl-names = "default"; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 status = "disabled"; 2102 }; 2103 2104 i2c5: i2c@b94000 { 2105 compatible = "qcom,geni-i2c"; 2106 reg = <0x0 0x00b94000 0x0 0x4000>; 2107 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2108 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2109 clock-names = "se"; 2110 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2111 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2112 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2113 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2114 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2115 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2116 interconnect-names = "qup-core", 2117 "qup-config", 2118 "qup-memory"; 2119 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2120 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2121 dma-names = "tx", 2122 "rx"; 2123 pinctrl-0 = <&qup_i2c5_data_clk>; 2124 pinctrl-names = "default"; 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 2128 status = "disabled"; 2129 }; 2130 2131 spi5: spi@b94000 { 2132 compatible = "qcom,geni-spi"; 2133 reg = <0x0 0x00b94000 0x0 0x4000>; 2134 interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>; 2135 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2136 clock-names = "se"; 2137 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2138 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2139 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2140 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2141 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2143 interconnect-names = "qup-core", 2144 "qup-config", 2145 "qup-memory"; 2146 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2147 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2148 dma-names = "tx", 2149 "rx"; 2150 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2151 pinctrl-names = "default"; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 2155 status = "disabled"; 2156 }; 2157 2158 i2c6: i2c@b98000 { 2159 compatible = "qcom,geni-i2c"; 2160 reg = <0x0 0x00b98000 0x0 0x4000>; 2161 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2163 clock-names = "se"; 2164 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2165 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2166 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2167 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2168 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2169 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2170 interconnect-names = "qup-core", 2171 "qup-config", 2172 "qup-memory"; 2173 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2174 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2175 dma-names = "tx", 2176 "rx"; 2177 pinctrl-0 = <&qup_i2c6_data_clk>; 2178 pinctrl-names = "default"; 2179 #address-cells = <1>; 2180 #size-cells = <0>; 2181 2182 status = "disabled"; 2183 }; 2184 2185 spi6: spi@b98000 { 2186 compatible = "qcom,geni-spi"; 2187 reg = <0x0 0x00b98000 0x0 0x4000>; 2188 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2189 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2190 clock-names = "se"; 2191 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2192 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2193 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2194 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2195 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2196 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2197 interconnect-names = "qup-core", 2198 "qup-config", 2199 "qup-memory"; 2200 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2201 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2202 dma-names = "tx", 2203 "rx"; 2204 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2205 pinctrl-names = "default"; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 2209 status = "disabled"; 2210 }; 2211 2212 i2c7: i2c@b9c000 { 2213 compatible = "qcom,geni-i2c"; 2214 reg = <0x0 0x00b9c000 0x0 0x4000>; 2215 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2217 clock-names = "se"; 2218 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2219 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2220 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2221 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2222 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2224 interconnect-names = "qup-core", 2225 "qup-config", 2226 "qup-memory"; 2227 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2228 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2229 dma-names = "tx", 2230 "rx"; 2231 pinctrl-0 = <&qup_i2c7_data_clk>; 2232 pinctrl-names = "default"; 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 2236 status = "disabled"; 2237 }; 2238 2239 spi7: spi@b9c000 { 2240 compatible = "qcom,geni-spi"; 2241 reg = <0x0 0x00b9c000 0x0 0x4000>; 2242 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2243 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2244 clock-names = "se"; 2245 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2246 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2247 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2248 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2249 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2251 interconnect-names = "qup-core", 2252 "qup-config", 2253 "qup-memory"; 2254 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2255 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2256 dma-names = "tx", 2257 "rx"; 2258 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2259 pinctrl-names = "default"; 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 2263 status = "disabled"; 2264 }; 2265 }; 2266 2267 usb_hs_phy: phy@fa0000 { 2268 compatible = "qcom,glymur-m31-eusb2-phy", 2269 "qcom,sm8750-m31-eusb2-phy"; 2270 reg = <0x0 0x00fa0000 0x0 0x154>; 2271 #phy-cells = <0>; 2272 2273 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2274 clock-names = "ref"; 2275 2276 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2277 2278 status = "disabled"; 2279 }; 2280 2281 usb_mp_hsphy0: phy@fa1000 { 2282 compatible = "qcom,glymur-m31-eusb2-phy", 2283 "qcom,sm8750-m31-eusb2-phy"; 2284 2285 reg = <0x0 0x00fa1000 0x0 0x29c>; 2286 #phy-cells = <0>; 2287 2288 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2289 clock-names = "ref"; 2290 2291 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2292 2293 status = "disabled"; 2294 }; 2295 2296 usb_mp_hsphy1: phy@fa2000 { 2297 compatible = "qcom,glymur-m31-eusb2-phy", 2298 "qcom,sm8750-m31-eusb2-phy"; 2299 2300 reg = <0x0 0x00fa2000 0x0 0x29c>; 2301 #phy-cells = <0>; 2302 2303 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2304 clock-names = "ref"; 2305 2306 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2307 2308 status = "disabled"; 2309 }; 2310 2311 usb_mp_qmpphy0: phy@fa3000 { 2312 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2313 reg = <0x0 0x00fa3000 0x0 0x2000>; 2314 2315 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2316 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2317 <&rpmhcc RPMH_CXO_CLK>, 2318 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2319 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2320 clock-names = "aux", 2321 "clkref", 2322 "ref", 2323 "com_aux", 2324 "pipe"; 2325 2326 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2327 2328 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2329 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2330 reset-names = "phy", 2331 "phy_phy"; 2332 2333 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2334 #clock-cells = <0>; 2335 #phy-cells = <0>; 2336 2337 status = "disabled"; 2338 }; 2339 2340 usb_mp_qmpphy1: phy@fa5000 { 2341 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2342 reg = <0x0 0x00fa5000 0x0 0x2000>; 2343 2344 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2345 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2346 <&rpmhcc RPMH_CXO_CLK>, 2347 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2348 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2349 clock-names = "aux", 2350 "clkref", 2351 "ref", 2352 "com_aux", 2353 "pipe"; 2354 2355 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2356 2357 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2358 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2359 reset-names = "phy", 2360 "phy_phy"; 2361 2362 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2363 2364 #clock-cells = <0>; 2365 #phy-cells = <0>; 2366 2367 status = "disabled"; 2368 }; 2369 2370 usb_0_hsphy: phy@fd3000 { 2371 compatible = "qcom,glymur-m31-eusb2-phy", 2372 "qcom,sm8750-m31-eusb2-phy"; 2373 2374 reg = <0x0 0x00fd3000 0x0 0x29c>; 2375 #phy-cells = <0>; 2376 2377 clocks = <&rpmhcc RPMH_CXO_CLK>; 2378 clock-names = "ref"; 2379 2380 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2381 2382 status = "disabled"; 2383 }; 2384 2385 usb_0_qmpphy: phy@fd5000 { 2386 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2387 reg = <0x0 0x00fd5000 0x0 0x8000>; 2388 2389 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2390 <&rpmhcc RPMH_CXO_CLK>, 2391 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2392 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2393 clock-names = "aux", 2394 "ref", 2395 "com_aux", 2396 "usb3_pipe"; 2397 2398 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2399 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2400 2401 reset-names = "phy", 2402 "common"; 2403 2404 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2405 2406 #clock-cells = <1>; 2407 #phy-cells = <1>; 2408 2409 mode-switch; 2410 orientation-switch; 2411 2412 status = "disabled"; 2413 2414 ports { 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 2418 port@0 { 2419 reg = <0>; 2420 2421 usb_0_qmpphy_out: endpoint { 2422 }; 2423 }; 2424 2425 port@1 { 2426 reg = <1>; 2427 2428 usb_0_qmpphy_usb_ss_in: endpoint { 2429 remote-endpoint = <&usb_0_dwc3_ss>; 2430 }; 2431 }; 2432 2433 port@2 { 2434 reg = <2>; 2435 2436 usb_dp_qmpphy_dp_in: endpoint { 2437 }; 2438 }; 2439 }; 2440 }; 2441 2442 usb_1_hsphy: phy@fdd000 { 2443 compatible = "qcom,glymur-m31-eusb2-phy", 2444 "qcom,sm8750-m31-eusb2-phy"; 2445 2446 reg = <0x0 0x00fdd000 0x0 0x29c>; 2447 #phy-cells = <0>; 2448 2449 clocks = <&rpmhcc RPMH_CXO_CLK>; 2450 clock-names = "ref"; 2451 2452 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2453 2454 status = "disabled"; 2455 }; 2456 2457 usb_1_qmpphy: phy@fde000 { 2458 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2459 reg = <0x0 0x00fde000 0x0 0x8000>; 2460 2461 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2462 <&rpmhcc RPMH_CXO_CLK>, 2463 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2464 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, 2465 <&tcsr TCSR_USB4_1_CLKREF_EN>; 2466 clock-names = "aux", 2467 "ref", 2468 "com_aux", 2469 "usb3_pipe", 2470 "clkref"; 2471 2472 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2473 2474 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2475 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2476 reset-names = "phy", 2477 "common"; 2478 2479 #clock-cells = <1>; 2480 #phy-cells = <1>; 2481 2482 mode-switch; 2483 orientation-switch; 2484 2485 status = "disabled"; 2486 2487 ports { 2488 #address-cells = <1>; 2489 #size-cells = <0>; 2490 2491 port@0 { 2492 reg = <0>; 2493 2494 usb_1_qmpphy_out: endpoint { 2495 }; 2496 }; 2497 2498 port@1 { 2499 reg = <1>; 2500 2501 usb_1_qmpphy_usb_ss_in: endpoint { 2502 remote-endpoint = <&usb_1_dwc3_ss>; 2503 }; 2504 }; 2505 2506 port@2 { 2507 reg = <2>; 2508 2509 usb_1_qmpphy_dp_in: endpoint { 2510 }; 2511 }; 2512 }; 2513 }; 2514 2515 2516 /* cluster0 */ 2517 bwmon_cluster0: pmu@100c400 { 2518 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2519 reg = <0x0 0x0100c400 0x0 0x600>; 2520 2521 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2522 2523 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2525 2526 operating-points-v2 = <&cpu_bwmon_opp_table>; 2527 2528 cpu_bwmon_opp_table: opp-table { 2529 compatible = "operating-points-v2"; 2530 2531 opp-0 { 2532 opp-peak-kBps = <800000>; 2533 }; 2534 2535 opp-1 { 2536 opp-peak-kBps = <2188800>; 2537 }; 2538 2539 opp-2 { 2540 opp-peak-kBps = <5414400>; 2541 }; 2542 2543 opp-3 { 2544 opp-peak-kBps = <6220800>; 2545 }; 2546 2547 opp-4 { 2548 opp-peak-kBps = <6835200>; 2549 }; 2550 2551 opp-5 { 2552 opp-peak-kBps = <8371200>; 2553 }; 2554 2555 opp-6 { 2556 opp-peak-kBps = <10944000>; 2557 }; 2558 2559 opp-7 { 2560 opp-peak-kBps = <12748800>; 2561 }; 2562 2563 opp-8 { 2564 opp-peak-kBps = <14745600>; 2565 }; 2566 2567 opp-9 { 2568 opp-peak-kBps = <16896000>; 2569 }; 2570 2571 opp-10 { 2572 opp-peak-kBps = <19046400>; 2573 }; 2574 }; 2575 }; 2576 2577 /* cluster1 */ 2578 bwmon_cluster1: pmu@100d400 { 2579 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2580 reg = <0x0 0x0100d400 0x0 0x600>; 2581 2582 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2583 2584 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2585 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2586 2587 operating-points-v2 = <&cpu_bwmon_opp_table>; 2588 }; 2589 2590 /* cluster2 */ 2591 bwmon_cluster2: pmu@100e400 { 2592 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2593 reg = <0x0 0x0100e400 0x0 0x600>; 2594 2595 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2596 2597 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2598 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2599 2600 operating-points-v2 = <&cpu_bwmon_opp_table>; 2601 }; 2602 cnoc_main: interconnect@1500000 { 2603 compatible = "qcom,glymur-cnoc-main"; 2604 reg = <0x0 0x01500000 0x0 0x17080>; 2605 qcom,bcm-voters = <&apps_bcm_voter>; 2606 #interconnect-cells = <2>; 2607 }; 2608 2609 config_noc: interconnect@1600000 { 2610 compatible = "qcom,glymur-cnoc-cfg"; 2611 reg = <0x0 0x01600000 0x0 0x6600>; 2612 qcom,bcm-voters = <&apps_bcm_voter>; 2613 #interconnect-cells = <2>; 2614 }; 2615 2616 system_noc: interconnect@1680000 { 2617 compatible = "qcom,glymur-system-noc"; 2618 reg = <0x0 0x01680000 0x0 0x1c080>; 2619 qcom,bcm-voters = <&apps_bcm_voter>; 2620 #interconnect-cells = <2>; 2621 }; 2622 2623 pcie_west_anoc: interconnect@16c0000 { 2624 compatible = "qcom,glymur-pcie-west-anoc"; 2625 reg = <0x0 0x016c0000 0x0 0xf580>; 2626 qcom,bcm-voters = <&apps_bcm_voter>; 2627 #interconnect-cells = <2>; 2628 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2629 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2630 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2631 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2632 }; 2633 2634 pcie_east_anoc: interconnect@16d0000 { 2635 compatible = "qcom,glymur-pcie-east-anoc"; 2636 reg = <0x0 0x016d0000 0x0 0xf300>; 2637 qcom,bcm-voters = <&apps_bcm_voter>; 2638 #interconnect-cells = <2>; 2639 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2640 }; 2641 2642 aggre1_noc: interconnect@16e0000 { 2643 compatible = "qcom,glymur-aggre1-noc"; 2644 reg = <0x0 0x016e0000 0x0 0x14400>; 2645 qcom,bcm-voters = <&apps_bcm_voter>; 2646 #interconnect-cells = <2>; 2647 }; 2648 2649 aggre2_noc: interconnect@1720000 { 2650 compatible = "qcom,glymur-aggre2-noc"; 2651 reg = <0x0 0x01720000 0x0 0x14400>; 2652 qcom,bcm-voters = <&apps_bcm_voter>; 2653 #interconnect-cells = <2>; 2654 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2655 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2656 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2657 }; 2658 2659 aggre3_noc: interconnect@1700000 { 2660 compatible = "qcom,glymur-aggre3-noc"; 2661 reg = <0x0 0x01700000 0x0 0x1d400>; 2662 qcom,bcm-voters = <&apps_bcm_voter>; 2663 #interconnect-cells = <2>; 2664 }; 2665 2666 aggre4_noc: interconnect@1740000 { 2667 compatible = "qcom,glymur-aggre4-noc"; 2668 reg = <0x0 0x01740000 0x0 0x14400>; 2669 qcom,bcm-voters = <&apps_bcm_voter>; 2670 #interconnect-cells = <2>; 2671 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2672 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2673 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2674 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2675 }; 2676 2677 mmss_noc: interconnect@1780000 { 2678 compatible = "qcom,glymur-mmss-noc"; 2679 reg = <0x0 0x01780000 0x0 0x5b800>; 2680 qcom,bcm-voters = <&apps_bcm_voter>; 2681 #interconnect-cells = <2>; 2682 }; 2683 2684 pcie_east_slv_noc: interconnect@1900000 { 2685 compatible = "qcom,glymur-pcie-east-slv-noc"; 2686 reg = <0x0 0x01900000 0x0 0xe080>; 2687 qcom,bcm-voters = <&apps_bcm_voter>; 2688 #interconnect-cells = <2>; 2689 }; 2690 2691 pcie_west_slv_noc: interconnect@1920000 { 2692 compatible = "qcom,glymur-pcie-west-slv-noc"; 2693 reg = <0x0 0x01920000 0x0 0xf180>; 2694 qcom,bcm-voters = <&apps_bcm_voter>; 2695 #interconnect-cells = <2>; 2696 }; 2697 2698 pcie4: pci@1bf0000 { 2699 device_type = "pci"; 2700 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2701 reg = <0x0 0x01bf0000 0x0 0x3000>, 2702 <0x0 0x78000000 0x0 0xf20>, 2703 <0x0 0x78000f40 0x0 0xa8>, 2704 <0x0 0x78001000 0x0 0x4000>, 2705 <0x0 0x78005000 0x0 0x100000>, 2706 <0x0 0x01bf3000 0x0 0x1000>; 2707 reg-names = "parf", 2708 "dbi", 2709 "elbi", 2710 "atu", 2711 "config", 2712 "mhi"; 2713 #address-cells = <3>; 2714 #size-cells = <2>; 2715 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2716 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2717 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2718 bus-range = <0x00 0xff>; 2719 2720 dma-coherent; 2721 2722 linux,pci-domain = <4>; 2723 num-lanes = <2>; 2724 2725 operating-points-v2 = <&pcie4_opp_table>; 2726 2727 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2728 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2729 2730 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2731 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2733 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2734 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2735 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2736 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2737 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2738 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2739 interrupt-names = "msi0", 2740 "msi1", 2741 "msi2", 2742 "msi3", 2743 "msi4", 2744 "msi5", 2745 "msi6", 2746 "msi7", 2747 "global"; 2748 2749 #interrupt-cells = <1>; 2750 interrupt-map-mask = <0 0 0 0x7>; 2751 interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, 2752 <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, 2753 <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, 2754 <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; 2755 2756 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2757 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2758 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2759 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2760 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2761 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2762 clock-names = "aux", 2763 "cfg", 2764 "bus_master", 2765 "bus_slave", 2766 "slave_q2a", 2767 "noc_aggr"; 2768 2769 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2770 assigned-clock-rates = <19200000>; 2771 2772 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2773 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2774 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2775 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2776 interconnect-names = "pcie-mem", 2777 "cpu-pcie"; 2778 2779 resets = <&gcc GCC_PCIE_4_BCR>, 2780 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2781 reset-names = "pci", 2782 "link_down"; 2783 2784 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2785 2786 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2787 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2788 2789 status = "disabled"; 2790 2791 pcie4_opp_table: opp-table { 2792 compatible = "operating-points-v2"; 2793 2794 /* GEN 1 x1 */ 2795 opp-2500000-1 { 2796 opp-hz = /bits/ 64 <2500000>; 2797 required-opps = <&rpmhpd_opp_low_svs>; 2798 opp-peak-kBps = <250000 1>; 2799 opp-level = <1>; 2800 }; 2801 2802 /* GEN 1 x2 */ 2803 opp-5000000-1 { 2804 opp-hz = /bits/ 64 <5000000>; 2805 required-opps = <&rpmhpd_opp_low_svs>; 2806 opp-peak-kBps = <500000 1>; 2807 opp-level = <1>; 2808 }; 2809 2810 /* GEN 2 x1 */ 2811 opp-5000000-2 { 2812 opp-hz = /bits/ 64 <5000000>; 2813 required-opps = <&rpmhpd_opp_low_svs>; 2814 opp-peak-kBps = <500000 1>; 2815 opp-level = <2>; 2816 }; 2817 2818 /* GEN 2 x2 */ 2819 opp-10000000-2 { 2820 opp-hz = /bits/ 64 <10000000>; 2821 required-opps = <&rpmhpd_opp_low_svs>; 2822 opp-peak-kBps = <1000000 1>; 2823 opp-level = <2>; 2824 }; 2825 2826 /* GEN 3 x1 */ 2827 opp-8000000-3 { 2828 opp-hz = /bits/ 64 <8000000>; 2829 required-opps = <&rpmhpd_opp_low_svs>; 2830 opp-peak-kBps = <984500 1>; 2831 opp-level = <3>; 2832 }; 2833 2834 /* GEN 3 x2 */ 2835 opp-16000000-3 { 2836 opp-hz = /bits/ 64 <16000000>; 2837 required-opps = <&rpmhpd_opp_low_svs>; 2838 opp-peak-kBps = <1969000 1>; 2839 opp-level = <3>; 2840 }; 2841 2842 /* GEN 4 x1 */ 2843 opp-16000000-4 { 2844 opp-hz = /bits/ 64 <16000000>; 2845 required-opps = <&rpmhpd_opp_low_svs>; 2846 opp-peak-kBps = <1969000 1>; 2847 opp-level = <4>; 2848 }; 2849 2850 /* GEN 4 x2 */ 2851 opp-32000000-4 { 2852 opp-hz = /bits/ 64 <32000000>; 2853 required-opps = <&rpmhpd_opp_low_svs>; 2854 opp-peak-kBps = <3938000 1>; 2855 opp-level = <4>; 2856 }; 2857 2858 }; 2859 2860 pcie4_port0: pcie@0 { 2861 device_type = "pci"; 2862 reg = <0x0 0x0 0x0 0x0 0x0>; 2863 bus-range = <0x01 0xff>; 2864 2865 phys = <&pcie4_phy>; 2866 2867 #address-cells = <3>; 2868 #size-cells = <2>; 2869 ranges; 2870 }; 2871 }; 2872 2873 pcie4_phy: phy@1bf6000 { 2874 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 2875 reg = <0x0 0x01bf6000 0x0 0x2000>; 2876 2877 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 2878 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2879 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 2880 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2881 <&gcc GCC_PCIE_4_PIPE_CLK>, 2882 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 2883 clock-names = "aux", 2884 "cfg_ahb", 2885 "ref", 2886 "rchng", 2887 "pipe", 2888 "pipediv2"; 2889 2890 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 2891 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 2892 reset-names = "phy", 2893 "phy_nocsr"; 2894 2895 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2896 assigned-clock-rates = <100000000>; 2897 2898 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2899 2900 #clock-cells = <0>; 2901 clock-output-names = "pcie4_pipe_clk"; 2902 2903 #phy-cells = <0>; 2904 2905 status = "disabled"; 2906 }; 2907 2908 pcie5: pci@1b40000 { 2909 device_type = "pci"; 2910 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2911 reg = <0x0 0x01b40000 0x0 0x3000>, 2912 <0x0 0x7a000000 0x0 0xf20>, 2913 <0x0 0x7a000f40 0x0 0xa8>, 2914 <0x0 0x7a001000 0x0 0x4000>, 2915 <0x0 0x7a100000 0x0 0x100000>, 2916 <0x0 0x01b43000 0x0 0x1000>; 2917 reg-names = "parf", 2918 "dbi", 2919 "elbi", 2920 "atu", 2921 "config", 2922 "mhi"; 2923 #address-cells = <3>; 2924 #size-cells = <2>; 2925 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 2926 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 2927 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 2928 bus-range = <0x00 0xff>; 2929 2930 dma-coherent; 2931 2932 linux,pci-domain = <5>; 2933 num-lanes = <4>; 2934 2935 operating-points-v2 = <&pcie5_opp_table>; 2936 2937 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 2938 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 2939 2940 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 2949 interrupt-names = "msi0", 2950 "msi1", 2951 "msi2", 2952 "msi3", 2953 "msi4", 2954 "msi5", 2955 "msi6", 2956 "msi7", 2957 "global"; 2958 2959 #interrupt-cells = <1>; 2960 interrupt-map-mask = <0 0 0 0x7>; 2961 interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, 2962 <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, 2963 <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, 2964 <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; 2965 2966 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 2967 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 2968 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 2969 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 2970 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 2971 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2972 clock-names = "aux", 2973 "cfg", 2974 "bus_master", 2975 "bus_slave", 2976 "slave_q2a", 2977 "noc_aggr"; 2978 2979 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 2980 assigned-clock-rates = <19200000>; 2981 2982 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 2983 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2984 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2985 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 2986 interconnect-names = "pcie-mem", 2987 "cpu-pcie"; 2988 2989 resets = <&gcc GCC_PCIE_5_BCR>, 2990 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 2991 reset-names = "pci", 2992 "link_down"; 2993 2994 power-domains = <&gcc GCC_PCIE_5_GDSC>; 2995 2996 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2997 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2998 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2999 3000 status = "disabled"; 3001 3002 pcie5_opp_table: opp-table { 3003 compatible = "operating-points-v2"; 3004 3005 /* GEN 1 x1 */ 3006 opp-2500000-1 { 3007 opp-hz = /bits/ 64 <2500000>; 3008 required-opps = <&rpmhpd_opp_low_svs>; 3009 opp-peak-kBps = <250000 1>; 3010 opp-level = <1>; 3011 }; 3012 3013 /* GEN 1 x2 */ 3014 opp-5000000-1 { 3015 opp-hz = /bits/ 64 <5000000>; 3016 required-opps = <&rpmhpd_opp_low_svs>; 3017 opp-peak-kBps = <500000 1>; 3018 opp-level = <1>; 3019 }; 3020 3021 /* GEN 1 x4 */ 3022 opp-10000000-1 { 3023 opp-hz = /bits/ 64 <10000000>; 3024 required-opps = <&rpmhpd_opp_low_svs>; 3025 opp-peak-kBps = <1000000 1>; 3026 opp-level = <1>; 3027 }; 3028 3029 /* GEN 2 x1 */ 3030 opp-5000000-2 { 3031 opp-hz = /bits/ 64 <5000000>; 3032 required-opps = <&rpmhpd_opp_low_svs>; 3033 opp-peak-kBps = <500000 1>; 3034 opp-level = <2>; 3035 }; 3036 3037 /* GEN 2 x2 */ 3038 opp-10000000-2 { 3039 opp-hz = /bits/ 64 <10000000>; 3040 required-opps = <&rpmhpd_opp_low_svs>; 3041 opp-peak-kBps = <1000000 1>; 3042 opp-level = <2>; 3043 }; 3044 3045 /* GEN 2 x4 */ 3046 opp-20000000-2 { 3047 opp-hz = /bits/ 64 <20000000>; 3048 required-opps = <&rpmhpd_opp_low_svs>; 3049 opp-peak-kBps = <2000000 1>; 3050 opp-level = <2>; 3051 }; 3052 3053 /* GEN 3 x1 */ 3054 opp-8000000-3 { 3055 opp-hz = /bits/ 64 <8000000>; 3056 required-opps = <&rpmhpd_opp_low_svs>; 3057 opp-peak-kBps = <984500 1>; 3058 opp-level = <3>; 3059 }; 3060 3061 /* GEN 3 x2 */ 3062 opp-16000000-3 { 3063 opp-hz = /bits/ 64 <16000000>; 3064 required-opps = <&rpmhpd_opp_low_svs>; 3065 opp-peak-kBps = <1969000 1>; 3066 opp-level = <3>; 3067 }; 3068 3069 /* GEN 3 x4 */ 3070 opp-32000000-3 { 3071 opp-hz = /bits/ 64 <32000000>; 3072 required-opps = <&rpmhpd_opp_low_svs>; 3073 opp-peak-kBps = <3938000 1>; 3074 opp-level = <3>; 3075 }; 3076 3077 /* GEN 4 x1 */ 3078 opp-16000000-4 { 3079 opp-hz = /bits/ 64 <16000000>; 3080 required-opps = <&rpmhpd_opp_svs>; 3081 opp-peak-kBps = <1969000 1>; 3082 opp-level = <4>; 3083 }; 3084 3085 /* GEN 4 x2 */ 3086 opp-32000000-4 { 3087 opp-hz = /bits/ 64 <32000000>; 3088 required-opps = <&rpmhpd_opp_svs>; 3089 opp-peak-kBps = <3938000 1>; 3090 opp-level = <4>; 3091 }; 3092 3093 /* GEN 4 x4 */ 3094 opp-64000000-4 { 3095 opp-hz = /bits/ 64 <64000000>; 3096 required-opps = <&rpmhpd_opp_svs>; 3097 opp-peak-kBps = <7876000 1>; 3098 opp-level = <4>; 3099 }; 3100 3101 /* GEN 5 x1 */ 3102 opp-32000000-5 { 3103 opp-hz = /bits/ 64 <32000000>; 3104 required-opps = <&rpmhpd_opp_nom>; 3105 opp-peak-kBps = <3938000 1>; 3106 opp-level = <5>; 3107 }; 3108 3109 /* GEN 5 x2 */ 3110 opp-64000000-5 { 3111 opp-hz = /bits/ 64 <64000000>; 3112 required-opps = <&rpmhpd_opp_nom>; 3113 opp-peak-kBps = <7876000 1>; 3114 opp-level = <5>; 3115 }; 3116 3117 /* GEN 5 x4 */ 3118 opp-128000000-5 { 3119 opp-hz = /bits/ 64 <128000000>; 3120 required-opps = <&rpmhpd_opp_nom>; 3121 opp-peak-kBps = <15753000 1>; 3122 opp-level = <5>; 3123 }; 3124 }; 3125 3126 pcie5_port0: pcie@0 { 3127 device_type = "pci"; 3128 reg = <0x0 0x0 0x0 0x0 0x0>; 3129 bus-range = <0x01 0xff>; 3130 3131 phys = <&pcie5_phy>; 3132 3133 #address-cells = <3>; 3134 #size-cells = <2>; 3135 ranges; 3136 }; 3137 }; 3138 3139 pcie5_phy: phy@1b50000 { 3140 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3141 reg = <0x0 0x01b50000 0x0 0x10000>; 3142 3143 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3144 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3145 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3146 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3147 <&gcc GCC_PCIE_5_PIPE_CLK>, 3148 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3149 clock-names = "aux", 3150 "cfg_ahb", 3151 "ref", 3152 "rchng", 3153 "pipe", 3154 "pipediv2"; 3155 3156 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3157 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3158 reset-names = "phy", 3159 "phy_nocsr"; 3160 3161 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3162 assigned-clock-rates = <100000000>; 3163 3164 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3165 3166 #clock-cells = <0>; 3167 clock-output-names = "pcie5_pipe_clk"; 3168 3169 #phy-cells = <0>; 3170 3171 status = "disabled"; 3172 }; 3173 3174 pcie6: pci@1c00000 { 3175 device_type = "pci"; 3176 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3177 reg = <0x0 0x01c00000 0x0 0x3000>, 3178 <0x0 0x7e000000 0x0 0xf20>, 3179 <0x0 0x7e000f40 0x0 0xa8>, 3180 <0x0 0x7e001000 0x0 0x4000>, 3181 <0x0 0x7e100000 0x0 0x100000>, 3182 <0x0 0x01c03000 0x0 0x1000>; 3183 reg-names = "parf", 3184 "dbi", 3185 "elbi", 3186 "atu", 3187 "config", 3188 "mhi"; 3189 #address-cells = <3>; 3190 #size-cells = <2>; 3191 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3192 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3193 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3194 bus-range = <0x00 0xff>; 3195 3196 dma-coherent; 3197 3198 linux,pci-domain = <6>; 3199 num-lanes = <2>; 3200 3201 operating-points-v2 = <&pcie6_opp_table>; 3202 3203 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3204 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3205 3206 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3207 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3208 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3212 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3215 interrupt-names = "msi0", 3216 "msi1", 3217 "msi2", 3218 "msi3", 3219 "msi4", 3220 "msi5", 3221 "msi6", 3222 "msi7", 3223 "global"; 3224 3225 #interrupt-cells = <1>; 3226 interrupt-map-mask = <0 0 0 0x7>; 3227 interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, 3228 <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, 3229 <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, 3230 <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; 3231 3232 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3233 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3234 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3235 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3236 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3237 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3238 clock-names = "aux", 3239 "cfg", 3240 "bus_master", 3241 "bus_slave", 3242 "slave_q2a", 3243 "noc_aggr"; 3244 3245 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3246 assigned-clock-rates = <19200000>; 3247 3248 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3249 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3250 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3251 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3252 interconnect-names = "pcie-mem", 3253 "cpu-pcie"; 3254 3255 resets = <&gcc GCC_PCIE_6_BCR>, 3256 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3257 reset-names = "pci", 3258 "link_down"; 3259 3260 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3261 3262 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3263 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3264 3265 status = "disabled"; 3266 3267 pcie6_opp_table: opp-table { 3268 compatible = "operating-points-v2"; 3269 3270 /* GEN 1 x1 */ 3271 opp-2500000-1 { 3272 opp-hz = /bits/ 64 <2500000>; 3273 required-opps = <&rpmhpd_opp_low_svs>; 3274 opp-peak-kBps = <250000 1>; 3275 opp-level = <1>; 3276 }; 3277 3278 /* GEN 1 x2 */ 3279 opp-5000000-1 { 3280 opp-hz = /bits/ 64 <5000000>; 3281 required-opps = <&rpmhpd_opp_low_svs>; 3282 opp-peak-kBps = <500000 1>; 3283 opp-level = <1>; 3284 }; 3285 3286 /* GEN 2 x1 */ 3287 opp-5000000-2 { 3288 opp-hz = /bits/ 64 <5000000>; 3289 required-opps = <&rpmhpd_opp_low_svs>; 3290 opp-peak-kBps = <500000 1>; 3291 opp-level = <2>; 3292 }; 3293 3294 /* GEN 2 x2 */ 3295 opp-10000000-2 { 3296 opp-hz = /bits/ 64 <10000000>; 3297 required-opps = <&rpmhpd_opp_low_svs>; 3298 opp-peak-kBps = <1000000 1>; 3299 opp-level = <2>; 3300 }; 3301 3302 /* GEN 3 x1 */ 3303 opp-8000000-3 { 3304 opp-hz = /bits/ 64 <8000000>; 3305 required-opps = <&rpmhpd_opp_low_svs>; 3306 opp-peak-kBps = <984500 1>; 3307 opp-level = <3>; 3308 }; 3309 3310 /* GEN 3 x2 */ 3311 opp-16000000-3 { 3312 opp-hz = /bits/ 64 <16000000>; 3313 required-opps = <&rpmhpd_opp_low_svs>; 3314 opp-peak-kBps = <1969000 1>; 3315 opp-level = <3>; 3316 }; 3317 3318 /* GEN 4 x1 */ 3319 opp-16000000-4 { 3320 opp-hz = /bits/ 64 <16000000>; 3321 required-opps = <&rpmhpd_opp_low_svs>; 3322 opp-peak-kBps = <1969000 1>; 3323 opp-level = <4>; 3324 }; 3325 3326 /* GEN 4 x2 */ 3327 opp-32000000-4 { 3328 opp-hz = /bits/ 64 <32000000>; 3329 required-opps = <&rpmhpd_opp_low_svs>; 3330 opp-peak-kBps = <3938000 1>; 3331 opp-level = <4>; 3332 }; 3333 3334 }; 3335 3336 pcie6_port0: pcie@0 { 3337 device_type = "pci"; 3338 reg = <0x0 0x0 0x0 0x0 0x0>; 3339 bus-range = <0x01 0xff>; 3340 3341 phys = <&pcie6_phy>; 3342 3343 #address-cells = <3>; 3344 #size-cells = <2>; 3345 ranges; 3346 }; 3347 }; 3348 3349 pcie6_phy: phy@1c06000 { 3350 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3351 reg = <0x0 0x01c06000 0x0 0x2000>; 3352 3353 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3354 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3355 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3356 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3357 <&gcc GCC_PCIE_6_PIPE_CLK>, 3358 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3359 clock-names = "aux", 3360 "cfg_ahb", 3361 "ref", 3362 "rchng", 3363 "pipe", 3364 "pipediv2"; 3365 3366 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3367 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3368 reset-names = "phy", 3369 "phy_nocsr"; 3370 3371 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3372 assigned-clock-rates = <100000000>; 3373 3374 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3375 3376 #clock-cells = <0>; 3377 clock-output-names = "pcie6_pipe_clk"; 3378 3379 #phy-cells = <0>; 3380 3381 status = "disabled"; 3382 }; 3383 3384 pcie3b: pci@1b80000 { 3385 device_type = "pci"; 3386 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3387 reg = <0x0 0x01b80000 0x0 0x3000>, 3388 <0x0 0x74000000 0x0 0xf20>, 3389 <0x0 0x74000f40 0x0 0xa8>, 3390 <0x0 0x74001000 0x0 0x4000>, 3391 <0x0 0x74100000 0x0 0x100000>, 3392 <0x0 0x01b83000 0x0 0x1000>; 3393 reg-names = "parf", 3394 "dbi", 3395 "elbi", 3396 "atu", 3397 "config", 3398 "mhi"; 3399 #address-cells = <3>; 3400 #size-cells = <2>; 3401 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3402 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3403 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3404 bus-range = <0x00 0xff>; 3405 3406 dma-coherent; 3407 3408 linux,pci-domain = <7>; 3409 num-lanes = <4>; 3410 3411 operating-points-v2 = <&pcie3b_opp_table>; 3412 3413 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3414 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3415 3416 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3425 interrupt-names = "msi0", 3426 "msi1", 3427 "msi2", 3428 "msi3", 3429 "msi4", 3430 "msi5", 3431 "msi6", 3432 "msi7", 3433 "global"; 3434 3435 #interrupt-cells = <1>; 3436 interrupt-map-mask = <0 0 0 0x7>; 3437 interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, 3438 <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, 3439 <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, 3440 <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; 3441 3442 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3443 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3444 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3445 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3446 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3447 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3448 clock-names = "aux", 3449 "cfg", 3450 "bus_master", 3451 "bus_slave", 3452 "slave_q2a", 3453 "noc_aggr"; 3454 3455 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3456 assigned-clock-rates = <19200000>; 3457 3458 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3459 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3460 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3461 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3462 interconnect-names = "pcie-mem", 3463 "cpu-pcie"; 3464 3465 resets = <&gcc GCC_PCIE_3B_BCR>, 3466 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3467 reset-names = "pci", 3468 "link_down"; 3469 3470 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3471 3472 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3473 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3474 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3475 3476 status = "disabled"; 3477 3478 pcie3b_opp_table: opp-table { 3479 compatible = "operating-points-v2"; 3480 3481 /* GEN 1 x1 */ 3482 opp-2500000-1 { 3483 opp-hz = /bits/ 64 <2500000>; 3484 required-opps = <&rpmhpd_opp_low_svs>; 3485 opp-peak-kBps = <250000 1>; 3486 opp-level = <1>; 3487 }; 3488 3489 /* GEN 1 x2 */ 3490 opp-5000000-1 { 3491 opp-hz = /bits/ 64 <5000000>; 3492 required-opps = <&rpmhpd_opp_low_svs>; 3493 opp-peak-kBps = <500000 1>; 3494 opp-level = <1>; 3495 }; 3496 3497 /* GEN 1 x4 */ 3498 opp-10000000-1 { 3499 opp-hz = /bits/ 64 <10000000>; 3500 required-opps = <&rpmhpd_opp_low_svs>; 3501 opp-peak-kBps = <1000000 1>; 3502 opp-level = <1>; 3503 }; 3504 3505 /* GEN 2 x1 */ 3506 opp-5000000-2 { 3507 opp-hz = /bits/ 64 <5000000>; 3508 required-opps = <&rpmhpd_opp_low_svs>; 3509 opp-peak-kBps = <500000 1>; 3510 opp-level = <2>; 3511 }; 3512 3513 /* GEN 2 x2 */ 3514 opp-10000000-2 { 3515 opp-hz = /bits/ 64 <10000000>; 3516 required-opps = <&rpmhpd_opp_low_svs>; 3517 opp-peak-kBps = <1000000 1>; 3518 opp-level = <2>; 3519 }; 3520 3521 /* GEN 2 x4 */ 3522 opp-20000000-2 { 3523 opp-hz = /bits/ 64 <20000000>; 3524 required-opps = <&rpmhpd_opp_low_svs>; 3525 opp-peak-kBps = <2000000 1>; 3526 opp-level = <2>; 3527 }; 3528 3529 /* GEN 3 x1 */ 3530 opp-8000000-3 { 3531 opp-hz = /bits/ 64 <8000000>; 3532 required-opps = <&rpmhpd_opp_low_svs>; 3533 opp-peak-kBps = <984500 1>; 3534 opp-level = <3>; 3535 }; 3536 3537 /* GEN 3 x2 */ 3538 opp-16000000-3 { 3539 opp-hz = /bits/ 64 <16000000>; 3540 required-opps = <&rpmhpd_opp_low_svs>; 3541 opp-peak-kBps = <1969000 1>; 3542 opp-level = <3>; 3543 }; 3544 3545 /* GEN 3 x4 */ 3546 opp-32000000-3 { 3547 opp-hz = /bits/ 64 <32000000>; 3548 required-opps = <&rpmhpd_opp_low_svs>; 3549 opp-peak-kBps = <3938000 1>; 3550 opp-level = <3>; 3551 }; 3552 3553 /* GEN 4 x1 */ 3554 opp-16000000-4 { 3555 opp-hz = /bits/ 64 <16000000>; 3556 required-opps = <&rpmhpd_opp_svs>; 3557 opp-peak-kBps = <1969000 1>; 3558 opp-level = <4>; 3559 }; 3560 3561 /* GEN 4 x2 */ 3562 opp-32000000-4 { 3563 opp-hz = /bits/ 64 <32000000>; 3564 required-opps = <&rpmhpd_opp_svs>; 3565 opp-peak-kBps = <3938000 1>; 3566 opp-level = <4>; 3567 }; 3568 3569 /* GEN 4 x4 */ 3570 opp-64000000-4 { 3571 opp-hz = /bits/ 64 <64000000>; 3572 required-opps = <&rpmhpd_opp_svs>; 3573 opp-peak-kBps = <7876000 1>; 3574 opp-level = <4>; 3575 }; 3576 3577 /* GEN 5 x1 */ 3578 opp-32000000-5 { 3579 opp-hz = /bits/ 64 <32000000>; 3580 required-opps = <&rpmhpd_opp_nom>; 3581 opp-peak-kBps = <3938000 1>; 3582 opp-level = <5>; 3583 }; 3584 3585 /* GEN 5 x2 */ 3586 opp-64000000-5 { 3587 opp-hz = /bits/ 64 <64000000>; 3588 required-opps = <&rpmhpd_opp_nom>; 3589 opp-peak-kBps = <7876000 1>; 3590 opp-level = <5>; 3591 }; 3592 3593 /* GEN 5 x4 */ 3594 opp-128000000-5 { 3595 opp-hz = /bits/ 64 <128000000>; 3596 required-opps = <&rpmhpd_opp_nom>; 3597 opp-peak-kBps = <15753000 1>; 3598 opp-level = <5>; 3599 }; 3600 }; 3601 3602 pcie3b_port0: pcie@0 { 3603 device_type = "pci"; 3604 reg = <0x0 0x0 0x0 0x0 0x0>; 3605 bus-range = <0x01 0xff>; 3606 3607 phys = <&pcie3b_phy>; 3608 3609 #address-cells = <3>; 3610 #size-cells = <2>; 3611 ranges; 3612 }; 3613 }; 3614 3615 pcie3b_phy: phy@f10000 { 3616 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3617 reg = <0x0 0x00f10000 0x0 0x10000>; 3618 3619 clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 3620 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3621 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 3622 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 3623 <&gcc GCC_PCIE_3B_PIPE_CLK>, 3624 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 3625 clock-names = "aux", 3626 "cfg_ahb", 3627 "ref", 3628 "rchng", 3629 "pipe", 3630 "pipediv2"; 3631 3632 resets = <&gcc GCC_PCIE_3B_PHY_BCR>, 3633 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 3634 reset-names = "phy", 3635 "phy_nocsr"; 3636 3637 assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 3638 assigned-clock-rates = <100000000>; 3639 3640 power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; 3641 3642 #clock-cells = <0>; 3643 clock-output-names = "pcie3b_pipe_clk"; 3644 3645 #phy-cells = <0>; 3646 3647 status = "disabled"; 3648 }; 3649 3650 tcsr_mutex: hwlock@1f40000 { 3651 compatible = "qcom,tcsr-mutex"; 3652 reg = <0x0 0x01f40000 0x0 0x20000>; 3653 3654 #hwlock-cells = <1>; 3655 }; 3656 3657 tcsr: clock-controller@1fd5000 { 3658 compatible = "qcom,glymur-tcsr", 3659 "syscon"; 3660 reg = <0x0 0x1fd5000 0x0 0x21000>; 3661 clocks = <&rpmhcc RPMH_CXO_CLK>; 3662 #clock-cells = <1>; 3663 #reset-cells = <1>; 3664 }; 3665 3666 hsc_noc: interconnect@2000000 { 3667 compatible = "qcom,glymur-hscnoc"; 3668 reg = <0x0 0x02000000 0x0 0x93a080>; 3669 qcom,bcm-voters = <&apps_bcm_voter>; 3670 #interconnect-cells = <2>; 3671 }; 3672 3673 ipcc: mailbox@3e04000 { 3674 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 3675 reg = <0x0 0x03e04000 0x0 0x1000>; 3676 3677 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3678 interrupt-controller; 3679 #interrupt-cells = <3>; 3680 3681 #mbox-cells = <2>; 3682 }; 3683 3684 lpass_lpiaon_noc: interconnect@7400000 { 3685 compatible = "qcom,glymur-lpass-lpiaon-noc"; 3686 reg = <0x0 0x07400000 0x0 0x19080>; 3687 qcom,bcm-voters = <&apps_bcm_voter>; 3688 #interconnect-cells = <2>; 3689 }; 3690 3691 lpass_lpicx_noc: interconnect@7420000 { 3692 compatible = "qcom,glymur-lpass-lpicx-noc"; 3693 reg = <0x0 0x07420000 0x0 0x44080>; 3694 qcom,bcm-voters = <&apps_bcm_voter>; 3695 #interconnect-cells = <2>; 3696 }; 3697 3698 lpass_ag_noc: interconnect@7e40000 { 3699 compatible = "qcom,glymur-lpass-ag-noc"; 3700 reg = <0x0 0x07e40000 0x0 0xe080>; 3701 qcom,bcm-voters = <&apps_bcm_voter>; 3702 #interconnect-cells = <2>; 3703 }; 3704 3705 usb_2_hsphy: phy@88e0000 { 3706 compatible = "qcom,glymur-m31-eusb2-phy", 3707 "qcom,sm8750-m31-eusb2-phy"; 3708 3709 reg = <0x0 0x088e0000 0x0 0x29c>; 3710 #phy-cells = <0>; 3711 3712 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 3713 clock-names = "ref"; 3714 3715 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3716 3717 status = "disabled"; 3718 }; 3719 3720 usb_2_qmpphy: phy@88e1000 { 3721 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 3722 reg = <0x0 0x088e1000 0x0 0x8000>; 3723 3724 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3725 <&rpmhcc RPMH_CXO_CLK>, 3726 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3727 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, 3728 <&tcsr TCSR_USB4_2_CLKREF_EN>; 3729 clock-names = "aux", 3730 "ref", 3731 "com_aux", 3732 "usb3_pipe", 3733 "clkref"; 3734 3735 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3736 3737 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3738 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 3739 reset-names = "phy", 3740 "common"; 3741 3742 #clock-cells = <1>; 3743 #phy-cells = <1>; 3744 3745 mode-switch; 3746 orientation-switch; 3747 3748 status = "disabled"; 3749 3750 ports { 3751 #address-cells = <1>; 3752 #size-cells = <0>; 3753 3754 port@0 { 3755 reg = <0>; 3756 3757 usb_2_qmpphy_out: endpoint { 3758 }; 3759 }; 3760 3761 port@1 { 3762 reg = <1>; 3763 3764 usb_2_qmpphy_usb_ss_in: endpoint { 3765 remote-endpoint = <&usb_2_dwc3_ss>; 3766 }; 3767 }; 3768 3769 port@2 { 3770 reg = <2>; 3771 3772 usb_2_qmpphy_dp_in: endpoint { 3773 }; 3774 }; 3775 }; 3776 }; 3777 3778 usb_0: usb@a600000 { 3779 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3780 reg = <0x0 0x0a600000 0x0 0xfc100>; 3781 3782 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3783 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3784 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3785 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3786 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3787 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3788 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3789 clock-names = "cfg_noc", 3790 "core", 3791 "iface", 3792 "sleep", 3793 "mock_utmi", 3794 "noc_aggr_north", 3795 "noc_aggr_south"; 3796 3797 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 3798 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 3799 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 3800 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 3801 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3802 interrupt-names = "dwc_usb3", 3803 "pwr_event", 3804 "dp_hs_phy_irq", 3805 "dm_hs_phy_irq", 3806 "ss_phy_irq"; 3807 3808 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3809 resets = <&gcc GCC_USB30_PRIM_BCR>; 3810 3811 iommus = <&apps_smmu 0x1420 0x0>; 3812 phys = <&usb_0_hsphy>, 3813 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3814 phy-names = "usb2-phy", 3815 "usb3-phy"; 3816 3817 snps,hird-threshold = /bits/ 8 <0x0>; 3818 snps,dis-u1-entry-quirk; 3819 snps,dis-u2-entry-quirk; 3820 snps,is-utmi-l1-suspend; 3821 snps,usb3_lpm_capable; 3822 snps,has-lpm-erratum; 3823 tx-fifo-resize; 3824 snps,dis_u2_susphy_quirk; 3825 snps,dis_enblslpm_quirk; 3826 3827 usb-role-switch; 3828 3829 status = "disabled"; 3830 3831 ports { 3832 #address-cells = <1>; 3833 #size-cells = <0>; 3834 3835 port@0 { 3836 reg = <0>; 3837 3838 usb_0_dwc3_hs: endpoint { 3839 }; 3840 }; 3841 3842 port@1 { 3843 reg = <1>; 3844 3845 usb_0_dwc3_ss: endpoint { 3846 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 3847 }; 3848 }; 3849 }; 3850 }; 3851 3852 usb_1: usb@a800000 { 3853 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3854 reg = <0x0 0x0a800000 0x0 0xfc100>; 3855 3856 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3857 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3858 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3859 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3860 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3861 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3862 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3863 clock-names = "cfg_noc", 3864 "core", 3865 "iface", 3866 "sleep", 3867 "mock_utmi", 3868 "noc_aggr_north", 3869 "noc_aggr_south"; 3870 3871 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 3872 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 3873 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 3874 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 3875 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 3876 interrupt-names = "dwc_usb3", 3877 "pwr_event", 3878 "dp_hs_phy_irq", 3879 "dm_hs_phy_irq", 3880 "ss_phy_irq"; 3881 3882 resets = <&gcc GCC_USB30_SEC_BCR>; 3883 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3884 3885 iommus = <&apps_smmu 0x1460 0x0>; 3886 3887 phys = <&usb_1_hsphy>, 3888 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3889 phy-names = "usb2-phy", 3890 "usb3-phy"; 3891 3892 snps,hird-threshold = /bits/ 8 <0x0>; 3893 snps,dis-u1-entry-quirk; 3894 snps,dis-u2-entry-quirk; 3895 snps,is-utmi-l1-suspend; 3896 snps,usb3_lpm_capable; 3897 snps,has-lpm-erratum; 3898 tx-fifo-resize; 3899 snps,dis_u2_susphy_quirk; 3900 snps,dis_enblslpm_quirk; 3901 3902 status = "disabled"; 3903 3904 ports { 3905 #address-cells = <1>; 3906 #size-cells = <0>; 3907 3908 port@0 { 3909 reg = <0>; 3910 3911 usb_1_dwc3_hs: endpoint { 3912 }; 3913 }; 3914 3915 port@1 { 3916 reg = <1>; 3917 3918 usb_1_dwc3_ss: endpoint { 3919 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3920 }; 3921 }; 3922 }; 3923 }; 3924 3925 usb_2: usb@a000000 { 3926 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3927 reg = <0x0 0x0a000000 0x0 0xfc100>; 3928 3929 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 3930 <&gcc GCC_USB30_TERT_MASTER_CLK>, 3931 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 3932 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 3933 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3934 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3935 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3936 clock-names = "cfg_noc", 3937 "core", 3938 "iface", 3939 "sleep", 3940 "mock_utmi", 3941 "noc_aggr_north", 3942 "noc_aggr_south"; 3943 3944 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 3945 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 3946 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 3947 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 3948 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 3949 interrupt-names = "dwc_usb3", 3950 "pwr_event", 3951 "dp_hs_phy_irq", 3952 "dm_hs_phy_irq", 3953 "ss_phy_irq"; 3954 3955 resets = <&gcc GCC_USB30_TERT_BCR>; 3956 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 3957 3958 iommus = <&apps_smmu 0x420 0x0>; 3959 3960 phys = <&usb_2_hsphy>, 3961 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 3962 phy-names = "usb2-phy", 3963 "usb3-phy"; 3964 3965 snps,hird-threshold = /bits/ 8 <0x0>; 3966 snps,dis-u1-entry-quirk; 3967 snps,dis-u2-entry-quirk; 3968 snps,is-utmi-l1-suspend; 3969 snps,usb3_lpm_capable; 3970 snps,has-lpm-erratum; 3971 tx-fifo-resize; 3972 snps,dis_u2_susphy_quirk; 3973 snps,dis_enblslpm_quirk; 3974 3975 status = "disabled"; 3976 3977 ports { 3978 #address-cells = <1>; 3979 #size-cells = <0>; 3980 3981 port@0 { 3982 reg = <0>; 3983 3984 usb_2_dwc3_hs: endpoint { 3985 }; 3986 }; 3987 3988 port@1 { 3989 reg = <1>; 3990 3991 usb_2_dwc3_ss: endpoint { 3992 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 3993 }; 3994 }; 3995 }; 3996 }; 3997 3998 usb_hs: usb@a2f8800 { 3999 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4000 reg = <0x0 0x0a200000 0x0 0xfc100>; 4001 4002 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4003 <&gcc GCC_USB20_MASTER_CLK>, 4004 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4005 <&gcc GCC_USB20_SLEEP_CLK>, 4006 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4007 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4008 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4009 clock-names = "cfg_noc", 4010 "core", 4011 "iface", 4012 "sleep", 4013 "mock_utmi", 4014 "noc_aggr_north", 4015 "noc_aggr_south"; 4016 4017 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4018 <&gcc GCC_USB20_MASTER_CLK>; 4019 assigned-clock-rates = <19200000>, <200000000>; 4020 4021 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4022 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 4023 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 4024 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4025 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 4026 interrupt-names = "dwc_usb3", 4027 "pwr_event", 4028 "dp_hs_phy_irq", 4029 "dm_hs_phy_irq", 4030 "hs_phy_irq"; 4031 4032 resets = <&gcc GCC_USB20_PRIM_BCR>; 4033 4034 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4035 required-opps = <&rpmhpd_opp_nom>; 4036 4037 iommus = <&apps_smmu 0x0ce0 0x0>; 4038 4039 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4040 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4041 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4042 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4043 interconnect-names = "usb-ddr", 4044 "apps-usb"; 4045 4046 phys = <&usb_hs_phy>; 4047 phy-names = "usb2-phy"; 4048 4049 snps,hird-threshold = /bits/ 8 <0x0>; 4050 snps,dis-u1-entry-quirk; 4051 snps,dis-u2-entry-quirk; 4052 snps,is-utmi-l1-suspend; 4053 snps,usb3_lpm_capable; 4054 snps,has-lpm-erratum; 4055 tx-fifo-resize; 4056 snps,dis_u2_susphy_quirk; 4057 snps,dis_enblslpm_quirk; 4058 4059 dr_mode = "host"; 4060 4061 maximum-speed = "high-speed"; 4062 4063 status = "disabled"; 4064 }; 4065 4066 usb_mp: usb@a400000 { 4067 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 4068 reg = <0x0 0x0a400000 0x0 0xfc100>; 4069 4070 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4071 <&gcc GCC_USB30_MP_MASTER_CLK>, 4072 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4073 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4074 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4075 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4076 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4077 clock-names = "cfg_noc", 4078 "core", 4079 "iface", 4080 "sleep", 4081 "mock_utmi", 4082 "noc_aggr_north", 4083 "noc_aggr_south"; 4084 4085 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4086 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4087 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4088 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 4089 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4090 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 4091 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 4092 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 4093 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 4094 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 4095 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 4096 interrupt-names = "dwc_usb3", 4097 "pwr_event_1", 4098 "pwr_event_2", 4099 "hs_phy_1", 4100 "hs_phy_2", 4101 "dp_hs_phy_1", 4102 "dm_hs_phy_1", 4103 "dp_hs_phy_2", 4104 "dm_hs_phy_2", 4105 "ss_phy_1", 4106 "ss_phy_2"; 4107 4108 resets = <&gcc GCC_USB30_MP_BCR>; 4109 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4110 4111 iommus = <&apps_smmu 0xda0 0x0>; 4112 4113 phys = <&usb_mp_hsphy0>, 4114 <&usb_mp_qmpphy0>, 4115 <&usb_mp_hsphy1>, 4116 <&usb_mp_qmpphy1>; 4117 phy-names = "usb2-0", 4118 "usb3-0", 4119 "usb2-1", 4120 "usb3-1"; 4121 4122 snps,hird-threshold = /bits/ 8 <0x0>; 4123 snps,dis-u1-entry-quirk; 4124 snps,dis-u2-entry-quirk; 4125 snps,is-utmi-l1-suspend; 4126 snps,usb3_lpm_capable; 4127 snps,has-lpm-erratum; 4128 tx-fifo-resize; 4129 snps,dis_u2_susphy_quirk; 4130 snps,dis_enblslpm_quirk; 4131 4132 dr_mode = "host"; 4133 4134 status = "disabled"; 4135 }; 4136 4137 4138 dispcc: clock-controller@af00000 { 4139 compatible = "qcom,glymur-dispcc"; 4140 reg = <0x0 0x0af00000 0x0 0x20000>; 4141 clocks = <&rpmhcc RPMH_CXO_CLK>, 4142 <&sleep_clk>, 4143 <0>, /* dp0 */ 4144 <0>, 4145 <0>, /* dp1 */ 4146 <0>, 4147 <0>, /* dp2 */ 4148 <0>, 4149 <0>, /* dp3 */ 4150 <0>, 4151 <0>, /* dsi0 */ 4152 <0>, 4153 <0>, /* dsi1 */ 4154 <0>, 4155 <0>, 4156 <0>, 4157 <0>, 4158 <0>; 4159 power-domains = <&rpmhpd RPMHPD_MMCX>; 4160 required-opps = <&rpmhpd_opp_low_svs>; 4161 #clock-cells = <1>; 4162 #reset-cells = <1>; 4163 #power-domain-cells = <1>; 4164 }; 4165 4166 pdc: interrupt-controller@b220000 { 4167 compatible = "qcom,glymur-pdc", "qcom,pdc"; 4168 reg = <0x0 0x0b220000 0x0 0x10000>; 4169 qcom,pdc-ranges = <0 745 51>, 4170 <51 527 47>, 4171 <98 609 32>, 4172 <130 717 12>, 4173 <142 251 5>, 4174 <147 796 16>, 4175 <171 4104 36>; 4176 #interrupt-cells = <2>; 4177 interrupt-parent = <&intc>; 4178 interrupt-controller; 4179 }; 4180 4181 tsens0: thermal-sensor@c22c000 { 4182 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4183 reg = <0x0 0x0c22c000 0x0 0x1000>, 4184 <0x0 0x0c222000 0x0 0x1000>; 4185 4186 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 4188 interrupt-names = "uplow", 4189 "critical"; 4190 4191 #qcom,sensors = <13>; 4192 4193 #thermal-sensor-cells = <1>; 4194 }; 4195 4196 tsens1: thermal-sensor@c22d000 { 4197 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4198 reg = <0x0 0x0c22d000 0x0 0x1000>, 4199 <0x0 0x0c223000 0x0 0x1000>; 4200 4201 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 4203 interrupt-names = "uplow", 4204 "critical"; 4205 4206 #qcom,sensors = <9>; 4207 4208 #thermal-sensor-cells = <1>; 4209 }; 4210 4211 tsens2: thermal-sensor@c22e000 { 4212 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4213 reg = <0x0 0x0c22e000 0x0 0x1000>, 4214 <0x0 0x0c224000 0x0 0x1000>; 4215 4216 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 4218 interrupt-names = "uplow", 4219 "critical"; 4220 4221 #qcom,sensors = <13>; 4222 4223 #thermal-sensor-cells = <1>; 4224 }; 4225 4226 tsens3: thermal-sensor@c22f000 { 4227 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4228 reg = <0x0 0x0c22f000 0x0 0x1000>, 4229 <0x0 0x0c225000 0x0 0x1000>; 4230 4231 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 4233 interrupt-names = "uplow", 4234 "critical"; 4235 4236 #qcom,sensors = <8>; 4237 4238 #thermal-sensor-cells = <1>; 4239 }; 4240 4241 tsens4: thermal-sensor@c230000 { 4242 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4243 reg = <0x0 0x0c230000 0x0 0x1000>, 4244 <0x0 0x0c226000 0x0 0x1000>; 4245 4246 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4248 interrupt-names = "uplow", 4249 "critical"; 4250 4251 #qcom,sensors = <13>; 4252 4253 #thermal-sensor-cells = <1>; 4254 }; 4255 4256 tsens5: thermal-sensor@c231000 { 4257 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4258 reg = <0x0 0x0c231000 0x0 0x1000>, 4259 <0x0 0x0c227000 0x0 0x1000>; 4260 4261 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 4263 interrupt-names = "uplow", 4264 "critical"; 4265 4266 #qcom,sensors = <8>; 4267 4268 #thermal-sensor-cells = <1>; 4269 }; 4270 4271 tsens6: thermal-sensor@c232000 { 4272 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4273 reg = <0x0 0x0c232000 0x0 0x1000>, 4274 <0x0 0x0c228000 0x0 0x1000>; 4275 4276 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 4278 interrupt-names = "uplow", 4279 "critical"; 4280 4281 #qcom,sensors = <13>; 4282 4283 #thermal-sensor-cells = <1>; 4284 }; 4285 4286 tsens7: thermal-sensor@c233000 { 4287 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4288 reg = <0x0 0x0c233000 0x0 0x1000>, 4289 <0x0 0x0c229000 0x0 0x1000>; 4290 4291 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 4293 interrupt-names = "uplow", 4294 "critical"; 4295 4296 #qcom,sensors = <15>; 4297 4298 #thermal-sensor-cells = <1>; 4299 }; 4300 4301 aoss_qmp: power-management@c300000 { 4302 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 4303 reg = <0x0 0x0c300000 0x0 0x400>; 4304 interrupt-parent = <&ipcc>; 4305 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4306 IRQ_TYPE_EDGE_RISING>; 4307 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4308 4309 #clock-cells = <0>; 4310 }; 4311 4312 sram@c30f000 { 4313 compatible = "qcom,rpmh-stats"; 4314 reg = <0x0 0x0c30f000 0x0 0x400>; 4315 }; 4316 4317 arbiter@c400000 { 4318 compatible = "qcom,glymur-spmi-pmic-arb"; 4319 reg = <0x0 0x0c400000 0x0 0x3000>, 4320 <0x0 0x0c900000 0x0 0x400000>, 4321 <0x0 0x0c4c0000 0x0 0x400000>, 4322 <0x0 0x0c403000 0x0 0x8000>; 4323 reg-names = "core", 4324 "chnls", 4325 "obsrvr", 4326 "chnl_map"; 4327 #address-cells = <2>; 4328 #size-cells = <2>; 4329 ranges; 4330 qcom,channel = <0>; 4331 qcom,ee = <0>; 4332 4333 spmi_bus0: spmi@c426000 { 4334 reg = <0x0 0x0c426000 0x0 0x4000>, 4335 <0x0 0x0c8c0000 0x0 0x10000>, 4336 <0x0 0x0c42a000 0x0 0x8000>; 4337 reg-names = "cnfg", 4338 "intr", 4339 "chnl_owner"; 4340 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4341 interrupt-names = "periph_irq"; 4342 interrupt-controller; 4343 #interrupt-cells = <4>; 4344 #address-cells = <2>; 4345 #size-cells = <0>; 4346 }; 4347 4348 spmi_bus1: spmi@c437000 { 4349 reg = <0x0 0x0c437000 0x0 0x4000>, 4350 <0x0 0x0c8d0000 0x0 0x10000>, 4351 <0x0 0x0c43b000 0x0 0x8000>; 4352 reg-names = "cnfg", 4353 "intr", 4354 "chnl_owner"; 4355 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 4356 interrupt-names = "periph_irq"; 4357 interrupt-controller; 4358 #interrupt-cells = <4>; 4359 #address-cells = <2>; 4360 #size-cells = <0>; 4361 }; 4362 4363 spmi_bus2: spmi@c48000 { 4364 reg = <0x0 0x0c448000 0x0 0x4000>, 4365 <0x0 0x0c8e0000 0x0 0x10000>, 4366 <0x0 0x0c44c000 0x0 0x8000>; 4367 reg-names = "cnfg", 4368 "intr", 4369 "chnl_owner"; 4370 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 4371 interrupt-names = "periph_irq"; 4372 interrupt-controller; 4373 #interrupt-cells = <4>; 4374 #address-cells = <2>; 4375 #size-cells = <0>; 4376 }; 4377 }; 4378 4379 tlmm: pinctrl@f100000 { 4380 compatible = "qcom,glymur-tlmm"; 4381 reg = <0x0 0x0f100000 0x0 0xf00000>; 4382 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4383 gpio-controller; 4384 #gpio-cells = <2>; 4385 interrupt-controller; 4386 #interrupt-cells = <2>; 4387 gpio-ranges = <&tlmm 0 0 249>; 4388 wakeup-parent = <&pdc>; 4389 4390 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4391 /* SDA, SCL */ 4392 pins = "gpio0", "gpio1"; 4393 function = "qup0_se0"; 4394 drive-strength = <2>; 4395 bias-pull-up = <2200>; 4396 }; 4397 4398 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4399 /* SDA, SCL */ 4400 pins = "gpio4", "gpio5"; 4401 function = "qup0_se1"; 4402 drive-strength = <2>; 4403 bias-pull-up = <2200>; 4404 }; 4405 4406 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4407 /* SDA, SCL */ 4408 pins = "gpio8", "gpio9"; 4409 function = "qup0_se2"; 4410 drive-strength = <2>; 4411 bias-pull-up = <2200>; 4412 }; 4413 4414 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4415 /* SDA, SCL */ 4416 pins = "gpio12", "gpio13"; 4417 function = "qup0_se3"; 4418 drive-strength = <2>; 4419 bias-pull-up = <2200>; 4420 }; 4421 4422 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4423 /* SDA, SCL */ 4424 pins = "gpio16", "gpio17"; 4425 function = "qup0_se4"; 4426 drive-strength = <2>; 4427 bias-pull-up = <2200>; 4428 }; 4429 4430 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4431 /* SDA, SCL */ 4432 pins = "gpio20", "gpio21"; 4433 function = "qup0_se5"; 4434 drive-strength = <2>; 4435 bias-pull-up = <2200>; 4436 }; 4437 4438 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4439 /* SDA, SCL */ 4440 pins = "gpio6", "gpio7"; 4441 function = "qup0_se6"; 4442 drive-strength = <2>; 4443 bias-pull-up = <2200>; 4444 }; 4445 4446 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4447 /* SDA, SCL */ 4448 pins = "gpio14", "gpio15"; 4449 function = "qup0_se7"; 4450 drive-strength = <2>; 4451 bias-pull-up = <2200>; 4452 }; 4453 4454 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4455 /* SDA, SCL */ 4456 pins = "gpio32", "gpio33"; 4457 function = "qup1_se0"; 4458 drive-strength = <2>; 4459 bias-pull-up = <2200>; 4460 }; 4461 4462 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4463 /* SDA, SCL */ 4464 pins = "gpio36", "gpio37"; 4465 function = "qup1_se1"; 4466 drive-strength = <2>; 4467 bias-pull-up = <2200>; 4468 }; 4469 4470 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4471 /* SDA, SCL */ 4472 pins = "gpio40", "gpio41"; 4473 function = "qup1_se2"; 4474 drive-strength = <2>; 4475 bias-pull-up = <2200>; 4476 }; 4477 4478 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4479 /* SDA, SCL */ 4480 pins = "gpio44", "gpio45"; 4481 function = "qup1_se3"; 4482 drive-strength = <2>; 4483 bias-pull-up = <2200>; 4484 }; 4485 4486 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4487 /* SDA, SCL */ 4488 pins = "gpio48", "gpio49"; 4489 function = "qup1_se4"; 4490 drive-strength = <2>; 4491 bias-pull-up = <2200>; 4492 }; 4493 4494 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4495 /* SDA, SCL */ 4496 pins = "gpio52", "gpio53"; 4497 function = "qup1_se5"; 4498 drive-strength = <2>; 4499 bias-pull-up = <2200>; 4500 }; 4501 4502 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4503 /* SDA, SCL */ 4504 pins = "gpio56", "gpio57"; 4505 function = "qup1_se6"; 4506 drive-strength = <2>; 4507 bias-pull-up = <2200>; 4508 }; 4509 4510 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4511 /* SDA, SCL */ 4512 pins = "gpio54", "gpio55"; 4513 function = "qup1_se7"; 4514 drive-strength = <2>; 4515 bias-pull-up = <2200>; 4516 }; 4517 4518 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4519 /* SDA, SCL */ 4520 pins = "gpio64", "gpio65"; 4521 function = "qup2_se0"; 4522 drive-strength = <2>; 4523 bias-pull-up = <2200>; 4524 }; 4525 4526 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 4527 /* SDA, SCL */ 4528 pins = "gpio68", "gpio69"; 4529 function = "qup2_se1"; 4530 drive-strength = <2>; 4531 bias-pull-up = <2200>; 4532 }; 4533 4534 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 4535 /* SDA, SCL */ 4536 pins = "gpio72", "gpio73"; 4537 function = "qup2_se2"; 4538 drive-strength = <2>; 4539 bias-pull-up = <2200>; 4540 }; 4541 4542 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 4543 /* SDA, SCL */ 4544 pins = "gpio76", "gpio77"; 4545 function = "qup2_se3"; 4546 drive-strength = <2>; 4547 bias-pull-up = <2200>; 4548 }; 4549 4550 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 4551 /* SDA, SCL */ 4552 pins = "gpio80", "gpio81"; 4553 function = "qup2_se4"; 4554 drive-strength = <2>; 4555 bias-pull-up = <2200>; 4556 }; 4557 4558 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 4559 /* SDA, SCL */ 4560 pins = "gpio84", "gpio85"; 4561 function = "qup2_se5"; 4562 drive-strength = <2>; 4563 bias-pull-up = <2200>; 4564 }; 4565 4566 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 4567 /* SDA, SCL */ 4568 pins = "gpio88", "gpio89"; 4569 function = "qup2_se6"; 4570 drive-strength = <2>; 4571 bias-pull-up = <2200>; 4572 }; 4573 4574 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 4575 /* SDA, SCL */ 4576 pins = "gpio80", "gpio81"; 4577 function = "qup2_se7"; 4578 drive-strength = <2>; 4579 bias-pull-up = <2200>; 4580 }; 4581 4582 qup_spi0_cs: qup-spi0-cs-state { 4583 pins = "gpio3"; 4584 function = "qup0_se0"; 4585 drive-strength = <6>; 4586 bias-disable; 4587 }; 4588 4589 qup_spi0_data_clk: qup-spi0-data-clk-state { 4590 /* MISO, MOSI, CLK */ 4591 pins = "gpio0", "gpio1", "gpio2"; 4592 function = "qup0_se0"; 4593 drive-strength = <6>; 4594 bias-disable; 4595 }; 4596 4597 qup_spi1_cs: qup-spi1-cs-state { 4598 pins = "gpio7"; 4599 function = "qup0_se1"; 4600 drive-strength = <6>; 4601 bias-disable; 4602 }; 4603 4604 qup_spi1_data_clk: qup-spi1-data-clk-state { 4605 /* MISO, MOSI, CLK */ 4606 pins = "gpio4", "gpio5", "gpio6"; 4607 function = "qup0_se1"; 4608 drive-strength = <6>; 4609 bias-disable; 4610 }; 4611 4612 qup_spi2_cs: qup-spi2-cs-state { 4613 pins = "gpio11"; 4614 function = "qup0_se2"; 4615 drive-strength = <6>; 4616 bias-disable; 4617 }; 4618 4619 qup_spi2_data_clk: qup-spi2-data-clk-state { 4620 /* MISO, MOSI, CLK */ 4621 pins = "gpio8", "gpio9", "gpio10"; 4622 function = "qup0_se2"; 4623 drive-strength = <6>; 4624 bias-disable; 4625 }; 4626 4627 qup_spi3_cs: qup-spi3-cs-state { 4628 pins = "gpio15"; 4629 function = "qup0_se3"; 4630 drive-strength = <6>; 4631 bias-disable; 4632 }; 4633 4634 qup_spi3_data_clk: qup-spi3-data-clk-state { 4635 /* MISO, MOSI, CLK */ 4636 pins = "gpio12", "gpio13", "gpio14"; 4637 function = "qup0_se3"; 4638 drive-strength = <6>; 4639 bias-disable; 4640 }; 4641 4642 qup_spi4_cs: qup-spi4-cs-state { 4643 pins = "gpio19"; 4644 function = "qup0_se4"; 4645 drive-strength = <6>; 4646 bias-disable; 4647 }; 4648 4649 qup_spi4_data_clk: qup-spi4-data-clk-state { 4650 /* MISO, MOSI, CLK */ 4651 pins = "gpio16", "gpio17", "gpio18"; 4652 function = "qup0_se4"; 4653 drive-strength = <6>; 4654 bias-disable; 4655 }; 4656 4657 qup_spi5_cs: qup-spi5-cs-state { 4658 pins = "gpio23"; 4659 function = "qup0_se5"; 4660 drive-strength = <6>; 4661 bias-disable; 4662 }; 4663 4664 qup_spi5_data_clk: qup-spi5-data-clk-state { 4665 /* MISO, MOSI, CLK */ 4666 pins = "gpio20", "gpio21", "gpio22"; 4667 function = "qup0_se5"; 4668 drive-strength = <6>; 4669 bias-disable; 4670 }; 4671 4672 qup_spi6_cs: qup-spi6-cs-state { 4673 pins = "gpio5"; 4674 function = "qup0_se6"; 4675 drive-strength = <6>; 4676 bias-disable; 4677 }; 4678 4679 qup_spi6_data_clk: qup-spi6-data-clk-state { 4680 /* MISO, MOSI, CLK */ 4681 pins = "gpio6", "gpio7", "gpio4"; 4682 function = "qup0_se6"; 4683 drive-strength = <6>; 4684 bias-disable; 4685 }; 4686 4687 qup_spi7_cs: qup-spi7-cs-state { 4688 pins = "gpio13"; 4689 function = "qup0_se7"; 4690 drive-strength = <6>; 4691 bias-disable; 4692 }; 4693 4694 qup_spi7_data_clk: qup-spi7-data-clk-state { 4695 /* MISO, MOSI, CLK */ 4696 pins = "gpio14", "gpio15", "gpio12"; 4697 function = "qup0_se7"; 4698 drive-strength = <6>; 4699 bias-disable; 4700 }; 4701 4702 qup_spi8_cs: qup-spi8-cs-state { 4703 pins = "gpio35"; 4704 function = "qup1_se0"; 4705 drive-strength = <6>; 4706 bias-disable; 4707 }; 4708 4709 qup_spi8_data_clk: qup-spi8-data-clk-state { 4710 /* MISO, MOSI, CLK */ 4711 pins = "gpio32", "gpio33", "gpio34"; 4712 function = "qup1_se0"; 4713 drive-strength = <6>; 4714 bias-disable; 4715 }; 4716 4717 qup_spi9_cs: qup-spi9-cs-state { 4718 pins = "gpio39"; 4719 function = "qup1_se1"; 4720 drive-strength = <6>; 4721 bias-disable; 4722 }; 4723 4724 qup_spi9_data_clk: qup-spi9-data-clk-state { 4725 /* MISO, MOSI, CLK */ 4726 pins = "gpio36", "gpio37", "gpio38"; 4727 function = "qup1_se1"; 4728 drive-strength = <6>; 4729 bias-disable; 4730 }; 4731 4732 qup_spi10_cs: qup-spi10-cs-state { 4733 pins = "gpio43"; 4734 function = "qup1_se2"; 4735 drive-strength = <6>; 4736 bias-disable; 4737 }; 4738 4739 qup_spi10_data_clk: qup-spi10-data-clk-state { 4740 /* MISO, MOSI, CLK */ 4741 pins = "gpio40", "gpio41", "gpio42"; 4742 function = "qup1_se2"; 4743 drive-strength = <6>; 4744 bias-disable; 4745 }; 4746 4747 qup_spi11_cs: qup-spi11-cs-state { 4748 pins = "gpio47"; 4749 function = "qup1_se3"; 4750 drive-strength = <6>; 4751 bias-disable; 4752 }; 4753 4754 qup_spi11_data_clk: qup-spi11-data-clk-state { 4755 pins = "gpio44", "gpio45", "gpio46"; 4756 function = "qup1_se3"; 4757 drive-strength = <6>; 4758 bias-disable; 4759 }; 4760 4761 qup_spi12_cs: qup-spi12-cs-state { 4762 pins = "gpio51"; 4763 function = "qup1_se4"; 4764 drive-strength = <6>; 4765 bias-disable; 4766 }; 4767 4768 qup_spi12_data_clk: qup-spi12-data-clk-state { 4769 /* MISO, MOSI, CLK */ 4770 pins = "gpio48", "gpio49", "gpio50"; 4771 function = "qup1_se4"; 4772 drive-strength = <6>; 4773 bias-disable; 4774 }; 4775 4776 qup_spi13_cs: qup-spi13-cs-state { 4777 pins = "gpio55"; 4778 function = "qup1_se5"; 4779 drive-strength = <6>; 4780 bias-disable; 4781 }; 4782 4783 qup_spi13_data_clk: qup-spi13-data-clk-state { 4784 /* MISO, MOSI, CLK */ 4785 pins = "gpio52", "gpio53", "gpio54"; 4786 function = "qup1_se5"; 4787 drive-strength = <6>; 4788 bias-disable; 4789 }; 4790 4791 qup_spi14_cs: qup-spi14-cs-state { 4792 pins = "gpio59"; 4793 function = "qup1_se6"; 4794 drive-strength = <6>; 4795 bias-disable; 4796 }; 4797 4798 qup_spi14_data_clk: qup-spi14-data-clk-state { 4799 /* MISO, MOSI, CLK */ 4800 pins = "gpio56", "gpio57", "gpio58"; 4801 function = "qup1_se6"; 4802 drive-strength = <6>; 4803 bias-disable; 4804 }; 4805 4806 qup_spi15_cs: qup-spi15-cs-state { 4807 pins = "gpio53"; 4808 function = "qup1_se7"; 4809 drive-strength = <6>; 4810 bias-disable; 4811 }; 4812 4813 qup_spi15_data_clk: qup-spi15-data-clk-state { 4814 /* MISO, MOSI, CLK */ 4815 pins = "gpio54", "gpio55", "gpio52"; 4816 function = "qup1_se7"; 4817 drive-strength = <6>; 4818 bias-disable; 4819 }; 4820 4821 qup_spi16_cs: qup-spi16-cs-state { 4822 pins = "gpio67"; 4823 function = "qup2_se0"; 4824 drive-strength = <6>; 4825 bias-disable; 4826 }; 4827 4828 qup_spi16_data_clk: qup-spi16-data-clk-state { 4829 /* MISO, MOSI, CLK */ 4830 pins = "gpio64", "gpio65", "gpio66"; 4831 function = "qup2_se0"; 4832 drive-strength = <6>; 4833 bias-disable; 4834 }; 4835 4836 qup_spi17_cs: qup-spi17-cs-state { 4837 pins = "gpio71"; 4838 function = "qup2_se1"; 4839 drive-strength = <6>; 4840 bias-disable; 4841 }; 4842 4843 qup_spi17_data_clk: qup-spi17-data-clk-state { 4844 /* MISO, MOSI, CLK */ 4845 pins = "gpio68", "gpio69", "gpio70"; 4846 function = "qup2_se1"; 4847 drive-strength = <6>; 4848 bias-disable; 4849 }; 4850 4851 qup_spi18_cs: qup-spi18-cs-state { 4852 pins = "gpio75"; 4853 function = "qup2_se2"; 4854 drive-strength = <6>; 4855 bias-disable; 4856 }; 4857 4858 qup_spi18_data_clk: qup-spi18-data-clk-state { 4859 /* MISO, MOSI, CLK */ 4860 pins = "gpio72", "gpio73", "gpio74"; 4861 function = "qup2_se2"; 4862 drive-strength = <6>; 4863 bias-disable; 4864 }; 4865 4866 qup_spi19_cs: qup-spi19-cs-state { 4867 pins = "gpio79"; 4868 function = "qup2_se3"; 4869 drive-strength = <6>; 4870 bias-disable; 4871 }; 4872 4873 qup_spi19_data_clk: qup-spi19-data-clk-state { 4874 /* MISO, MOSI, CLK */ 4875 pins = "gpio76", "gpio77", "gpio78"; 4876 function = "qup2_se3"; 4877 drive-strength = <6>; 4878 bias-disable; 4879 }; 4880 4881 qup_spi20_cs: qup-spi20-cs-state { 4882 pins = "gpio83"; 4883 function = "qup2_se4"; 4884 drive-strength = <6>; 4885 bias-disable; 4886 }; 4887 4888 qup_spi20_data_clk: qup-spi20-data-clk-state { 4889 /* MISO, MOSI, CLK */ 4890 pins = "gpio80", "gpio81", "gpio82"; 4891 function = "qup2_se4"; 4892 drive-strength = <6>; 4893 bias-disable; 4894 }; 4895 4896 qup_spi21_cs: qup-spi21-cs-state { 4897 pins = "gpio87"; 4898 function = "qup2_se5"; 4899 drive-strength = <6>; 4900 bias-disable; 4901 }; 4902 4903 qup_spi21_data_clk: qup-spi21-data-clk-state { 4904 /* MISO, MOSI, CLK */ 4905 pins = "gpio84", "gpio85", "gpio86"; 4906 function = "qup2_se5"; 4907 drive-strength = <6>; 4908 bias-disable; 4909 }; 4910 4911 qup_spi22_cs: qup-spi22-cs-state { 4912 pins = "gpio91"; 4913 function = "qup2_se6"; 4914 drive-strength = <6>; 4915 bias-disable; 4916 }; 4917 4918 qup_spi22_data_clk: qup-spi22-data-clk-state { 4919 /* MISO, MOSI, CLK */ 4920 pins = "gpio88", "gpio89", "gpio90"; 4921 function = "qup2_se6"; 4922 drive-strength = <6>; 4923 bias-disable; 4924 }; 4925 4926 qup_spi23_cs: qup-spi23-cs-state { 4927 pins = "gpio83"; 4928 function = "qup2_se7"; 4929 drive-strength = <6>; 4930 bias-disable; 4931 }; 4932 4933 qup_spi23_data_clk: qup-spi23-data-clk-state { 4934 /* MISO, MOSI, CLK */ 4935 pins = "gpio80", "gpio81", "gpio82"; 4936 function = "qup2_se7"; 4937 drive-strength = <6>; 4938 bias-disable; 4939 }; 4940 4941 qup_uart2_default: qup-uart2-default-state { 4942 tx-pins { 4943 pins = "gpio10"; 4944 function = "qup0_se2"; 4945 drive-strength = <2>; 4946 bias-disable; 4947 }; 4948 4949 rx-pins { 4950 pins = "gpio11"; 4951 function = "qup0_se2"; 4952 drive-strength = <2>; 4953 bias-disable; 4954 }; 4955 }; 4956 4957 qup_uart14_default: qup-uart14-default-state { 4958 cts-pins { 4959 pins = "gpio56"; 4960 function = "qup1_se6"; 4961 drive-strength = <2>; 4962 bias-disable; 4963 }; 4964 4965 rts-pins { 4966 pins = "gpio57"; 4967 function = "qup1_se6"; 4968 drive-strength = <2>; 4969 bias-disable; 4970 }; 4971 4972 tx-pins { 4973 pins = "gpio58"; 4974 function = "qup1_se6"; 4975 drive-strength = <2>; 4976 bias-disable; 4977 }; 4978 4979 rx-pins { 4980 pins = "gpio59"; 4981 function = "qup1_se6"; 4982 drive-strength = <2>; 4983 bias-disable; 4984 }; 4985 }; 4986 4987 qup_uart19_default: qup-uart19-default-state { 4988 cts-pins { 4989 pins = "gpio76"; 4990 function = "qup2_se3"; 4991 drive-strength = <2>; 4992 bias-disable; 4993 }; 4994 4995 rts-pins { 4996 pins = "gpio77"; 4997 function = "qup2_se3"; 4998 drive-strength = <2>; 4999 bias-disable; 5000 }; 5001 5002 tx-pins { 5003 pins = "gpio78"; 5004 function = "qup2_se3"; 5005 drive-strength = <2>; 5006 bias-disable; 5007 }; 5008 5009 rx-pins { 5010 pins = "gpio79"; 5011 function = "qup2_se3"; 5012 drive-strength = <2>; 5013 bias-disable; 5014 }; 5015 }; 5016 5017 qup_uart21_default: qup-uart21-default-state { 5018 tx-pins { 5019 pins = "gpio86"; 5020 function = "qup2_se5"; 5021 drive-strength = <2>; 5022 bias-disable; 5023 }; 5024 5025 rx-pins { 5026 pins = "gpio87"; 5027 function = "qup2_se5"; 5028 drive-strength = <2>; 5029 bias-disable; 5030 }; 5031 }; 5032 5033 qup_uart22_default: qup-uart22-default-state { 5034 tx-pins { 5035 pins = "gpio90"; 5036 function = "qup2_se6"; 5037 drive-strength = <2>; 5038 bias-disable; 5039 }; 5040 5041 rx-pins { 5042 pins = "gpio91"; 5043 function = "qup2_se6"; 5044 drive-strength = <2>; 5045 bias-disable; 5046 }; 5047 }; 5048 }; 5049 5050 apps_smmu: iommu@15000000 { 5051 compatible = "qcom,glymur-smmu-500", 5052 "qcom,smmu-500", 5053 "arm,mmu-500"; 5054 reg = <0x0 0x15000000 0x0 0x100000>; 5055 5056 #iommu-cells = <2>; 5057 #global-interrupts = <1>; 5058 5059 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 5172 5173 dma-coherent; 5174 }; 5175 5176 pcie_smmu: iommu@15480000 { 5177 compatible = "arm,smmu-v3"; 5178 reg = <0x0 0x15480000 0x0 0x20000>; 5179 interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>; 5182 interrupt-names = "eventq", "cmdq-sync", "gerror"; 5183 dma-coherent; 5184 #iommu-cells = <1>; 5185 }; 5186 5187 intc: interrupt-controller@17000000 { 5188 compatible = "arm,gic-v3"; 5189 reg = <0x0 0x17000000 0x0 0x10000>, 5190 <0x0 0x17080000 0x0 0x480000>; 5191 5192 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5193 5194 #interrupt-cells = <3>; 5195 interrupt-controller; 5196 5197 #address-cells = <2>; 5198 #size-cells = <2>; 5199 ranges; 5200 5201 gic_its: msi-controller@17040000 { 5202 compatible = "arm,gic-v3-its"; 5203 reg = <0x0 0x17040000 0x0 0x40000>; 5204 5205 msi-controller; 5206 #msi-cells = <1>; 5207 }; 5208 }; 5209 5210 watchdog@17600000 { 5211 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 5212 reg = <0x0 0x17600000 0x0 0x1000>; 5213 clocks = <&sleep_clk>; 5214 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5215 }; 5216 5217 pdp0_mbox: mailbox@17610000 { 5218 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 5219 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 5220 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 5221 #mbox-cells = <1>; 5222 }; 5223 5224 timer@17810000 { 5225 compatible = "arm,armv7-timer-mem"; 5226 reg = <0x0 0x17810000 0x0 0x1000>; 5227 #address-cells = <2>; 5228 #size-cells = <1>; 5229 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 5230 5231 frame@17811000 { 5232 reg = <0x0 0x17811000 0x1000>, 5233 <0x0 0x17812000 0x1000>; 5234 5235 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5236 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5237 5238 frame-number = <0>; 5239 }; 5240 5241 frame@17813000 { 5242 reg = <0x0 0x17813000 0x1000>; 5243 5244 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5245 5246 frame-number = <1>; 5247 5248 status = "disabled"; 5249 }; 5250 5251 frame@17815000 { 5252 reg = <0x0 0x17815000 0x1000>; 5253 5254 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5255 5256 frame-number = <2>; 5257 5258 status = "disabled"; 5259 }; 5260 5261 frame@17817000 { 5262 reg = <0x0 0x17817000 0x1000>; 5263 5264 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5265 5266 frame-number = <3>; 5267 5268 status = "disabled"; 5269 }; 5270 5271 frame@17819000 { 5272 reg = <0x0 0x17819000 0x1000>; 5273 5274 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5275 5276 frame-number = <4>; 5277 5278 status = "disabled"; 5279 }; 5280 5281 frame@1781b000 { 5282 reg = <0x0 0x1781b000 0x1000>; 5283 5284 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5285 5286 frame-number = <5>; 5287 5288 status = "disabled"; 5289 }; 5290 5291 frame@1781d000 { 5292 reg = <0x0 0x1781d000 0x1000>; 5293 5294 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5295 5296 frame-number = <6>; 5297 5298 status = "disabled"; 5299 }; 5300 }; 5301 5302 apps_rsc: rsc@18900000 { 5303 compatible = "qcom,rpmh-rsc"; 5304 label = "apps_rsc"; 5305 reg = <0x0 0x18900000 0x0 0x10000>, 5306 <0x0 0x18910000 0x0 0x10000>, 5307 <0x0 0x18920000 0x0 0x10000>; 5308 reg-names = "drv-0", 5309 "drv-1", 5310 "drv-2"; 5311 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5314 qcom,tcs-offset = <0xd00>; 5315 qcom,drv-id = <2>; 5316 qcom,tcs-config = <ACTIVE_TCS 2>, 5317 <SLEEP_TCS 3>, 5318 <WAKE_TCS 3>, 5319 <CONTROL_TCS 0>; 5320 power-domains = <&system_pd>; 5321 5322 apps_bcm_voter: bcm-voter { 5323 compatible = "qcom,bcm-voter"; 5324 }; 5325 5326 rpmhcc: clock-controller { 5327 compatible = "qcom,glymur-rpmh-clk"; 5328 5329 clocks = <&xo_board>; 5330 clock-names = "xo"; 5331 5332 #clock-cells = <1>; 5333 }; 5334 5335 rpmhpd: power-controller { 5336 compatible = "qcom,glymur-rpmhpd"; 5337 5338 operating-points-v2 = <&rpmhpd_opp_table>; 5339 5340 #power-domain-cells = <1>; 5341 5342 rpmhpd_opp_table: opp-table { 5343 compatible = "operating-points-v2"; 5344 5345 rpmhpd_opp_ret: opp-16 { 5346 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5347 }; 5348 5349 rpmhpd_opp_min_svs: opp-48 { 5350 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5351 }; 5352 5353 rpmhpd_opp_low_svs_d2: opp-52 { 5354 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5355 }; 5356 5357 rpmhpd_opp_low_svs_d1: opp-56 { 5358 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5359 }; 5360 5361 rpmhpd_opp_low_svs_d0: opp-60 { 5362 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5363 }; 5364 5365 rpmhpd_opp_low_svs: opp-64 { 5366 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5367 }; 5368 5369 rpmhpd_opp_low_svs_l1: opp-80 { 5370 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5371 }; 5372 5373 rpmhpd_opp_svs: opp-128 { 5374 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5375 }; 5376 5377 rpmhpd_opp_svs_l0: opp-144 { 5378 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5379 }; 5380 5381 rpmhpd_opp_svs_l1: opp-192 { 5382 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5383 }; 5384 5385 rpmhpd_opp_nom: opp-256 { 5386 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5387 }; 5388 5389 rpmhpd_opp_nom_l1: opp-320 { 5390 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5391 }; 5392 5393 rpmhpd_opp_nom_l2: opp-336 { 5394 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5395 }; 5396 5397 rpmhpd_opp_turbo: opp-384 { 5398 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5399 }; 5400 5401 rpmhpd_opp_turbo_l1: opp-416 { 5402 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5403 }; 5404 }; 5405 }; 5406 }; 5407 5408 nsi_noc: interconnect@1d600000 { 5409 compatible = "qcom,glymur-nsinoc"; 5410 reg = <0x0 0x1d600000 0x0 0x14080>; 5411 qcom,bcm-voters = <&apps_bcm_voter>; 5412 #interconnect-cells = <2>; 5413 }; 5414 5415 oobm_ss_noc: interconnect@1f300000 { 5416 compatible = "qcom,glymur-oobm-ss-noc"; 5417 reg = <0x0 0x1f300000 0x0 0x49a00>; 5418 qcom,bcm-voters = <&apps_bcm_voter>; 5419 #interconnect-cells = <2>; 5420 }; 5421 5422 system-cache-controller@20400000 { 5423 compatible = "qcom,glymur-llcc"; 5424 reg = <0x0 0x21800000 0x0 0x100000>, 5425 <0x0 0x21a00000 0x0 0x100000>, 5426 <0x0 0x21c00000 0x0 0x100000>, 5427 <0x0 0x21e00000 0x0 0x100000>, 5428 <0x0 0x22800000 0x0 0x100000>, 5429 <0x0 0x22a00000 0x0 0x100000>, 5430 <0x0 0x22c00000 0x0 0x100000>, 5431 <0x0 0x22e00000 0x0 0x100000>, 5432 <0x0 0x23800000 0x0 0x100000>, 5433 <0x0 0x23a00000 0x0 0x100000>, 5434 <0x0 0x23c00000 0x0 0x100000>, 5435 <0x0 0x23e00000 0x0 0x100000>, 5436 <0x0 0x20400000 0x0 0x100000>, 5437 <0x0 0x20600000 0x0 0x100000>; 5438 reg-names = "llcc0_base", 5439 "llcc1_base", 5440 "llcc2_base", 5441 "llcc3_base", 5442 "llcc4_base", 5443 "llcc5_base", 5444 "llcc6_base", 5445 "llcc7_base", 5446 "llcc8_base", 5447 "llcc9_base", 5448 "llcc10_base", 5449 "llcc11_base", 5450 "llcc_broadcast_base", 5451 "llcc_broadcast_and_base"; 5452 5453 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5454 }; 5455 5456 nsp_noc: interconnect@320c0000 { 5457 compatible = "qcom,glymur-nsp-noc"; 5458 reg = <0x0 0x320c0000 0x0 0x21280>; 5459 qcom,bcm-voters = <&apps_bcm_voter>; 5460 #interconnect-cells = <2>; 5461 }; 5462 5463 imem: sram@81e08000 { 5464 compatible = "mmio-sram"; 5465 reg = <0x0 0x81e08600 0x0 0x300>; 5466 5467 #address-cells = <1>; 5468 #size-cells = <1>; 5469 ranges = <0x0 0x0 0x81e08600 0x300>; 5470 5471 cpu_scp_lpri0: scp-sram-section@0 { 5472 compatible = "arm,scmi-shmem"; 5473 reg = <0x0 0x180>; 5474 }; 5475 5476 cpu_scp_lpri1: scp-sram-section@180 { 5477 compatible = "arm,scmi-shmem"; 5478 reg = <0x180 0x180>; 5479 }; 5480 }; 5481 }; 5482 5483 timer { 5484 compatible = "arm,armv8-timer"; 5485 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5486 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5487 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5488 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 5489 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 5490 }; 5491 5492 thermal_zones: thermal-zones { 5493 aoss-0-thermal { 5494 thermal-sensors = <&tsens0 0>; 5495 5496 trips { 5497 aoss-0-critical { 5498 temperature = <115000>; 5499 hysteresis = <1000>; 5500 type = "critical"; 5501 }; 5502 }; 5503 }; 5504 5505 cpu-0-0-0-thermal { 5506 thermal-sensors = <&tsens0 1>; 5507 5508 trips { 5509 cpu-0-0-0-critical { 5510 temperature = <115000>; 5511 hysteresis = <1000>; 5512 type = "critical"; 5513 }; 5514 }; 5515 }; 5516 5517 cpu-0-0-1-thermal { 5518 thermal-sensors = <&tsens0 2>; 5519 5520 trips { 5521 cpu-0-0-1-critical { 5522 temperature = <115000>; 5523 hysteresis = <1000>; 5524 type = "critical"; 5525 }; 5526 }; 5527 }; 5528 5529 cpu-0-1-0-thermal { 5530 thermal-sensors = <&tsens0 3>; 5531 5532 trips { 5533 cpu-0-1-0-critical { 5534 temperature = <115000>; 5535 hysteresis = <1000>; 5536 type = "critical"; 5537 }; 5538 }; 5539 }; 5540 5541 cpu-0-1-1-thermal { 5542 thermal-sensors = <&tsens0 4>; 5543 5544 trips { 5545 cpu-0-1-1-critical { 5546 temperature = <115000>; 5547 hysteresis = <1000>; 5548 type = "critical"; 5549 }; 5550 }; 5551 }; 5552 5553 cpu-0-2-0-thermal { 5554 thermal-sensors = <&tsens0 5>; 5555 5556 trips { 5557 cpu-0-2-0-critical { 5558 temperature = <115000>; 5559 hysteresis = <1000>; 5560 type = "critical"; 5561 }; 5562 }; 5563 }; 5564 5565 cpu-0-2-1-thermal { 5566 thermal-sensors = <&tsens0 6>; 5567 5568 trips { 5569 cpu-0-2-1-critical { 5570 temperature = <115000>; 5571 hysteresis = <1000>; 5572 type = "critical"; 5573 }; 5574 }; 5575 }; 5576 5577 cpu-0-3-0-thermal { 5578 thermal-sensors = <&tsens0 7>; 5579 5580 trips { 5581 cpu-0-3-0-critical { 5582 temperature = <115000>; 5583 hysteresis = <1000>; 5584 type = "critical"; 5585 }; 5586 }; 5587 }; 5588 5589 cpu-0-3-1-thermal { 5590 thermal-sensors = <&tsens0 8>; 5591 5592 trips { 5593 cpu-0-3-1-critical { 5594 temperature = <115000>; 5595 hysteresis = <1000>; 5596 type = "critical"; 5597 }; 5598 }; 5599 }; 5600 5601 cpu-0-4-0-thermal { 5602 thermal-sensors = <&tsens0 9>; 5603 5604 trips { 5605 cpu-0-4-0-critical { 5606 temperature = <115000>; 5607 hysteresis = <1000>; 5608 type = "critical"; 5609 }; 5610 }; 5611 }; 5612 5613 cpu-0-4-1-thermal { 5614 thermal-sensors = <&tsens0 10>; 5615 5616 trips { 5617 cpu-0-4-1-critical { 5618 temperature = <115000>; 5619 hysteresis = <1000>; 5620 type = "critical"; 5621 }; 5622 }; 5623 }; 5624 5625 cpu-0-5-0-thermal { 5626 thermal-sensors = <&tsens0 11>; 5627 5628 trips { 5629 cpu-0-5-0-critical { 5630 temperature = <115000>; 5631 hysteresis = <1000>; 5632 type = "critical"; 5633 }; 5634 }; 5635 }; 5636 5637 cpu-0-5-1-thermal { 5638 thermal-sensors = <&tsens0 12>; 5639 5640 trips { 5641 cpu-0-5-1-critical { 5642 temperature = <115000>; 5643 hysteresis = <1000>; 5644 type = "critical"; 5645 }; 5646 }; 5647 }; 5648 5649 aoss-1-thermal { 5650 thermal-sensors = <&tsens1 0>; 5651 5652 trips { 5653 aoss-1-critical { 5654 temperature = <115000>; 5655 hysteresis = <1000>; 5656 type = "critical"; 5657 }; 5658 }; 5659 }; 5660 5661 cpullc-0-0-thermal { 5662 thermal-sensors = <&tsens1 1>; 5663 5664 trips { 5665 cpullc-0-0-critical { 5666 temperature = <115000>; 5667 hysteresis = <1000>; 5668 type = "critical"; 5669 }; 5670 }; 5671 }; 5672 5673 cpullc-0-1-thermal { 5674 thermal-sensors = <&tsens1 2>; 5675 5676 trips { 5677 cpullc-0-1-critical { 5678 temperature = <115000>; 5679 hysteresis = <1000>; 5680 type = "critical"; 5681 }; 5682 }; 5683 }; 5684 5685 qmx-0-0-thermal { 5686 thermal-sensors = <&tsens1 3>; 5687 5688 trips { 5689 qmx-0-0-critical { 5690 temperature = <115000>; 5691 hysteresis = <1000>; 5692 type = "critical"; 5693 }; 5694 }; 5695 }; 5696 5697 qmx-0-1-thermal { 5698 thermal-sensors = <&tsens1 4>; 5699 5700 trips { 5701 qmx-0-1-critical { 5702 temperature = <115000>; 5703 hysteresis = <1000>; 5704 type = "critical"; 5705 }; 5706 }; 5707 }; 5708 5709 qmx-0-2-thermal { 5710 thermal-sensors = <&tsens1 5>; 5711 5712 trips { 5713 qmx-0-2-critical { 5714 temperature = <115000>; 5715 hysteresis = <1000>; 5716 type = "critical"; 5717 }; 5718 }; 5719 }; 5720 5721 ddr-0-thermal { 5722 thermal-sensors = <&tsens1 6>; 5723 5724 trips { 5725 ddr-0-critical { 5726 temperature = <115000>; 5727 hysteresis = <1000>; 5728 type = "critical"; 5729 }; 5730 }; 5731 }; 5732 5733 video-0-thermal { 5734 thermal-sensors = <&tsens1 7>; 5735 5736 trips { 5737 video-0-critical { 5738 temperature = <115000>; 5739 hysteresis = <1000>; 5740 type = "critical"; 5741 }; 5742 }; 5743 }; 5744 5745 video-1-thermal { 5746 thermal-sensors = <&tsens1 8>; 5747 5748 trips { 5749 video-1-critical { 5750 temperature = <115000>; 5751 hysteresis = <1000>; 5752 type = "critical"; 5753 }; 5754 }; 5755 }; 5756 5757 aoss-2-thermal { 5758 thermal-sensors = <&tsens2 0>; 5759 5760 trips { 5761 aoss-2-critical { 5762 temperature = <115000>; 5763 hysteresis = <1000>; 5764 type = "critical"; 5765 }; 5766 }; 5767 }; 5768 5769 cpu-1-0-0-thermal { 5770 thermal-sensors = <&tsens2 1>; 5771 5772 trips { 5773 cpu-1-0-0-critical { 5774 temperature = <115000>; 5775 hysteresis = <1000>; 5776 type = "critical"; 5777 }; 5778 }; 5779 }; 5780 5781 cpu-1-0-1-thermal { 5782 thermal-sensors = <&tsens2 2>; 5783 5784 trips { 5785 cpu-1-0-1-critical { 5786 temperature = <115000>; 5787 hysteresis = <1000>; 5788 type = "critical"; 5789 }; 5790 }; 5791 }; 5792 5793 cpu-1-1-0-thermal { 5794 thermal-sensors = <&tsens2 3>; 5795 5796 trips { 5797 cpu-1-1-0-critical { 5798 temperature = <115000>; 5799 hysteresis = <1000>; 5800 type = "critical"; 5801 }; 5802 }; 5803 }; 5804 5805 cpu-1-1-1-thermal { 5806 thermal-sensors = <&tsens2 4>; 5807 5808 trips { 5809 cpu-1-1-1-critical { 5810 temperature = <115000>; 5811 hysteresis = <1000>; 5812 type = "critical"; 5813 }; 5814 }; 5815 }; 5816 5817 cpu-1-2-0-thermal { 5818 thermal-sensors = <&tsens2 5>; 5819 5820 trips { 5821 cpu-1-2-0-critical { 5822 temperature = <115000>; 5823 hysteresis = <1000>; 5824 type = "critical"; 5825 }; 5826 }; 5827 }; 5828 5829 cpu-1-2-1-thermal { 5830 thermal-sensors = <&tsens2 6>; 5831 5832 trips { 5833 cpu-1-2-1-critical { 5834 temperature = <115000>; 5835 hysteresis = <1000>; 5836 type = "critical"; 5837 }; 5838 }; 5839 }; 5840 5841 cpu-1-3-0-thermal { 5842 thermal-sensors = <&tsens2 7>; 5843 5844 trips { 5845 cpu-1-3-0-critical { 5846 temperature = <115000>; 5847 hysteresis = <1000>; 5848 type = "critical"; 5849 }; 5850 }; 5851 }; 5852 5853 cpu-1-3-1-thermal { 5854 thermal-sensors = <&tsens2 8>; 5855 5856 trips { 5857 cpu-1-3-1-critical { 5858 temperature = <115000>; 5859 hysteresis = <1000>; 5860 type = "critical"; 5861 }; 5862 }; 5863 }; 5864 5865 cpu-1-4-0-thermal { 5866 thermal-sensors = <&tsens2 9>; 5867 5868 trips { 5869 cpu-1-4-0-critical { 5870 temperature = <115000>; 5871 hysteresis = <1000>; 5872 type = "critical"; 5873 }; 5874 }; 5875 }; 5876 5877 cpu-1-4-1-thermal { 5878 thermal-sensors = <&tsens2 10>; 5879 5880 trips { 5881 cpu-1-4-1-critical { 5882 temperature = <115000>; 5883 hysteresis = <1000>; 5884 type = "critical"; 5885 }; 5886 }; 5887 }; 5888 5889 cpu-1-5-0-thermal { 5890 thermal-sensors = <&tsens2 11>; 5891 5892 trips { 5893 cpu-1-5-0-critical { 5894 temperature = <115000>; 5895 hysteresis = <1000>; 5896 type = "critical"; 5897 }; 5898 }; 5899 }; 5900 5901 cpu-1-5-1-thermal { 5902 thermal-sensors = <&tsens2 12>; 5903 5904 trips { 5905 cpu-1-5-1-critical { 5906 temperature = <115000>; 5907 hysteresis = <1000>; 5908 type = "critical"; 5909 }; 5910 }; 5911 }; 5912 5913 aoss-3-thermal { 5914 thermal-sensors = <&tsens3 0>; 5915 5916 trips { 5917 aoss-3-critical { 5918 temperature = <115000>; 5919 hysteresis = <1000>; 5920 type = "critical"; 5921 }; 5922 }; 5923 }; 5924 5925 cpullc-1-0-thermal { 5926 thermal-sensors = <&tsens3 1>; 5927 5928 trips { 5929 cpullc-1-0-critical { 5930 temperature = <115000>; 5931 hysteresis = <1000>; 5932 type = "critical"; 5933 }; 5934 }; 5935 }; 5936 5937 cpullc-1-1-thermal { 5938 thermal-sensors = <&tsens3 2>; 5939 5940 trips { 5941 cpullc-1-1-critical { 5942 temperature = <115000>; 5943 hysteresis = <1000>; 5944 type = "critical"; 5945 }; 5946 }; 5947 }; 5948 5949 qmx-1-0-thermal { 5950 thermal-sensors = <&tsens3 3>; 5951 5952 trips { 5953 qmx-1-0-critical { 5954 temperature = <115000>; 5955 hysteresis = <1000>; 5956 type = "critical"; 5957 }; 5958 }; 5959 }; 5960 5961 qmx-1-1-thermal { 5962 thermal-sensors = <&tsens3 4>; 5963 5964 trips { 5965 qmx-1-1-critical { 5966 temperature = <115000>; 5967 hysteresis = <1000>; 5968 type = "critical"; 5969 }; 5970 }; 5971 }; 5972 5973 qmx-1-2-thermal { 5974 thermal-sensors = <&tsens3 5>; 5975 5976 trips { 5977 qmx-1-2-critical { 5978 temperature = <115000>; 5979 hysteresis = <1000>; 5980 type = "critical"; 5981 }; 5982 }; 5983 }; 5984 5985 qmx-1-3-thermal { 5986 thermal-sensors = <&tsens3 6>; 5987 5988 trips { 5989 qmx-1-3-critical { 5990 temperature = <115000>; 5991 hysteresis = <1000>; 5992 type = "critical"; 5993 }; 5994 }; 5995 }; 5996 5997 qmx-1-4-thermal { 5998 thermal-sensors = <&tsens3 7>; 5999 6000 trips { 6001 qmx-1-4-critical { 6002 temperature = <115000>; 6003 hysteresis = <1000>; 6004 type = "critical"; 6005 }; 6006 }; 6007 }; 6008 6009 aoss-4-thermal { 6010 thermal-sensors = <&tsens4 0>; 6011 6012 trips { 6013 aoss-4-critical { 6014 temperature = <115000>; 6015 hysteresis = <1000>; 6016 type = "critical"; 6017 }; 6018 }; 6019 }; 6020 6021 cpu-2-0-0-thermal { 6022 thermal-sensors = <&tsens4 1>; 6023 6024 trips { 6025 cpu-2-0-0-critical { 6026 temperature = <115000>; 6027 hysteresis = <1000>; 6028 type = "critical"; 6029 }; 6030 }; 6031 }; 6032 6033 cpu-2-0-1-thermal { 6034 thermal-sensors = <&tsens4 2>; 6035 6036 trips { 6037 cpu-2-0-1-critical { 6038 temperature = <115000>; 6039 hysteresis = <1000>; 6040 type = "critical"; 6041 }; 6042 }; 6043 }; 6044 6045 cpu-2-1-0-thermal { 6046 thermal-sensors = <&tsens4 3>; 6047 6048 trips { 6049 cpu-2-1-0-critical { 6050 temperature = <115000>; 6051 hysteresis = <1000>; 6052 type = "critical"; 6053 }; 6054 }; 6055 }; 6056 6057 cpu-2-1-1-thermal { 6058 thermal-sensors = <&tsens4 4>; 6059 6060 trips { 6061 cpu-2-1-1-critical { 6062 temperature = <115000>; 6063 hysteresis = <1000>; 6064 type = "critical"; 6065 }; 6066 }; 6067 }; 6068 6069 cpu-2-2-0-thermal { 6070 thermal-sensors = <&tsens4 5>; 6071 6072 trips { 6073 cpu-2-2-0-critical { 6074 temperature = <115000>; 6075 hysteresis = <1000>; 6076 type = "critical"; 6077 }; 6078 }; 6079 }; 6080 6081 cpu-2-2-1-thermal { 6082 thermal-sensors = <&tsens4 6>; 6083 6084 trips { 6085 cpu-2-2-1-critical { 6086 temperature = <115000>; 6087 hysteresis = <1000>; 6088 type = "critical"; 6089 }; 6090 }; 6091 }; 6092 6093 cpu-2-3-0-thermal { 6094 thermal-sensors = <&tsens4 7>; 6095 6096 trips { 6097 cpu-2-3-0-critical { 6098 temperature = <115000>; 6099 hysteresis = <1000>; 6100 type = "critical"; 6101 }; 6102 }; 6103 }; 6104 6105 cpu-2-3-1-thermal { 6106 thermal-sensors = <&tsens4 8>; 6107 6108 trips { 6109 cpu-2-3-1-critical { 6110 temperature = <115000>; 6111 hysteresis = <1000>; 6112 type = "critical"; 6113 }; 6114 }; 6115 }; 6116 6117 cpu-2-4-0-thermal { 6118 thermal-sensors = <&tsens4 9>; 6119 6120 trips { 6121 cpu-2-4-0-critical { 6122 temperature = <115000>; 6123 hysteresis = <1000>; 6124 type = "critical"; 6125 }; 6126 }; 6127 }; 6128 6129 cpu-2-4-1-thermal { 6130 thermal-sensors = <&tsens4 10>; 6131 6132 trips { 6133 cpu-2-4-1-critical { 6134 temperature = <115000>; 6135 hysteresis = <1000>; 6136 type = "critical"; 6137 }; 6138 }; 6139 }; 6140 6141 cpu-2-5-0-thermal { 6142 thermal-sensors = <&tsens4 11>; 6143 6144 trips { 6145 cpu-2-5-0-critical { 6146 temperature = <115000>; 6147 hysteresis = <1000>; 6148 type = "critical"; 6149 }; 6150 }; 6151 }; 6152 6153 cpu-2-5-1-thermal { 6154 thermal-sensors = <&tsens4 12>; 6155 6156 trips { 6157 cpu-2-5-1-critical { 6158 temperature = <115000>; 6159 hysteresis = <1000>; 6160 type = "critical"; 6161 }; 6162 }; 6163 }; 6164 6165 aoss-5-thermal { 6166 thermal-sensors = <&tsens5 0>; 6167 6168 trips { 6169 aoss-5-critical { 6170 temperature = <115000>; 6171 hysteresis = <1000>; 6172 type = "critical"; 6173 }; 6174 }; 6175 }; 6176 6177 cpullc-2-0-thermal { 6178 thermal-sensors = <&tsens5 1>; 6179 6180 trips { 6181 cpullc-2-0-critical { 6182 temperature = <115000>; 6183 hysteresis = <1000>; 6184 type = "critical"; 6185 }; 6186 }; 6187 }; 6188 6189 cpuillc-2-1-thermal { 6190 thermal-sensors = <&tsens5 2>; 6191 6192 trips { 6193 cpullc-2-1-critical { 6194 temperature = <115000>; 6195 hysteresis = <1000>; 6196 type = "critical"; 6197 }; 6198 }; 6199 }; 6200 6201 qmx-2-0-thermal { 6202 thermal-sensors = <&tsens5 3>; 6203 6204 trips { 6205 qmx-2-0-critical { 6206 temperature = <115000>; 6207 hysteresis = <1000>; 6208 type = "critical"; 6209 }; 6210 }; 6211 }; 6212 6213 qmx-2-1-thermal { 6214 thermal-sensors = <&tsens5 4>; 6215 6216 trips { 6217 qmx-2-1-critical { 6218 temperature = <115000>; 6219 hysteresis = <1000>; 6220 type = "critical"; 6221 }; 6222 }; 6223 }; 6224 6225 qmx-2-2-thermal { 6226 thermal-sensors = <&tsens5 5>; 6227 6228 trips { 6229 qmx-2-2-critical { 6230 temperature = <115000>; 6231 hysteresis = <1000>; 6232 type = "critical"; 6233 }; 6234 }; 6235 }; 6236 6237 qmx-2-3-thermal { 6238 thermal-sensors = <&tsens5 6>; 6239 6240 trips { 6241 qmx-2-3-critical { 6242 temperature = <115000>; 6243 hysteresis = <1000>; 6244 type = "critical"; 6245 }; 6246 }; 6247 }; 6248 6249 qmx-2-4-thermal { 6250 thermal-sensors = <&tsens5 7>; 6251 6252 trips { 6253 qmx-2-4-critical { 6254 temperature = <115000>; 6255 hysteresis = <1000>; 6256 type = "critical"; 6257 }; 6258 }; 6259 }; 6260 6261 aoss-6-thermal { 6262 thermal-sensors = <&tsens6 0>; 6263 6264 trips { 6265 aoss-6-critical { 6266 temperature = <115000>; 6267 hysteresis = <1000>; 6268 type = "critical"; 6269 }; 6270 }; 6271 }; 6272 6273 nsphvx-0-thermal { 6274 thermal-sensors = <&tsens6 1>; 6275 6276 trips { 6277 nsphvx-0-critical { 6278 temperature = <115000>; 6279 hysteresis = <1000>; 6280 type = "critical"; 6281 }; 6282 }; 6283 }; 6284 6285 nsphvx-1-thermal { 6286 thermal-sensors = <&tsens6 2>; 6287 6288 trips { 6289 nsphvx-1-critical { 6290 temperature = <115000>; 6291 hysteresis = <1000>; 6292 type = "critical"; 6293 }; 6294 }; 6295 }; 6296 6297 nsphvx-2-thermal { 6298 thermal-sensors = <&tsens6 3>; 6299 6300 trips { 6301 nsphvx-2-critical { 6302 temperature = <115000>; 6303 hysteresis = <1000>; 6304 type = "critical"; 6305 }; 6306 }; 6307 }; 6308 6309 nsphvx-3-thermal { 6310 thermal-sensors = <&tsens6 4>; 6311 6312 trips { 6313 nsphvx-3-critical { 6314 temperature = <115000>; 6315 hysteresis = <1000>; 6316 type = "critical"; 6317 }; 6318 }; 6319 }; 6320 6321 nsphmx-0-thermal { 6322 thermal-sensors = <&tsens6 5>; 6323 6324 trips { 6325 nsphmx-0-critical { 6326 temperature = <115000>; 6327 hysteresis = <1000>; 6328 type = "critical"; 6329 }; 6330 }; 6331 }; 6332 6333 nsphmx-1-thermal { 6334 thermal-sensors = <&tsens6 6>; 6335 6336 trips { 6337 nsphmx-1-critical { 6338 temperature = <115000>; 6339 hysteresis = <1000>; 6340 type = "critical"; 6341 }; 6342 }; 6343 }; 6344 6345 nsphmx-2-thermal { 6346 thermal-sensors = <&tsens6 7>; 6347 6348 trips { 6349 nsphmx-2-critical { 6350 temperature = <115000>; 6351 hysteresis = <1000>; 6352 type = "critical"; 6353 }; 6354 }; 6355 }; 6356 6357 nsphmx-3-thermal { 6358 thermal-sensors = <&tsens6 8>; 6359 6360 trips { 6361 nsphmx-3-critical { 6362 temperature = <115000>; 6363 hysteresis = <1000>; 6364 type = "critical"; 6365 }; 6366 }; 6367 }; 6368 6369 camera-0-thermal { 6370 thermal-sensors = <&tsens6 9>; 6371 6372 trips { 6373 camera-0-critical { 6374 temperature = <115000>; 6375 hysteresis = <1000>; 6376 type = "critical"; 6377 }; 6378 }; 6379 }; 6380 6381 camera-1-thermal { 6382 thermal-sensors = <&tsens6 10>; 6383 6384 trips { 6385 camera-1-critical { 6386 temperature = <115000>; 6387 hysteresis = <1000>; 6388 type = "critical"; 6389 }; 6390 }; 6391 }; 6392 6393 ddr-1-thermal { 6394 thermal-sensors = <&tsens6 11>; 6395 6396 trips { 6397 ddr-1-critical { 6398 temperature = <115000>; 6399 hysteresis = <1000>; 6400 type = "critical"; 6401 }; 6402 }; 6403 }; 6404 6405 ddr-2-thermal { 6406 thermal-sensors = <&tsens6 12>; 6407 6408 trips { 6409 ddr-2-critical { 6410 temperature = <115000>; 6411 hysteresis = <1000>; 6412 type = "critical"; 6413 }; 6414 }; 6415 }; 6416 6417 aoss-7-thermal { 6418 thermal-sensors = <&tsens7 0>; 6419 6420 trips { 6421 aoss-7-critical { 6422 temperature = <115000>; 6423 hysteresis = <1000>; 6424 type = "critical"; 6425 }; 6426 }; 6427 }; 6428 6429 gpu-0-0-thermal { 6430 thermal-sensors = <&tsens7 1>; 6431 6432 trips { 6433 trip-point0 { 6434 temperature = <90000>; 6435 hysteresis = <5000>; 6436 type = "hot"; 6437 }; 6438 6439 gpu-0-0-critical { 6440 temperature = <115000>; 6441 hysteresis = <1000>; 6442 type = "critical"; 6443 }; 6444 }; 6445 }; 6446 6447 gpu-0-1-thermal { 6448 thermal-sensors = <&tsens7 2>; 6449 6450 trips { 6451 trip-point0 { 6452 temperature = <90000>; 6453 hysteresis = <5000>; 6454 type = "hot"; 6455 }; 6456 6457 gpu-0-1-critical { 6458 temperature = <115000>; 6459 hysteresis = <1000>; 6460 type = "critical"; 6461 }; 6462 }; 6463 }; 6464 6465 gpu-0-2-thermal { 6466 thermal-sensors = <&tsens7 3>; 6467 6468 trips { 6469 trip-point0 { 6470 temperature = <90000>; 6471 hysteresis = <5000>; 6472 type = "hot"; 6473 }; 6474 6475 gpu-0-2-critical { 6476 temperature = <115000>; 6477 hysteresis = <1000>; 6478 type = "critical"; 6479 }; 6480 }; 6481 }; 6482 6483 gpu-1-0-thermal { 6484 thermal-sensors = <&tsens7 4>; 6485 6486 trips { 6487 trip-point0 { 6488 temperature = <90000>; 6489 hysteresis = <5000>; 6490 type = "hot"; 6491 }; 6492 6493 gpu-1-0-critical { 6494 temperature = <115000>; 6495 hysteresis = <1000>; 6496 type = "critical"; 6497 }; 6498 }; 6499 }; 6500 6501 gpu-1-1-thermal { 6502 thermal-sensors = <&tsens7 5>; 6503 6504 trips { 6505 trip-point0 { 6506 temperature = <90000>; 6507 hysteresis = <5000>; 6508 type = "hot"; 6509 }; 6510 6511 gpu-1-1-critical { 6512 temperature = <115000>; 6513 hysteresis = <1000>; 6514 type = "critical"; 6515 }; 6516 }; 6517 }; 6518 6519 gpu-1-2-thermal { 6520 thermal-sensors = <&tsens7 6>; 6521 6522 trips { 6523 trip-point0 { 6524 temperature = <90000>; 6525 hysteresis = <5000>; 6526 type = "hot"; 6527 }; 6528 6529 gpu-1-2-critical { 6530 temperature = <115000>; 6531 hysteresis = <1000>; 6532 type = "critical"; 6533 }; 6534 }; 6535 }; 6536 6537 gpu-2-0-thermal { 6538 thermal-sensors = <&tsens7 7>; 6539 6540 trips { 6541 trip-point0 { 6542 temperature = <90000>; 6543 hysteresis = <5000>; 6544 type = "hot"; 6545 }; 6546 6547 gpu-2-0-critical { 6548 temperature = <115000>; 6549 hysteresis = <1000>; 6550 type = "critical"; 6551 }; 6552 }; 6553 }; 6554 6555 gpu-2-1-thermal { 6556 thermal-sensors = <&tsens7 8>; 6557 6558 trips { 6559 trip-point0 { 6560 temperature = <90000>; 6561 hysteresis = <5000>; 6562 type = "hot"; 6563 }; 6564 6565 gpu-2-1-critical { 6566 temperature = <115000>; 6567 hysteresis = <1000>; 6568 type = "critical"; 6569 }; 6570 }; 6571 }; 6572 6573 gpu-2-2-thermal { 6574 thermal-sensors = <&tsens7 9>; 6575 6576 trips { 6577 trip-point0 { 6578 temperature = <90000>; 6579 hysteresis = <5000>; 6580 type = "hot"; 6581 }; 6582 6583 gpu-2-2-critical { 6584 temperature = <115000>; 6585 hysteresis = <1000>; 6586 type = "critical"; 6587 }; 6588 }; 6589 }; 6590 6591 gpu-3-0-thermal { 6592 thermal-sensors = <&tsens7 10>; 6593 6594 trips { 6595 trip-point0 { 6596 temperature = <90000>; 6597 hysteresis = <5000>; 6598 type = "hot"; 6599 }; 6600 6601 gpu-3-0-critical { 6602 temperature = <115000>; 6603 hysteresis = <1000>; 6604 type = "critical"; 6605 }; 6606 }; 6607 }; 6608 6609 gpu-3-1-thermal { 6610 thermal-sensors = <&tsens7 11>; 6611 6612 trips { 6613 trip-point0 { 6614 temperature = <90000>; 6615 hysteresis = <5000>; 6616 type = "hot"; 6617 }; 6618 6619 gpu-3-1-critical { 6620 temperature = <115000>; 6621 hysteresis = <1000>; 6622 type = "critical"; 6623 }; 6624 }; 6625 }; 6626 6627 gpu-3-2-thermal { 6628 thermal-sensors = <&tsens7 12>; 6629 6630 trips { 6631 trip-point0 { 6632 temperature = <90000>; 6633 hysteresis = <5000>; 6634 type = "hot"; 6635 }; 6636 6637 gpu-3-2-critical { 6638 temperature = <115000>; 6639 hysteresis = <1000>; 6640 type = "critical"; 6641 }; 6642 }; 6643 }; 6644 6645 gpuss-0-thermal { 6646 thermal-sensors = <&tsens7 13>; 6647 6648 trips { 6649 trip-point0 { 6650 temperature = <90000>; 6651 hysteresis = <5000>; 6652 type = "hot"; 6653 }; 6654 6655 gpuss-0-critical { 6656 temperature = <115000>; 6657 hysteresis = <1000>; 6658 type = "critical"; 6659 }; 6660 }; 6661 }; 6662 6663 gpuss-1-thermal { 6664 thermal-sensors = <&tsens7 14>; 6665 6666 trips { 6667 trip-point0 { 6668 temperature = <90000>; 6669 hysteresis = <5000>; 6670 type = "hot"; 6671 }; 6672 6673 gpuss-1-critical { 6674 temperature = <115000>; 6675 hysteresis = <1000>; 6676 type = "critical"; 6677 }; 6678 }; 6679 }; 6680 }; 6681}; 6682