xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt8195-demo.dts (revision d79603c2be61ca9d4fafa89ac7f5d8cc78568af4) 
16147314aSFabien Parent// SPDX-License-Identifier: (GPL-2.0 OR MIT)
26147314aSFabien Parent/*
36147314aSFabien Parent * Copyright (C) 2022 BayLibre, SAS.
46147314aSFabien Parent * Author: Fabien Parent <fparent@baylibre.com>
56147314aSFabien Parent */
66147314aSFabien Parent/dts-v1/;
76147314aSFabien Parent
86147314aSFabien Parent#include "mt8195.dtsi"
96147314aSFabien Parent#include "mt6359.dtsi"
106147314aSFabien Parent
116147314aSFabien Parent#include <dt-bindings/gpio/gpio.h>
126147314aSFabien Parent#include <dt-bindings/input/input.h>
136147314aSFabien Parent#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
146147314aSFabien Parent#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
156147314aSFabien Parent
166147314aSFabien Parent/ {
176147314aSFabien Parent	model = "MediaTek MT8195 demo board";
186147314aSFabien Parent	compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
196147314aSFabien Parent
206147314aSFabien Parent	aliases {
216147314aSFabien Parent		serial0 = &uart0;
226147314aSFabien Parent	};
236147314aSFabien Parent
246147314aSFabien Parent	chosen {
256147314aSFabien Parent		stdout-path = "serial0:921600n8";
266147314aSFabien Parent	};
276147314aSFabien Parent
286147314aSFabien Parent	firmware {
296147314aSFabien Parent		optee {
306147314aSFabien Parent			compatible = "linaro,optee-tz";
316147314aSFabien Parent			method = "smc";
326147314aSFabien Parent		};
336147314aSFabien Parent	};
346147314aSFabien Parent
356147314aSFabien Parent	gpio-keys {
366147314aSFabien Parent		compatible = "gpio-keys";
376147314aSFabien Parent		pinctrl-names = "default";
386147314aSFabien Parent		pinctrl-0 = <&gpio_keys_pins>;
396147314aSFabien Parent
406147314aSFabien Parent		key-0 {
416147314aSFabien Parent			gpios = <&pio 106 GPIO_ACTIVE_LOW>;
426147314aSFabien Parent			label = "volume_up";
436147314aSFabien Parent			linux,code = <KEY_VOLUMEUP>;
446147314aSFabien Parent			wakeup-source;
456147314aSFabien Parent			debounce-interval = <15>;
466147314aSFabien Parent		};
476147314aSFabien Parent	};
486147314aSFabien Parent
496147314aSFabien Parent	memory@40000000 {
506147314aSFabien Parent		device_type = "memory";
5125389c03SMacpaul Lin		reg = <0 0x40000000 0x2 0x00000000>;
526147314aSFabien Parent	};
536147314aSFabien Parent
546147314aSFabien Parent	reserved-memory {
556147314aSFabien Parent		#address-cells = <2>;
566147314aSFabien Parent		#size-cells = <2>;
576147314aSFabien Parent		ranges;
586147314aSFabien Parent
596cd2a30bSMacpaul Lin		/*
606cd2a30bSMacpaul Lin		 * 12 MiB reserved for OP-TEE (BL32)
616147314aSFabien Parent		 * +-----------------------+ 0x43e0_0000
626147314aSFabien Parent		 * |      SHMEM 2MiB       |
636147314aSFabien Parent		 * +-----------------------+ 0x43c0_0000
646147314aSFabien Parent		 * |        | TA_RAM  8MiB |
656147314aSFabien Parent		 * + TZDRAM +--------------+ 0x4340_0000
666147314aSFabien Parent		 * |        | TEE_RAM 2MiB |
676147314aSFabien Parent		 * +-----------------------+ 0x4320_0000
686147314aSFabien Parent		 */
696147314aSFabien Parent		optee_reserved: optee@43200000 {
706147314aSFabien Parent			no-map;
716147314aSFabien Parent			reg = <0 0x43200000 0 0x00c00000>;
726147314aSFabien Parent		};
736cd2a30bSMacpaul Lin
746cd2a30bSMacpaul Lin		scp_mem: memory@50000000 {
756cd2a30bSMacpaul Lin			compatible = "shared-dma-pool";
766cd2a30bSMacpaul Lin			reg = <0 0x50000000 0 0x2900000>;
776cd2a30bSMacpaul Lin			no-map;
786cd2a30bSMacpaul Lin		};
796cd2a30bSMacpaul Lin
806cd2a30bSMacpaul Lin		vpu_mem: memory@53000000 {
816cd2a30bSMacpaul Lin			compatible = "shared-dma-pool";
826cd2a30bSMacpaul Lin			reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
836cd2a30bSMacpaul Lin		};
846cd2a30bSMacpaul Lin
856cd2a30bSMacpaul Lin		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
866cd2a30bSMacpaul Lin		bl31_secmon_mem: memory@54600000 {
876cd2a30bSMacpaul Lin			no-map;
886cd2a30bSMacpaul Lin			reg = <0 0x54600000 0x0 0x200000>;
896cd2a30bSMacpaul Lin		};
906cd2a30bSMacpaul Lin
916cd2a30bSMacpaul Lin		snd_dma_mem: memory@60000000 {
926cd2a30bSMacpaul Lin			compatible = "shared-dma-pool";
936cd2a30bSMacpaul Lin			reg = <0 0x60000000 0 0x1100000>;
946cd2a30bSMacpaul Lin			no-map;
956cd2a30bSMacpaul Lin		};
966cd2a30bSMacpaul Lin
976cd2a30bSMacpaul Lin		apu_mem: memory@62000000 {
986cd2a30bSMacpaul Lin			compatible = "shared-dma-pool";
996cd2a30bSMacpaul Lin			reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
1006cd2a30bSMacpaul Lin		};
1016147314aSFabien Parent	};
1026147314aSFabien Parent};
1036147314aSFabien Parent
104c5fe37e8SBiao Huang&eth {
105c5fe37e8SBiao Huang	phy-mode = "rgmii-id";
106c5fe37e8SBiao Huang	phy-handle = <&ethernet_phy0>;
107c5fe37e8SBiao Huang	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
108c5fe37e8SBiao Huang	snps,reset-delays-us = <0 10000 80000>;
109c5fe37e8SBiao Huang	pinctrl-names = "default", "sleep";
110c5fe37e8SBiao Huang	pinctrl-0 = <&eth_default_pins>;
111c5fe37e8SBiao Huang	pinctrl-1 = <&eth_sleep_pins>;
112c5fe37e8SBiao Huang	status = "okay";
113c5fe37e8SBiao Huang
114c5fe37e8SBiao Huang	mdio {
115c5fe37e8SBiao Huang		ethernet_phy0: ethernet-phy@1 {
116c5fe37e8SBiao Huang			reg = <0x1>;
117c5fe37e8SBiao Huang		};
118c5fe37e8SBiao Huang	};
119c5fe37e8SBiao Huang};
120c5fe37e8SBiao Huang
1216147314aSFabien Parent&i2c6 {
1226147314aSFabien Parent	clock-frequency = <400000>;
1236147314aSFabien Parent	pinctrl-0 = <&i2c6_pins>;
1246147314aSFabien Parent	pinctrl-names = "default";
1256147314aSFabien Parent	status = "okay";
1266147314aSFabien Parent
1276147314aSFabien Parent	mt6360: pmic@34 {
1286147314aSFabien Parent		compatible = "mediatek,mt6360";
1296147314aSFabien Parent		reg = <0x34>;
1306147314aSFabien Parent		interrupt-controller;
13191adecf9SRob Herring		#interrupt-cells = <1>;
1326147314aSFabien Parent		interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
1336147314aSFabien Parent		interrupt-names = "IRQB";
1346147314aSFabien Parent
1356147314aSFabien Parent		charger {
1366147314aSFabien Parent			compatible = "mediatek,mt6360-chg";
1376147314aSFabien Parent			richtek,vinovp-microvolt = <14500000>;
1386147314aSFabien Parent
1396147314aSFabien Parent			otg_vbus_regulator: usb-otg-vbus-regulator {
1406147314aSFabien Parent				regulator-compatible = "usb-otg-vbus";
1416147314aSFabien Parent				regulator-name = "usb-otg-vbus";
1426147314aSFabien Parent				regulator-min-microvolt = <4425000>;
1436147314aSFabien Parent				regulator-max-microvolt = <5825000>;
1446147314aSFabien Parent			};
1456147314aSFabien Parent		};
1466147314aSFabien Parent
1476147314aSFabien Parent		regulator {
1486147314aSFabien Parent			compatible = "mediatek,mt6360-regulator";
1496147314aSFabien Parent			LDO_VIN3-supply = <&mt6360_buck2>;
1506147314aSFabien Parent
1516147314aSFabien Parent			mt6360_buck1: buck1 {
1526147314aSFabien Parent				regulator-compatible = "BUCK1";
1536147314aSFabien Parent				regulator-name = "mt6360,buck1";
1546147314aSFabien Parent				regulator-min-microvolt = <300000>;
1556147314aSFabien Parent				regulator-max-microvolt = <1300000>;
1566147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
1576147314aSFabien Parent							   MT6360_OPMODE_LP
1586147314aSFabien Parent							   MT6360_OPMODE_ULP>;
1596147314aSFabien Parent				regulator-always-on;
1606147314aSFabien Parent			};
1616147314aSFabien Parent
1626147314aSFabien Parent			mt6360_buck2: buck2 {
1636147314aSFabien Parent				regulator-compatible = "BUCK2";
1646147314aSFabien Parent				regulator-name = "mt6360,buck2";
1656147314aSFabien Parent				regulator-min-microvolt = <300000>;
1666147314aSFabien Parent				regulator-max-microvolt = <1300000>;
1676147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
1686147314aSFabien Parent							   MT6360_OPMODE_LP
1696147314aSFabien Parent							   MT6360_OPMODE_ULP>;
1706147314aSFabien Parent				regulator-always-on;
1716147314aSFabien Parent			};
1726147314aSFabien Parent
1736147314aSFabien Parent			mt6360_ldo1: ldo1 {
1746147314aSFabien Parent				regulator-compatible = "LDO1";
1756147314aSFabien Parent				regulator-name = "mt6360,ldo1";
1766147314aSFabien Parent				regulator-min-microvolt = <1200000>;
1776147314aSFabien Parent				regulator-max-microvolt = <3600000>;
1786147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
1796147314aSFabien Parent							   MT6360_OPMODE_LP>;
1806147314aSFabien Parent			};
1816147314aSFabien Parent
1826147314aSFabien Parent			mt6360_ldo2: ldo2 {
1836147314aSFabien Parent				regulator-compatible = "LDO2";
1846147314aSFabien Parent				regulator-name = "mt6360,ldo2";
1856147314aSFabien Parent				regulator-min-microvolt = <1200000>;
1866147314aSFabien Parent				regulator-max-microvolt = <3600000>;
1876147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
1886147314aSFabien Parent							   MT6360_OPMODE_LP>;
1896147314aSFabien Parent			};
1906147314aSFabien Parent
1916147314aSFabien Parent			mt6360_ldo3: ldo3 {
1926147314aSFabien Parent				regulator-compatible = "LDO3";
1936147314aSFabien Parent				regulator-name = "mt6360,ldo3";
1946147314aSFabien Parent				regulator-min-microvolt = <1200000>;
1956147314aSFabien Parent				regulator-max-microvolt = <3600000>;
1966147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
1976147314aSFabien Parent							   MT6360_OPMODE_LP>;
1986147314aSFabien Parent			};
1996147314aSFabien Parent
2006147314aSFabien Parent			mt6360_ldo5: ldo5 {
2016147314aSFabien Parent				regulator-compatible = "LDO5";
2026147314aSFabien Parent				regulator-name = "mt6360,ldo5";
2036147314aSFabien Parent				regulator-min-microvolt = <2700000>;
2046147314aSFabien Parent				regulator-max-microvolt = <3600000>;
2056147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
2066147314aSFabien Parent							   MT6360_OPMODE_LP>;
2076147314aSFabien Parent			};
2086147314aSFabien Parent
2096147314aSFabien Parent			mt6360_ldo6: ldo6 {
2106147314aSFabien Parent				regulator-compatible = "LDO6";
2116147314aSFabien Parent				regulator-name = "mt6360,ldo6";
2126147314aSFabien Parent				regulator-min-microvolt = <500000>;
2136147314aSFabien Parent				regulator-max-microvolt = <2100000>;
2146147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
2156147314aSFabien Parent							   MT6360_OPMODE_LP>;
2166147314aSFabien Parent			};
2176147314aSFabien Parent
2186147314aSFabien Parent			mt6360_ldo7: ldo7 {
2196147314aSFabien Parent				regulator-compatible = "LDO7";
2206147314aSFabien Parent				regulator-name = "mt6360,ldo7";
2216147314aSFabien Parent				regulator-min-microvolt = <500000>;
2226147314aSFabien Parent				regulator-max-microvolt = <2100000>;
2236147314aSFabien Parent				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
2246147314aSFabien Parent							   MT6360_OPMODE_LP>;
2256147314aSFabien Parent				regulator-always-on;
2266147314aSFabien Parent			};
2276147314aSFabien Parent		};
2286147314aSFabien Parent	};
2296147314aSFabien Parent};
2306147314aSFabien Parent
2316147314aSFabien Parent&mmc0 {
2326147314aSFabien Parent	status = "okay";
2336147314aSFabien Parent	pinctrl-names = "default", "state_uhs";
2346147314aSFabien Parent	pinctrl-0 = <&mmc0_default_pins>;
2356147314aSFabien Parent	pinctrl-1 = <&mmc0_uhs_pins>;
2366147314aSFabien Parent	bus-width = <8>;
2376147314aSFabien Parent	max-frequency = <200000000>;
2386147314aSFabien Parent	cap-mmc-highspeed;
2396147314aSFabien Parent	mmc-hs200-1_8v;
2406147314aSFabien Parent	mmc-hs400-1_8v;
2416147314aSFabien Parent	cap-mmc-hw-reset;
2426147314aSFabien Parent	no-sdio;
2436147314aSFabien Parent	no-sd;
2446147314aSFabien Parent	hs400-ds-delay = <0x14c11>;
2456147314aSFabien Parent	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
2466147314aSFabien Parent	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
2476147314aSFabien Parent	non-removable;
2486147314aSFabien Parent};
2496147314aSFabien Parent
2506147314aSFabien Parent&mmc1 {
2516147314aSFabien Parent	pinctrl-names = "default", "state_uhs";
2526147314aSFabien Parent	pinctrl-0 = <&mmc1_default_pins>;
2536147314aSFabien Parent	pinctrl-1 = <&mmc1_uhs_pins>;
2546147314aSFabien Parent	cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
2556147314aSFabien Parent	bus-width = <4>;
2566147314aSFabien Parent	max-frequency = <200000000>;
2576147314aSFabien Parent	cap-sd-highspeed;
2586147314aSFabien Parent	sd-uhs-sdr50;
2596147314aSFabien Parent	sd-uhs-sdr104;
2606147314aSFabien Parent	vmmc-supply = <&mt6360_ldo5>;
2616147314aSFabien Parent	vqmmc-supply = <&mt6360_ldo3>;
2626147314aSFabien Parent	status = "okay";
2636147314aSFabien Parent};
2646147314aSFabien Parent
2656147314aSFabien Parent&mt6359_vbbck_ldo_reg {
2666147314aSFabien Parent	regulator-always-on;
2676147314aSFabien Parent};
2686147314aSFabien Parent
2696147314aSFabien Parent&mt6359_vcore_buck_reg {
2706147314aSFabien Parent	regulator-always-on;
2716147314aSFabien Parent};
2726147314aSFabien Parent
2736147314aSFabien Parent&mt6359_vgpu11_buck_reg {
2746147314aSFabien Parent	regulator-always-on;
2756147314aSFabien Parent};
2766147314aSFabien Parent
2776147314aSFabien Parent&mt6359_vproc1_buck_reg {
2786147314aSFabien Parent	regulator-always-on;
2796147314aSFabien Parent};
2806147314aSFabien Parent
2816147314aSFabien Parent&mt6359_vproc2_buck_reg {
2826147314aSFabien Parent	regulator-always-on;
2836147314aSFabien Parent};
2846147314aSFabien Parent
2856147314aSFabien Parent&mt6359_vpu_buck_reg {
2866147314aSFabien Parent	regulator-always-on;
2876147314aSFabien Parent};
2886147314aSFabien Parent
2896147314aSFabien Parent&mt6359_vrf12_ldo_reg {
2906147314aSFabien Parent	regulator-always-on;
2916147314aSFabien Parent};
2926147314aSFabien Parent
2936147314aSFabien Parent&mt6359_vsram_md_ldo_reg {
2946147314aSFabien Parent	regulator-always-on;
2956147314aSFabien Parent};
2966147314aSFabien Parent
2976147314aSFabien Parent&mt6359_vsram_others_ldo_reg {
2986147314aSFabien Parent	regulator-always-on;
2996147314aSFabien Parent};
3006147314aSFabien Parent
3016147314aSFabien Parent&pio {
302c5fe37e8SBiao Huang	eth_default_pins: eth-default-pins {
303c5fe37e8SBiao Huang		pins-txd {
304c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
305c5fe37e8SBiao Huang				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
306c5fe37e8SBiao Huang				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
307c5fe37e8SBiao Huang				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
308*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
309c5fe37e8SBiao Huang		};
310c5fe37e8SBiao Huang		pins-cc {
311c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
312c5fe37e8SBiao Huang				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
313c5fe37e8SBiao Huang				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
314c5fe37e8SBiao Huang				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
315*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
316c5fe37e8SBiao Huang		};
317c5fe37e8SBiao Huang		pins-rxd {
318c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
319c5fe37e8SBiao Huang				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
320c5fe37e8SBiao Huang				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
321c5fe37e8SBiao Huang				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
322c5fe37e8SBiao Huang		};
323c5fe37e8SBiao Huang		pins-mdio {
324c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
325c5fe37e8SBiao Huang				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
326c5fe37e8SBiao Huang			input-enable;
327c5fe37e8SBiao Huang		};
328c5fe37e8SBiao Huang		pins-power {
329c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
330c5fe37e8SBiao Huang				 <PINMUX_GPIO92__FUNC_GPIO92>;
331c5fe37e8SBiao Huang			output-high;
332c5fe37e8SBiao Huang		};
333c5fe37e8SBiao Huang	};
334c5fe37e8SBiao Huang
335c5fe37e8SBiao Huang	eth_sleep_pins: eth-sleep-pins {
336c5fe37e8SBiao Huang		pins-txd {
337c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
338c5fe37e8SBiao Huang				 <PINMUX_GPIO78__FUNC_GPIO78>,
339c5fe37e8SBiao Huang				 <PINMUX_GPIO79__FUNC_GPIO79>,
340c5fe37e8SBiao Huang				 <PINMUX_GPIO80__FUNC_GPIO80>;
341c5fe37e8SBiao Huang		};
342c5fe37e8SBiao Huang		pins-cc {
343c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
344c5fe37e8SBiao Huang				 <PINMUX_GPIO88__FUNC_GPIO88>,
345c5fe37e8SBiao Huang				 <PINMUX_GPIO87__FUNC_GPIO87>,
346c5fe37e8SBiao Huang				 <PINMUX_GPIO86__FUNC_GPIO86>;
347c5fe37e8SBiao Huang		};
348c5fe37e8SBiao Huang		pins-rxd {
349c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
350c5fe37e8SBiao Huang				 <PINMUX_GPIO82__FUNC_GPIO82>,
351c5fe37e8SBiao Huang				 <PINMUX_GPIO83__FUNC_GPIO83>,
352c5fe37e8SBiao Huang				 <PINMUX_GPIO84__FUNC_GPIO84>;
353c5fe37e8SBiao Huang		};
354c5fe37e8SBiao Huang		pins-mdio {
355c5fe37e8SBiao Huang			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
356c5fe37e8SBiao Huang				 <PINMUX_GPIO90__FUNC_GPIO90>;
357c5fe37e8SBiao Huang			input-disable;
358c5fe37e8SBiao Huang			bias-disable;
359c5fe37e8SBiao Huang		};
360c5fe37e8SBiao Huang	};
361c5fe37e8SBiao Huang
3626147314aSFabien Parent	gpio_keys_pins: gpio-keys-pins {
3636147314aSFabien Parent		pins {
3646147314aSFabien Parent			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
3656147314aSFabien Parent			input-enable;
3666147314aSFabien Parent		};
3676147314aSFabien Parent	};
3686147314aSFabien Parent
3696147314aSFabien Parent	i2c6_pins: i2c6-pins {
3706147314aSFabien Parent		pins {
3716147314aSFabien Parent			pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
3726147314aSFabien Parent				 <PINMUX_GPIO26__FUNC_SCL6>;
3736147314aSFabien Parent			bias-pull-up;
3746147314aSFabien Parent		};
3756147314aSFabien Parent	};
3766147314aSFabien Parent
3776147314aSFabien Parent	mmc0_default_pins: mmc0-default-pins {
3786147314aSFabien Parent		pins-clk {
3796147314aSFabien Parent			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
380*d79603c2SAngeloGioacchino Del Regno			drive-strength = <6>;
3816147314aSFabien Parent			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
3826147314aSFabien Parent		};
3836147314aSFabien Parent
3846147314aSFabien Parent		pins-cmd-dat {
3856147314aSFabien Parent			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
3866147314aSFabien Parent				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
3876147314aSFabien Parent				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
3886147314aSFabien Parent				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
3896147314aSFabien Parent				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
3906147314aSFabien Parent				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
3916147314aSFabien Parent				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
3926147314aSFabien Parent				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
3936147314aSFabien Parent				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
3946147314aSFabien Parent			input-enable;
395*d79603c2SAngeloGioacchino Del Regno			drive-strength = <6>;
3966147314aSFabien Parent			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
3976147314aSFabien Parent		};
3986147314aSFabien Parent
3996147314aSFabien Parent		pins-rst {
4006147314aSFabien Parent			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
401*d79603c2SAngeloGioacchino Del Regno			drive-strength = <6>;
4026147314aSFabien Parent			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
4036147314aSFabien Parent		};
4046147314aSFabien Parent	};
4056147314aSFabien Parent
4066147314aSFabien Parent	mmc0_uhs_pins: mmc0-uhs-pins {
4076147314aSFabien Parent		pins-clk {
4086147314aSFabien Parent			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
409*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4106147314aSFabien Parent			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
4116147314aSFabien Parent		};
4126147314aSFabien Parent
4136147314aSFabien Parent		pins-cmd-dat {
4146147314aSFabien Parent			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
4156147314aSFabien Parent				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
4166147314aSFabien Parent				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
4176147314aSFabien Parent				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
4186147314aSFabien Parent				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
4196147314aSFabien Parent				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
4206147314aSFabien Parent				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
4216147314aSFabien Parent				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
4226147314aSFabien Parent				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
4236147314aSFabien Parent			input-enable;
424*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4256147314aSFabien Parent			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
4266147314aSFabien Parent		};
4276147314aSFabien Parent
4286147314aSFabien Parent		pins-ds {
4296147314aSFabien Parent			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
430*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4316147314aSFabien Parent			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
4326147314aSFabien Parent		};
4336147314aSFabien Parent
4346147314aSFabien Parent		pins-rst {
4356147314aSFabien Parent			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
436*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4376147314aSFabien Parent			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
4386147314aSFabien Parent		};
4396147314aSFabien Parent	};
4406147314aSFabien Parent
4416147314aSFabien Parent	mmc1_default_pins: mmc1-default-pins {
4426147314aSFabien Parent		pins-clk {
4436147314aSFabien Parent			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
444*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4456147314aSFabien Parent			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
4466147314aSFabien Parent		};
4476147314aSFabien Parent
4486147314aSFabien Parent		pins-cmd-dat {
4496147314aSFabien Parent			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
4506147314aSFabien Parent				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
4516147314aSFabien Parent				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
4526147314aSFabien Parent				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
4536147314aSFabien Parent				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
4546147314aSFabien Parent			input-enable;
455*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4566147314aSFabien Parent			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
4576147314aSFabien Parent		};
4586147314aSFabien Parent
4596147314aSFabien Parent		pins-insert {
4606147314aSFabien Parent			pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
4616147314aSFabien Parent			bias-pull-up;
4626147314aSFabien Parent		};
4636147314aSFabien Parent	};
4646147314aSFabien Parent
4656147314aSFabien Parent	mmc1_uhs_pins: mmc1-uhs-pins {
4666147314aSFabien Parent		pins-clk {
4676147314aSFabien Parent			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
468*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4696147314aSFabien Parent			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
4706147314aSFabien Parent		};
4716147314aSFabien Parent
4726147314aSFabien Parent		pins-cmd-dat {
4736147314aSFabien Parent			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
4746147314aSFabien Parent				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
4756147314aSFabien Parent				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
4766147314aSFabien Parent				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
4776147314aSFabien Parent				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
4786147314aSFabien Parent			input-enable;
479*d79603c2SAngeloGioacchino Del Regno			drive-strength = <8>;
4806147314aSFabien Parent			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
4816147314aSFabien Parent		};
4826147314aSFabien Parent	};
4836147314aSFabien Parent
4846147314aSFabien Parent	uart0_pins: uart0-pins {
4856147314aSFabien Parent		pins {
4866147314aSFabien Parent			pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
4876147314aSFabien Parent				 <PINMUX_GPIO99__FUNC_URXD0>;
4886147314aSFabien Parent		};
4896147314aSFabien Parent	};
4906147314aSFabien Parent
4916147314aSFabien Parent	uart1_pins: uart1-pins {
4926147314aSFabien Parent		pins {
4936147314aSFabien Parent			pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
4946147314aSFabien Parent				 <PINMUX_GPIO103__FUNC_URXD1>;
4956147314aSFabien Parent		};
4966147314aSFabien Parent	};
4976147314aSFabien Parent};
4986147314aSFabien Parent
4996147314aSFabien Parent
5006147314aSFabien Parent&pmic {
5016147314aSFabien Parent	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
5026147314aSFabien Parent};
5036147314aSFabien Parent
5046147314aSFabien Parent&uart0 {
5056147314aSFabien Parent	pinctrl-names = "default";
5066147314aSFabien Parent	pinctrl-0 = <&uart0_pins>;
5076147314aSFabien Parent	status = "okay";
5086147314aSFabien Parent};
5096147314aSFabien Parent
5107640d435SFabien Parent&uart1 {
5117640d435SFabien Parent	pinctrl-names = "default";
5127640d435SFabien Parent	pinctrl-0 = <&uart1_pins>;
5137640d435SFabien Parent	status = "okay";
5147640d435SFabien Parent};
5157640d435SFabien Parent
5166147314aSFabien Parent&u3phy0 {
5176147314aSFabien Parent	status = "okay";
5186147314aSFabien Parent};
5196147314aSFabien Parent
5206147314aSFabien Parent&u3phy1 {
5216147314aSFabien Parent	status = "okay";
5226147314aSFabien Parent};
5236147314aSFabien Parent
5246147314aSFabien Parent&u3phy2 {
5256147314aSFabien Parent	status = "okay";
5266147314aSFabien Parent};
5276147314aSFabien Parent
5286147314aSFabien Parent&u3phy3 {
5296147314aSFabien Parent	status = "okay";
5306147314aSFabien Parent};
5316147314aSFabien Parent
532795d5f0cSAngeloGioacchino Del Regno&ssusb0 {
5336147314aSFabien Parent	vusb33-supply = <&mt6359_vusb_ldo_reg>;
534795d5f0cSAngeloGioacchino Del Regno	status = "okay";
535795d5f0cSAngeloGioacchino Del Regno};
536795d5f0cSAngeloGioacchino Del Regno
537795d5f0cSAngeloGioacchino Del Regno&ssusb2 {
538795d5f0cSAngeloGioacchino Del Regno	vusb33-supply = <&mt6359_vusb_ldo_reg>;
539795d5f0cSAngeloGioacchino Del Regno	status = "okay";
540795d5f0cSAngeloGioacchino Del Regno};
541795d5f0cSAngeloGioacchino Del Regno
542795d5f0cSAngeloGioacchino Del Regno&ssusb3 {
543795d5f0cSAngeloGioacchino Del Regno	vusb33-supply = <&mt6359_vusb_ldo_reg>;
544795d5f0cSAngeloGioacchino Del Regno	status = "okay";
545795d5f0cSAngeloGioacchino Del Regno};
546795d5f0cSAngeloGioacchino Del Regno
547795d5f0cSAngeloGioacchino Del Regno&xhci0 {
5486147314aSFabien Parent	vbus-supply = <&otg_vbus_regulator>;
5496147314aSFabien Parent	status = "okay";
5506147314aSFabien Parent};
5516147314aSFabien Parent
5526147314aSFabien Parent&xhci1 {
5536147314aSFabien Parent	vusb33-supply = <&mt6359_vusb_ldo_reg>;
5546147314aSFabien Parent	status = "okay";
5556147314aSFabien Parent};
5566147314aSFabien Parent
5576147314aSFabien Parent&xhci2 {
5586147314aSFabien Parent	status = "okay";
5596147314aSFabien Parent};
5606147314aSFabien Parent
5616147314aSFabien Parent&xhci3 {
5626147314aSFabien Parent	status = "okay";
5636147314aSFabien Parent};
564