1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5/dts-v1/; 6#include "mt8186.dtsi" 7#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/input/gpio-keys.h> 11#include <dt-bindings/regulator/mediatek,mt6397-regulator.h> 12 13/ { 14 aliases { 15 i2c0 = &i2c0; 16 i2c1 = &i2c1; 17 i2c2 = &i2c2; 18 i2c3 = &i2c3; 19 i2c5 = &i2c5; 20 mmc0 = &mmc0; 21 mmc1 = &mmc1; 22 serial0 = &uart0; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 /* The size should be filled in by the bootloader. */ 32 reg = <0 0x40000000 0 0>; 33 }; 34 35 backlight_lcd0: backlight-lcd0 { 36 compatible = "pwm-backlight"; 37 pwms = <&pwm0 0 500000>; 38 power-supply = <&ppvar_sys>; 39 enable-gpios = <&pio 152 0>; 40 brightness-levels = <0 1023>; 41 num-interpolated-steps = <1023>; 42 default-brightness-level = <576>; 43 }; 44 45 bt-sco { 46 compatible = "linux,bt-sco"; 47 #sound-dai-cells = <0>; 48 }; 49 50 dmic-codec { 51 compatible = "dmic-codec"; 52 #sound-dai-cells = <0>; 53 num-channels = <2>; 54 wakeup-delay-ms = <50>; 55 }; 56 57 gpio_keys: gpio-keys { 58 compatible = "gpio-keys"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pen_eject>; 61 62 pen_insert: pen-insert-switch { 63 label = "Pen Insert"; 64 /* Insert = low, eject = high */ 65 gpios = <&pio 18 GPIO_ACTIVE_LOW>; 66 wakeup-event-action = <EV_ACT_DEASSERTED>; 67 wakeup-source; 68 linux,code = <SW_PEN_INSERTED>; 69 linux,input-type = <EV_SW>; 70 }; 71 }; 72 73 pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx { 74 compatible = "regulator-fixed"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&en_pp1800_dpbrdg>; 77 gpios = <&pio 39 GPIO_ACTIVE_HIGH>; 78 regulator-name = "pp1800_dpbrdg_dx"; 79 enable-active-high; 80 vin-supply = <&mt6366_vio18_reg>; 81 }; 82 83 pp3300_disp_x: regulator-pp3300-disp-x { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&edp_panel_fixed_pins>; 87 gpios = <&pio 153 GPIO_ACTIVE_HIGH>; 88 regulator-name = "pp3300_disp_x"; 89 enable-active-high; 90 regulator-boot-on; 91 vin-supply = <&pp3300_z2>; 92 }; 93 94 /* system wide LDO 3.3V power rail */ 95 pp3300_z5: regulator-pp3300-ldo-z5 { 96 compatible = "regulator-fixed"; 97 regulator-name = "pp3300_ldo_z5"; 98 regulator-always-on; 99 regulator-boot-on; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 vin-supply = <&ppvar_sys>; 103 }; 104 105 /* separately switched 3.3V power rail */ 106 pp3300_s3: regulator-pp3300-s3 { 107 compatible = "regulator-fixed"; 108 regulator-name = "pp3300_s3"; 109 /* automatically sequenced by PMIC EXT_PMIC_EN2 */ 110 regulator-always-on; 111 regulator-boot-on; 112 vin-supply = <&pp3300_z2>; 113 }; 114 115 /* system wide 3.3V power rail */ 116 pp3300_z2: regulator-pp3300-z2 { 117 compatible = "regulator-fixed"; 118 regulator-name = "pp3300_z2"; 119 /* EN pin tied to pp4200_z2, which is controlled by EC */ 120 regulator-always-on; 121 regulator-boot-on; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <&ppvar_sys>; 125 }; 126 127 /* system wide 4.2V power rail */ 128 pp4200_z2: regulator-pp4200-z2 { 129 compatible = "regulator-fixed"; 130 regulator-name = "pp4200_z2"; 131 /* controlled by EC */ 132 regulator-always-on; 133 regulator-boot-on; 134 regulator-min-microvolt = <4200000>; 135 regulator-max-microvolt = <4200000>; 136 vin-supply = <&ppvar_sys>; 137 }; 138 139 /* system wide switching 5.0V power rail */ 140 pp5000_z2: regulator-pp5000-z2 { 141 compatible = "regulator-fixed"; 142 regulator-name = "pp5000_z2"; 143 /* controlled by EC */ 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 vin-supply = <&ppvar_sys>; 149 }; 150 151 /* system wide semi-regulated power rail from battery or USB */ 152 ppvar_sys: regulator-ppvar-sys { 153 compatible = "regulator-fixed"; 154 regulator-name = "ppvar_sys"; 155 regulator-always-on; 156 regulator-boot-on; 157 }; 158 159 reserved_memory: reserved-memory { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 ranges; 163 164 adsp_dma_mem: memory@61000000 { 165 compatible = "shared-dma-pool"; 166 reg = <0 0x61000000 0 0x100000>; 167 no-map; 168 }; 169 170 adsp_mem: memory@60000000 { 171 compatible = "shared-dma-pool"; 172 reg = <0 0x60000000 0 0x1000000>; 173 no-map; 174 }; 175 176 scp_mem: memory@50000000 { 177 compatible = "shared-dma-pool"; 178 reg = <0 0x50000000 0 0x10a0000>; 179 no-map; 180 }; 181 }; 182 183 sound: sound { 184 compatible = "mediatek,mt8186-mt6366-rt1019-rt5682s-sound"; 185 pinctrl-names = "aud_clk_mosi_off", 186 "aud_clk_mosi_on", 187 "aud_clk_miso_off", 188 "aud_clk_miso_on", 189 "aud_dat_miso_off", 190 "aud_dat_miso_on", 191 "aud_dat_mosi_off", 192 "aud_dat_mosi_on", 193 "aud_gpio_i2s0_off", 194 "aud_gpio_i2s0_on", 195 "aud_gpio_i2s1_off", 196 "aud_gpio_i2s1_on", 197 "aud_gpio_i2s2_off", 198 "aud_gpio_i2s2_on", 199 "aud_gpio_i2s3_off", 200 "aud_gpio_i2s3_on", 201 "aud_gpio_pcm_off", 202 "aud_gpio_pcm_on", 203 "aud_gpio_dmic_sec"; 204 pinctrl-0 = <&aud_clk_mosi_off>; 205 pinctrl-1 = <&aud_clk_mosi_on>; 206 pinctrl-2 = <&aud_clk_miso_off>; 207 pinctrl-3 = <&aud_clk_miso_on>; 208 pinctrl-4 = <&aud_dat_miso_off>; 209 pinctrl-5 = <&aud_dat_miso_on>; 210 pinctrl-6 = <&aud_dat_mosi_off>; 211 pinctrl-7 = <&aud_dat_mosi_on>; 212 pinctrl-8 = <&aud_gpio_i2s0_off>; 213 pinctrl-9 = <&aud_gpio_i2s0_on>; 214 pinctrl-10 = <&aud_gpio_i2s1_off>; 215 pinctrl-11 = <&aud_gpio_i2s1_on>; 216 pinctrl-12 = <&aud_gpio_i2s2_off>; 217 pinctrl-13 = <&aud_gpio_i2s2_on>; 218 pinctrl-14 = <&aud_gpio_i2s3_off>; 219 pinctrl-15 = <&aud_gpio_i2s3_on>; 220 pinctrl-16 = <&aud_gpio_pcm_off>; 221 pinctrl-17 = <&aud_gpio_pcm_on>; 222 pinctrl-18 = <&aud_gpio_dmic_sec>; 223 mediatek,adsp = <&adsp>; 224 mediatek,platform = <&afe>; 225 226 audio-routing = 227 "Headphone", "HPOL", 228 "Headphone", "HPOR", 229 "IN1P", "Headset Mic", 230 "Speakers", "Speaker", 231 "HDMI1", "TX"; 232 233 hs-playback-dai-link { 234 link-name = "I2S0"; 235 dai-format = "i2s"; 236 mediatek,clk-provider = "cpu"; 237 codec { 238 sound-dai = <&rt5682s 0>; 239 }; 240 }; 241 242 hs-capture-dai-link { 243 link-name = "I2S1"; 244 dai-format = "i2s"; 245 mediatek,clk-provider = "cpu"; 246 codec { 247 sound-dai = <&rt5682s 0>; 248 }; 249 }; 250 251 spk-share-dai-link { 252 link-name = "I2S2"; 253 mediatek,clk-provider = "cpu"; 254 }; 255 256 spk-hdmi-playback-dai-link { 257 link-name = "I2S3"; 258 dai-format = "i2s"; 259 mediatek,clk-provider = "cpu"; 260 /* RT1019P and IT6505 connected to the same I2S line */ 261 codec { 262 sound-dai = <&it6505dptx>, <&rt1019p>; 263 }; 264 }; 265 }; 266 267 rt1019p: speaker-codec { 268 compatible = "realtek,rt1019p"; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&rt1019p_pins_default>; 271 #sound-dai-cells = <0>; 272 sdb-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; 273 }; 274 275 usb_p1_vbus: regulator-usb-p1-vbus { 276 compatible = "regulator-fixed"; 277 gpio = <&pio 148 GPIO_ACTIVE_HIGH>; 278 regulator-name = "vbus1"; 279 regulator-min-microvolt = <5000000>; 280 regulator-max-microvolt = <5000000>; 281 enable-active-high; 282 vin-supply = <&pp5000_z2>; 283 }; 284 285 wifi_pwrseq: wifi-pwrseq { 286 compatible = "mmc-pwrseq-simple"; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&wifi_enable_pin>; 289 post-power-on-delay-ms = <50>; 290 reset-gpios = <&pio 54 GPIO_ACTIVE_LOW>; 291 }; 292 293 wifi_wakeup: wifi-wakeup { 294 compatible = "gpio-keys"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&wifi_wakeup_pin>; 297 298 wowlan-event { 299 label = "Wake on WiFi"; 300 gpios = <&pio 7 GPIO_ACTIVE_LOW>; 301 linux,code = <KEY_WAKEUP>; 302 wakeup-source; 303 }; 304 }; 305}; 306 307&adsp { 308 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 309 status = "okay"; 310}; 311 312&afe { 313 status = "okay"; 314}; 315 316&cci { 317 proc-supply = <&mt6366_vproc12_reg>; 318}; 319 320&cpu0 { 321 proc-supply = <&mt6366_vproc12_reg>; 322}; 323 324&cpu1 { 325 proc-supply = <&mt6366_vproc12_reg>; 326}; 327 328&cpu2 { 329 proc-supply = <&mt6366_vproc12_reg>; 330}; 331 332&cpu3 { 333 proc-supply = <&mt6366_vproc12_reg>; 334}; 335 336&cpu4 { 337 proc-supply = <&mt6366_vproc12_reg>; 338}; 339 340&cpu5 { 341 proc-supply = <&mt6366_vproc12_reg>; 342}; 343 344&cpu6 { 345 proc-supply = <&mt6366_vproc11_reg>; 346}; 347 348&cpu7 { 349 proc-supply = <&mt6366_vproc11_reg>; 350}; 351 352&dpi { 353 pinctrl-names = "default", "sleep"; 354 pinctrl-0 = <&dpi_pins_default>; 355 pinctrl-1 = <&dpi_pins_sleep>; 356 /* TODO Re-enable after DP to Type-C port muxing can be described */ 357 status = "disabled"; 358}; 359 360&dpi_out { 361 remote-endpoint = <&it6505_in>; 362}; 363 364&dsi0 { 365 status = "okay"; 366}; 367 368&gic { 369 mediatek,broken-save-restore-fw; 370}; 371 372&gpu { 373 mali-supply = <&mt6366_vgpu_reg>; 374 status = "okay"; 375}; 376 377&i2c0 { 378 pinctrl-names = "default"; 379 pinctrl-0 = <&i2c0_pins>; 380 status = "okay"; 381}; 382 383&i2c1 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&i2c1_pins>; 386 clock-frequency = <400000>; 387 i2c-scl-internal-delay-ns = <8000>; 388 status = "okay"; 389}; 390 391&i2c2 { 392 pinctrl-names = "default"; 393 /* 394 * Trackpad pin put here to work around second source components 395 * sharing the pinmux in steelix designs. 396 */ 397 pinctrl-0 = <&i2c2_pins>, <&trackpad_pin>; 398 clock-frequency = <400000>; 399 i2c-scl-internal-delay-ns = <10000>; 400 status = "okay"; 401 402 trackpad@15 { 403 compatible = "elan,ekth3000"; 404 reg = <0x15>; 405 interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; 406 vcc-supply = <&pp3300_s3>; 407 wakeup-source; 408 }; 409}; 410 411&i2c3 { 412 pinctrl-names = "default"; 413 pinctrl-0 = <&i2c3_pins>; 414 clock-frequency = <100000>; 415 status = "okay"; 416 417 it6505dptx: dp-bridge@5c { 418 compatible = "ite,it6505"; 419 reg = <0x5c>; 420 interrupts-extended = <&pio 8 IRQ_TYPE_LEVEL_LOW>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&it6505_pins>; 423 #sound-dai-cells = <0>; 424 ovdd-supply = <&mt6366_vsim2_reg>; 425 pwr18-supply = <&pp1800_dpbrdg_dx>; 426 reset-gpios = <&pio 177 GPIO_ACTIVE_HIGH>; 427 428 ports { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 432 port@0 { 433 reg = <0>; 434 435 it6505_in: endpoint { 436 link-frequencies = /bits/ 64 <150000000>; 437 remote-endpoint = <&dpi_out>; 438 }; 439 }; 440 441 port@1 { 442 reg = <1>; 443 }; 444 }; 445 }; 446}; 447 448&i2c5 { 449 pinctrl-names = "default"; 450 pinctrl-0 = <&i2c5_pins>; 451 status = "okay"; 452 453 rt5682s: codec@1a { 454 compatible = "realtek,rt5682s"; 455 reg = <0x1a>; 456 interrupts-extended = <&pio 17 IRQ_TYPE_EDGE_BOTH>; 457 #sound-dai-cells = <1>; 458 AVDD-supply = <&mt6366_vio18_reg>; 459 DBVDD-supply = <&mt6366_vio18_reg>; 460 LDO1-IN-supply = <&mt6366_vio18_reg>; 461 MICVDD-supply = <&pp3300_z2>; 462 realtek,jd-src = <1>; 463 }; 464}; 465 466&mfg0 { 467 domain-supply = <&mt6366_vsram_gpu_reg>; 468}; 469 470&mfg1 { 471 domain-supply = <&mt6366_vgpu_reg>; 472}; 473 474&mipi_tx0 { 475 status = "okay"; 476}; 477 478&mmc0 { 479 pinctrl-names = "default", "state_uhs"; 480 pinctrl-0 = <&mmc0_pins_default>; 481 pinctrl-1 = <&mmc0_pins_uhs>; 482 bus-width = <8>; 483 max-frequency = <200000000>; 484 non-removable; 485 cap-mmc-highspeed; 486 mmc-hs200-1_8v; 487 mmc-hs400-1_8v; 488 supports-cqe; 489 no-sd; 490 no-sdio; 491 cap-mmc-hw-reset; 492 hs400-ds-delay = <0x11814>; 493 mediatek,hs400-ds-dly3 = <0x14>; 494 vmmc-supply = <&mt6366_vemc_reg>; 495 vqmmc-supply = <&mt6366_vio18_reg>; 496 status = "okay"; 497}; 498 499&mmc1 { 500 pinctrl-names = "default", "state_uhs", "state_eint"; 501 pinctrl-0 = <&mmc1_pins_default>; 502 pinctrl-1 = <&mmc1_pins_uhs>; 503 pinctrl-2 = <&mmc1_pins_eint>; 504 /delete-property/ interrupts; 505 interrupt-names = "msdc", "sdio_wakeup"; 506 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 507 <&pio 87 IRQ_TYPE_LEVEL_LOW>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 bus-width = <4>; 511 max-frequency = <200000000>; 512 cap-sd-highspeed; 513 sd-uhs-sdr104; 514 sd-uhs-sdr50; 515 keep-power-in-suspend; 516 wakeup-source; 517 cap-sdio-irq; 518 no-mmc; 519 no-sd; 520 non-removable; 521 vmmc-supply = <&pp3300_s3>; 522 vqmmc-supply = <&mt6366_vio18_reg>; 523 mmc-pwrseq = <&wifi_pwrseq>; 524 status = "okay"; 525 526 bluetooth@2 { 527 compatible = "mediatek,mt7921s-bluetooth"; 528 reg = <2>; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&bt_pins_reset>; 531 reset-gpios = <&pio 155 GPIO_ACTIVE_LOW>; 532 }; 533}; 534 535&nor_flash { 536 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D7_D4>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&nor_pins_default>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "okay"; 542 543 flash@0 { 544 compatible = "jedec,spi-nor"; 545 reg = <0>; 546 spi-max-frequency = <39000000>; 547 }; 548}; 549 550&pio { 551 /* 185 lines */ 552 gpio-line-names = "TP", 553 "TP", 554 "TP", 555 "I2S0_HP_DI", 556 "I2S3_DP_SPKR_DO", 557 "SAR_INT_ODL", 558 "BT_WAKE_AP_ODL", 559 "WIFI_INT_ODL", 560 "DPBRDG_INT_ODL", 561 "EDPBRDG_INT_ODL", 562 "EC_AP_HPD_OD", 563 "TCHPAD_INT_ODL", 564 "TCHSCR_INT_1V8_ODL", 565 "EC_AP_INT_ODL", 566 "EC_IN_RW_ODL", 567 "GSC_AP_INT_ODL", 568 /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ 569 "AP_FLASH_WP_L", 570 "HP_INT_ODL", 571 "PEN_EJECT_OD", 572 "WCAM_PWDN_L", 573 "WCAM_RST_L", 574 "UCAM_SEN_EN", 575 "UCAM_RST_L", 576 "LTE_RESET_L", 577 "LTE_SAR_DETECT_L", 578 "I2S2_DP_SPK_MCK", 579 "I2S2_DP_SPKR_BCK", 580 "I2S2_DP_SPKR_LRCK", 581 "I2S2_DP_SPKR_DI (TP)", 582 "EN_PP1000_EDPBRDG", 583 "EN_PP1800_EDPBRDG", 584 "EN_PP3300_EDPBRDG", 585 "UART_GSC_TX_AP_RX", 586 "UART_AP_TX_GSC_RX", 587 "UART_DBGCON_TX_ADSP_RX", 588 "UART_ADSP_TX_DBGCON_RX", 589 "EN_PP1000_DPBRDG", 590 "TCHSCR_REPORT_DISABLE", 591 "EN_PP3300_DPBRDG", 592 "EN_PP1800_DPBRDG", 593 "SPI_AP_CLK_EC", 594 "SPI_AP_CS_EC_L", 595 "SPI_AP_DO_EC_DI", 596 "SPI_AP_DI_EC_DO", 597 "SPI_AP_CLK_GSC", 598 "SPI_AP_CS_GSC_L", 599 "SPI_AP_DO_GSC_DI", 600 "SPI_AP_DI_GSC_DO", 601 "UART_DBGCON_TX_SCP_RX", 602 "UART_SCP_TX_DBGCON_RX", 603 "EN_PP1200_CAM_X", 604 "EN_PP2800A_VCM_X", 605 "EN_PP2800A_UCAM_X", 606 "EN_PP2800A_WCAM_X", 607 "WLAN_MODULE_RST_L", 608 "EN_PP1200_UCAM_X", 609 "I2S1_HP_DO", 610 "I2S1_HP_BCK", 611 "I2S1_HP_LRCK", 612 "I2S1_HP_MCK", 613 "TCHSCR_RST_1V8_L", 614 "SPI_AP_CLK_ROM", 615 "SPI_AP_CS_ROM_L", 616 "SPI_AP_DO_ROM_DI", 617 "SPI_AP_DI_ROM_DO", 618 "NC", 619 "NC", 620 "EMMC_STRB", 621 "EMMC_CLK", 622 "EMMC_CMD", 623 "EMMC_RST_L", 624 "EMMC_DATA0", 625 "EMMC_DATA1", 626 "EMMC_DATA2", 627 "EMMC_DATA3", 628 "EMMC_DATA4", 629 "EMMC_DATA5", 630 "EMMC_DATA6", 631 "EMMC_DATA7", 632 "AP_KPCOL0", 633 "NC", 634 "NC", 635 "NC", 636 "TP", 637 "SDIO_CLK", 638 "SDIO_CMD", 639 "SDIO_DATA0", 640 "SDIO_DATA1", 641 "SDIO_DATA2", 642 "SDIO_DATA3", 643 "NC", 644 "NC", 645 "NC", 646 "NC", 647 "NC", 648 "NC", 649 "EDPBRDG_PWREN", 650 "BL_PWM_1V8", 651 "EDPBRDG_RST_L", 652 "MIPI_DPI_CLK", 653 "MIPI_DPI_VSYNC", 654 "MIPI_DPI_HSYNC", 655 "MIPI_DPI_DE", 656 "MIPI_DPI_D0", 657 "MIPI_DPI_D1", 658 "MIPI_DPI_D2", 659 "MIPI_DPI_D3", 660 "MIPI_DPI_D4", 661 "MIPI_DPI_D5", 662 "MIPI_DPI_D6", 663 "MIPI_DPI_DA7", 664 "MIPI_DPI_D8", 665 "MIPI_DPI_D9", 666 "MIPI_DPI_D10", 667 "MIPI_DPI_D11", 668 "PCM_BT_CLK", 669 "PCM_BT_SYNC", 670 "PCM_BT_DI", 671 "PCM_BT_DO", 672 "JTAG_TMS_TP", 673 "JTAG_TCK_TP", 674 "JTAG_TDI_TP", 675 "JTAG_TDO_TP", 676 "JTAG_TRSTN_TP", 677 "CLK_24M_WCAM", 678 "CLK_24M_UCAM", 679 "UCAM_DET_ODL", 680 "AP_I2C_EDPBRDG_SCL_1V8", 681 "AP_I2C_EDPBRDG_SDA_1V8", 682 "AP_I2C_TCHSCR_SCL_1V8", 683 "AP_I2C_TCHSCR_SDA_1V8", 684 "AP_I2C_TCHPAD_SCL_1V8", 685 "AP_I2C_TCHPAD_SDA_1V8", 686 "AP_I2C_DPBRDG_SCL_1V8", 687 "AP_I2C_DPBRDG_SDA_1V8", 688 "AP_I2C_WLAN_SCL_1V8", 689 "AP_I2C_WLAN_SDA_1V8", 690 "AP_I2C_AUD_SCL_1V8", 691 "AP_I2C_AUD_SDA_1V8", 692 "AP_I2C_TPM_SCL_1V8", 693 "AP_I2C_UCAM_SDA_1V8", 694 "AP_I2C_UCAM_SCL_1V8", 695 "AP_I2C_UCAM_SDA_1V8", 696 "AP_I2C_WCAM_SCL_1V8", 697 "AP_I2C_WCAM_SDA_1V8", 698 "SCP_I2C_SENSOR_SCL_1V8", 699 "SCP_I2C_SENSOR_SDA_1V8", 700 "AP_EC_WARM_RST_REQ", 701 "AP_XHCI_INIT_DONE", 702 "USB3_HUB_RST_L", 703 "EN_SPKR", 704 "BEEP_ON", 705 "AP_EDP_BKLTEN", 706 "EN_PP3300_DISP_X", 707 "EN_PP3300_SDBRDG_X", 708 "BT_KILL_1V8_L", 709 "WIFI_KILL_1V8_L", 710 "PWRAP_SPI0_CSN", 711 "PWRAP_SPI0_CK", 712 "PWRAP_SPI0_MO", 713 "PWRAP_SPI0_MI", 714 "SRCLKENA0", 715 "SRCLKENA1", 716 "SCP_VREQ_VAO", 717 "AP_RTC_CLK32K", 718 "AP_PMIC_WDTRST_L", 719 "AUD_CLK_MOSI", 720 "AUD_SYNC_MOSI", 721 "AUD_DAT_MOSI0", 722 "AUD_DAT_MOSI1", 723 "AUD_CLK_MISO", 724 "AUD_SYNC_MISO", 725 "AUD_DAT_MISO0", 726 "AUD_DAT_MISO1", 727 "NC", 728 "NC", 729 "DPBRDG_PWREN", 730 "DPBRDG_RST_L", 731 "LTE_W_DISABLE_L", 732 "LTE_SAR_DETECT_L", 733 "EN_PP3300_LTE_X", 734 "LTE_PWR_OFF_L", 735 "LTE_RESET_L", 736 "TP", 737 "TP"; 738 739 aud_clk_mosi_off: aud-clk-mosi-off-pins { 740 pins-clk-sync { 741 pinmux = <PINMUX_GPIO166__FUNC_GPIO166>, 742 <PINMUX_GPIO167__FUNC_GPIO167>; 743 input-enable; 744 bias-pull-down; 745 }; 746 }; 747 748 aud_clk_mosi_on: aud-clk-mosi-on-pins { 749 pins-clk-sync { 750 pinmux = <PINMUX_GPIO166__FUNC_AUD_CLK_MOSI>, 751 <PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI>; 752 }; 753 }; 754 755 aud_clk_miso_off: aud-clk-miso-off-pins { 756 pins-clk-sync { 757 pinmux = <PINMUX_GPIO170__FUNC_GPIO170>, 758 <PINMUX_GPIO171__FUNC_GPIO171>; 759 input-enable; 760 bias-pull-down; 761 }; 762 }; 763 764 aud_clk_miso_on: aud-clk-miso-on-pins { 765 pins-clk-sync { 766 pinmux = <PINMUX_GPIO170__FUNC_AUD_CLK_MISO>, 767 <PINMUX_GPIO171__FUNC_AUD_SYNC_MISO>; 768 }; 769 }; 770 771 aud_dat_mosi_off: aud-dat-mosi-off-pins { 772 pins-dat { 773 pinmux = <PINMUX_GPIO168__FUNC_GPIO168>, 774 <PINMUX_GPIO169__FUNC_GPIO169>; 775 input-enable; 776 bias-pull-down; 777 }; 778 }; 779 780 aud_dat_mosi_on: aud-dat-mosi-on-pins { 781 pins-dat { 782 pinmux = <PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0>, 783 <PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1>; 784 }; 785 }; 786 787 aud_dat_miso_off: aud-dat-miso-off-pins { 788 pins-dat { 789 pinmux = <PINMUX_GPIO172__FUNC_GPIO172>, 790 <PINMUX_GPIO173__FUNC_GPIO173>; 791 input-enable; 792 bias-pull-down; 793 }; 794 }; 795 796 aud_dat_miso_on: aud-dat-miso-on-pins { 797 pins-dat { 798 pinmux = <PINMUX_GPIO172__FUNC_AUD_DAT_MISO0>, 799 <PINMUX_GPIO173__FUNC_AUD_DAT_MISO1>; 800 input-schmitt-enable; 801 bias-disable; 802 }; 803 }; 804 805 aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins { 806 pins-sdata { 807 pinmux = <PINMUX_GPIO3__FUNC_GPIO3>; 808 }; 809 }; 810 811 aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins { 812 pins-sdata { 813 pinmux = <PINMUX_GPIO3__FUNC_I2S0_DI>; 814 }; 815 }; 816 817 aud_gpio_i2s1_off: aud-gpio-i2s-off-pins { 818 pins-clk-sdata { 819 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>, 820 <PINMUX_GPIO57__FUNC_GPIO57>, 821 <PINMUX_GPIO58__FUNC_GPIO58>, 822 <PINMUX_GPIO59__FUNC_GPIO59>; 823 output-low; 824 }; 825 }; 826 827 aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins { 828 pins-clk-sdata { 829 pinmux = <PINMUX_GPIO56__FUNC_I2S1_DO>, 830 <PINMUX_GPIO57__FUNC_I2S1_BCK>, 831 <PINMUX_GPIO58__FUNC_I2S1_LRCK>, 832 <PINMUX_GPIO59__FUNC_I2S1_MCK>; 833 }; 834 }; 835 836 aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins { 837 pins-cmd-dat { 838 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>, 839 <PINMUX_GPIO27__FUNC_GPIO27>; 840 output-low; 841 }; 842 }; 843 844 aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins { 845 pins-clk { 846 pinmux = <PINMUX_GPIO26__FUNC_I2S2_BCK>, 847 <PINMUX_GPIO27__FUNC_I2S2_LRCK>; 848 drive-strength = <4>; 849 }; 850 }; 851 852 aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins { 853 pins-sdata { 854 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; 855 output-low; 856 }; 857 }; 858 859 aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins { 860 pins-sdata { 861 pinmux = <PINMUX_GPIO4__FUNC_I2S3_DO>; 862 drive-strength = <4>; 863 }; 864 }; 865 866 aud_gpio_pcm_off: aud-gpio-pcm-off-pins { 867 pins-clk-sdata { 868 pinmux = <PINMUX_GPIO115__FUNC_GPIO115>, 869 <PINMUX_GPIO116__FUNC_GPIO116>, 870 <PINMUX_GPIO117__FUNC_GPIO117>, 871 <PINMUX_GPIO118__FUNC_GPIO118>; 872 output-low; 873 }; 874 }; 875 876 aud_gpio_pcm_on: aud-gpio-pcm-on-pins { 877 pins-clk-sdata { 878 pinmux = <PINMUX_GPIO115__FUNC_PCM_CLK>, 879 <PINMUX_GPIO116__FUNC_PCM_SYNC>, 880 <PINMUX_GPIO117__FUNC_PCM_DI>, 881 <PINMUX_GPIO118__FUNC_PCM_DO>; 882 }; 883 }; 884 885 aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins { 886 pins { 887 pinmux = <PINMUX_GPIO23__FUNC_GPIO23>; 888 output-low; 889 }; 890 }; 891 892 bt_pins_reset: bt-reset-pins { 893 pins-bt-reset { 894 pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; 895 output-high; 896 }; 897 }; 898 899 dpi_pins_sleep: dpi-sleep-pins { 900 pins-cmd-dat { 901 pinmux = <PINMUX_GPIO103__FUNC_GPIO103>, 902 <PINMUX_GPIO104__FUNC_GPIO104>, 903 <PINMUX_GPIO105__FUNC_GPIO105>, 904 <PINMUX_GPIO106__FUNC_GPIO106>, 905 <PINMUX_GPIO107__FUNC_GPIO107>, 906 <PINMUX_GPIO108__FUNC_GPIO108>, 907 <PINMUX_GPIO109__FUNC_GPIO109>, 908 <PINMUX_GPIO110__FUNC_GPIO110>, 909 <PINMUX_GPIO111__FUNC_GPIO111>, 910 <PINMUX_GPIO112__FUNC_GPIO112>, 911 <PINMUX_GPIO113__FUNC_GPIO113>, 912 <PINMUX_GPIO114__FUNC_GPIO114>, 913 <PINMUX_GPIO101__FUNC_GPIO101>, 914 <PINMUX_GPIO100__FUNC_GPIO100>, 915 <PINMUX_GPIO102__FUNC_GPIO102>, 916 <PINMUX_GPIO99__FUNC_GPIO99>; 917 drive-strength = <10>; 918 output-low; 919 }; 920 }; 921 922 dpi_pins_default: dpi-default-pins { 923 pins-cmd-dat { 924 pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>, 925 <PINMUX_GPIO104__FUNC_DPI_DATA1>, 926 <PINMUX_GPIO105__FUNC_DPI_DATA2>, 927 <PINMUX_GPIO106__FUNC_DPI_DATA3>, 928 <PINMUX_GPIO107__FUNC_DPI_DATA4>, 929 <PINMUX_GPIO108__FUNC_DPI_DATA5>, 930 <PINMUX_GPIO109__FUNC_DPI_DATA6>, 931 <PINMUX_GPIO110__FUNC_DPI_DATA7>, 932 <PINMUX_GPIO111__FUNC_DPI_DATA8>, 933 <PINMUX_GPIO112__FUNC_DPI_DATA9>, 934 <PINMUX_GPIO113__FUNC_DPI_DATA10>, 935 <PINMUX_GPIO114__FUNC_DPI_DATA11>, 936 <PINMUX_GPIO101__FUNC_DPI_HSYNC>, 937 <PINMUX_GPIO100__FUNC_DPI_VSYNC>, 938 <PINMUX_GPIO102__FUNC_DPI_DE>, 939 <PINMUX_GPIO99__FUNC_DPI_PCLK>; 940 drive-strength = <10>; 941 }; 942 }; 943 944 ec_ap_int: cros-ec-int-pins { 945 pins-ec-ap-int-odl { 946 pinmux = <PINMUX_GPIO13__FUNC_GPIO13>; 947 input-enable; 948 }; 949 }; 950 951 edp_panel_fixed_pins: edp-panel-fixed-pins { 952 pins-vreg-en { 953 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 954 output-high; 955 }; 956 }; 957 958 en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins { 959 pins-vreg-en { 960 pinmux = <PINMUX_GPIO39__FUNC_GPIO39>; 961 output-low; 962 }; 963 }; 964 965 gsc_int: gsc-int-pins { 966 pins-gsc-ap-int-odl { 967 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 968 input-enable; 969 }; 970 }; 971 972 i2c0_pins: i2c0-pins { 973 pins-bus { 974 pinmux = <PINMUX_GPIO128__FUNC_SDA0>, 975 <PINMUX_GPIO127__FUNC_SCL0>; 976 bias-disable; 977 drive-strength = <4>; 978 input-enable; 979 }; 980 }; 981 982 i2c1_pins: i2c1-pins { 983 pins-bus { 984 pinmux = <PINMUX_GPIO130__FUNC_SDA1>, 985 <PINMUX_GPIO129__FUNC_SCL1>; 986 bias-disable; 987 drive-strength = <4>; 988 input-enable; 989 }; 990 }; 991 992 i2c2_pins: i2c2-pins { 993 pins-bus { 994 pinmux = <PINMUX_GPIO132__FUNC_SDA2>, 995 <PINMUX_GPIO131__FUNC_SCL2>; 996 bias-disable; 997 drive-strength = <4>; 998 input-enable; 999 }; 1000 }; 1001 1002 i2c3_pins: i2c3-pins { 1003 pins-bus { 1004 pinmux = <PINMUX_GPIO134__FUNC_SDA3>, 1005 <PINMUX_GPIO133__FUNC_SCL3>; 1006 bias-disable; 1007 drive-strength = <4>; 1008 input-enable; 1009 }; 1010 }; 1011 1012 i2c5_pins: i2c5-pins { 1013 pins-bus { 1014 pinmux = <PINMUX_GPIO138__FUNC_SDA5>, 1015 <PINMUX_GPIO137__FUNC_SCL5>; 1016 bias-disable; 1017 drive-strength = <4>; 1018 input-enable; 1019 }; 1020 }; 1021 1022 it6505_pins: it6505-pins { 1023 pins-hpd { 1024 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>; 1025 input-enable; 1026 bias-pull-up; 1027 }; 1028 1029 pins-int { 1030 pinmux = <PINMUX_GPIO8__FUNC_GPIO8>; 1031 input-enable; 1032 bias-pull-up; 1033 }; 1034 1035 pins-reset { 1036 pinmux = <PINMUX_GPIO177__FUNC_GPIO177>; 1037 output-low; 1038 bias-pull-up; 1039 }; 1040 }; 1041 1042 mmc0_pins_default: mmc0-default-pins { 1043 pins-clk { 1044 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1045 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1046 }; 1047 1048 pins-cmd-dat { 1049 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1050 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1051 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1052 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1053 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1054 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1055 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1056 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1057 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1058 input-enable; 1059 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1060 }; 1061 1062 pins-rst { 1063 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1064 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1065 }; 1066 }; 1067 1068 mmc0_pins_uhs: mmc0-uhs-pins { 1069 pins-clk { 1070 pinmux = <PINMUX_GPIO68__FUNC_MSDC0_CLK>; 1071 drive-strength = <6>; 1072 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1073 }; 1074 1075 pins-cmd-dat { 1076 pinmux = <PINMUX_GPIO71__FUNC_MSDC0_DAT0>, 1077 <PINMUX_GPIO72__FUNC_MSDC0_DAT1>, 1078 <PINMUX_GPIO73__FUNC_MSDC0_DAT2>, 1079 <PINMUX_GPIO74__FUNC_MSDC0_DAT3>, 1080 <PINMUX_GPIO75__FUNC_MSDC0_DAT4>, 1081 <PINMUX_GPIO76__FUNC_MSDC0_DAT5>, 1082 <PINMUX_GPIO77__FUNC_MSDC0_DAT6>, 1083 <PINMUX_GPIO78__FUNC_MSDC0_DAT7>, 1084 <PINMUX_GPIO69__FUNC_MSDC0_CMD>; 1085 input-enable; 1086 drive-strength = <6>; 1087 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1088 }; 1089 1090 pins-ds { 1091 pinmux = <PINMUX_GPIO67__FUNC_MSDC0_DSL>; 1092 drive-strength = <6>; 1093 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1094 }; 1095 1096 pins-rst { 1097 pinmux = <PINMUX_GPIO70__FUNC_MSDC0_RSTB>; 1098 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1099 }; 1100 }; 1101 1102 mmc1_pins_default: mmc1-default-pins { 1103 pins-clk { 1104 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1105 drive-strength = <6>; 1106 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1107 }; 1108 1109 pins-cmd-dat { 1110 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1111 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1112 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1113 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1114 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1115 input-enable; 1116 drive-strength = <6>; 1117 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1118 }; 1119 }; 1120 1121 mmc1_pins_uhs: mmc1-uhs-pins { 1122 pins-clk { 1123 pinmux = <PINMUX_GPIO84__FUNC_MSDC1_CLK>; 1124 drive-strength = <6>; 1125 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1126 }; 1127 1128 pins-cmd-dat { 1129 pinmux = <PINMUX_GPIO86__FUNC_MSDC1_DAT0>, 1130 <PINMUX_GPIO87__FUNC_MSDC1_DAT1>, 1131 <PINMUX_GPIO88__FUNC_MSDC1_DAT2>, 1132 <PINMUX_GPIO89__FUNC_MSDC1_DAT3>, 1133 <PINMUX_GPIO85__FUNC_MSDC1_CMD>; 1134 input-enable; 1135 drive-strength = <8>; 1136 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1137 }; 1138 }; 1139 1140 mmc1_pins_eint: mmc1-eint-pins { 1141 pins-dat1 { 1142 pinmux = <PINMUX_GPIO87__FUNC_GPIO87>; 1143 input-enable; 1144 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1145 }; 1146 }; 1147 1148 nor_pins_default: nor-default-pins { 1149 pins-clk-dat { 1150 pinmux = <PINMUX_GPIO63__FUNC_SPINOR_IO0>, 1151 <PINMUX_GPIO61__FUNC_SPINOR_CK>, 1152 <PINMUX_GPIO64__FUNC_SPINOR_IO1>; 1153 drive-strength = <6>; 1154 bias-pull-down; 1155 }; 1156 1157 pins-cs-dat { 1158 pinmux = <PINMUX_GPIO62__FUNC_SPINOR_CS>, 1159 <PINMUX_GPIO65__FUNC_SPINOR_IO2>, 1160 <PINMUX_GPIO66__FUNC_SPINOR_IO3>; 1161 drive-strength = <6>; 1162 bias-pull-up; 1163 }; 1164 }; 1165 1166 pen_eject: pen-eject-pins { 1167 pins { 1168 pinmux = <PINMUX_GPIO18__FUNC_GPIO18>; 1169 input-enable; 1170 /* External pull-up. */ 1171 bias-disable; 1172 }; 1173 }; 1174 1175 pwm0_pin: disp-pwm-pins { 1176 pins { 1177 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM>; 1178 output-high; 1179 }; 1180 }; 1181 1182 rt1019p_pins_default: rt1019p-default-pins { 1183 pins-sdb { 1184 pinmux = <PINMUX_GPIO150__FUNC_GPIO150>; 1185 output-low; 1186 }; 1187 }; 1188 1189 scp_pins: scp-default-pins { 1190 pins-scp-uart { 1191 pinmux = <PINMUX_GPIO48__FUNC_TP_URXD2_AO>, 1192 <PINMUX_GPIO49__FUNC_TP_UTXD2_AO>; 1193 }; 1194 }; 1195 1196 spi1_pins: spi1-pins { 1197 pins-bus { 1198 pinmux = <PINMUX_GPIO40__FUNC_SPI1_CLK_A>, 1199 <PINMUX_GPIO41__FUNC_SPI1_CSB_A>, 1200 <PINMUX_GPIO42__FUNC_SPI1_MO_A>, 1201 <PINMUX_GPIO43__FUNC_SPI1_MI_A>; 1202 bias-disable; 1203 input-enable; 1204 }; 1205 }; 1206 1207 spi2_pins: spi2-pins { 1208 pins-bus { 1209 pinmux = <PINMUX_GPIO44__FUNC_SPI2_CLK_A>, 1210 <PINMUX_GPIO45__FUNC_GPIO45>, 1211 <PINMUX_GPIO46__FUNC_SPI2_MO_A>, 1212 <PINMUX_GPIO47__FUNC_SPI2_MI_A>; 1213 bias-disable; 1214 input-enable; 1215 }; 1216 }; 1217 1218 spmi_pins: spmi-pins { 1219 pins-bus { 1220 pinmux = <PINMUX_GPIO183__FUNC_SPMI_SCL>, 1221 <PINMUX_GPIO184__FUNC_SPMI_SDA>; 1222 }; 1223 }; 1224 1225 touchscreen_pins: touchscreen-pins { 1226 pins-irq { 1227 pinmux = <PINMUX_GPIO12__FUNC_GPIO12>; 1228 input-enable; 1229 bias-pull-up; 1230 }; 1231 1232 pins-reset { 1233 pinmux = <PINMUX_GPIO60__FUNC_GPIO60>; 1234 output-high; 1235 }; 1236 1237 pins-report-sw { 1238 pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; 1239 output-low; 1240 }; 1241 }; 1242 1243 trackpad_pin: trackpad-default-pins { 1244 pins-int-n { 1245 pinmux = <PINMUX_GPIO11__FUNC_GPIO11>; 1246 input-enable; 1247 bias-disable; /* pulled externally */ 1248 }; 1249 }; 1250 1251 wifi_enable_pin: wifi-enable-pins { 1252 pins-wifi-enable { 1253 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; 1254 }; 1255 }; 1256 1257 wifi_wakeup_pin: wifi-wakeup-pins { 1258 pins-wifi-wakeup { 1259 pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; 1260 input-enable; 1261 }; 1262 }; 1263}; 1264 1265&pwm0 { 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&pwm0_pin>; 1268 status = "okay"; 1269}; 1270 1271&pwrap { 1272 pmic { 1273 compatible = "mediatek,mt6366", "mediatek,mt6358"; 1274 interrupt-controller; 1275 interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>; 1276 #interrupt-cells = <2>; 1277 1278 mt6366codec: codec { 1279 compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound"; 1280 Avdd-supply = <&mt6366_vaud28_reg>; 1281 mediatek,dmic-mode = <1>; /* one-wire */ 1282 }; 1283 1284 mt6366_regulators: regulators { 1285 compatible = "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; 1286 vsys-ldo1-supply = <&pp4200_z2>; 1287 vsys-ldo2-supply = <&pp4200_z2>; 1288 vsys-ldo3-supply = <&pp4200_z2>; 1289 vsys-vcore-supply = <&pp4200_z2>; 1290 vsys-vdram1-supply = <&pp4200_z2>; 1291 vsys-vgpu-supply = <&pp4200_z2>; 1292 vsys-vmodem-supply = <&pp4200_z2>; 1293 vsys-vpa-supply = <&pp4200_z2>; 1294 vsys-vproc11-supply = <&pp4200_z2>; 1295 vsys-vproc12-supply = <&pp4200_z2>; 1296 vsys-vs1-supply = <&pp4200_z2>; 1297 vsys-vs2-supply = <&pp4200_z2>; 1298 vs1-ldo1-supply = <&mt6366_vs1_reg>; 1299 vs2-ldo1-supply = <&mt6366_vdram1_reg>; 1300 vs2-ldo2-supply = <&mt6366_vs2_reg>; 1301 vs2-ldo3-supply = <&mt6366_vs2_reg>; 1302 1303 vcore { 1304 regulator-name = "pp0750_dvdd_core"; 1305 regulator-min-microvolt = <550000>; 1306 regulator-max-microvolt = <800000>; 1307 regulator-ramp-delay = <6250>; 1308 regulator-enable-ramp-delay = <200>; 1309 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1310 MT6397_BUCK_MODE_FORCE_PWM>; 1311 regulator-always-on; 1312 }; 1313 1314 mt6366_vdram1_reg: vdram1 { 1315 regulator-name = "pp1125_emi_vdd2"; 1316 regulator-min-microvolt = <1125000>; 1317 regulator-max-microvolt = <1125000>; 1318 regulator-ramp-delay = <12500>; 1319 regulator-enable-ramp-delay = <0>; 1320 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1321 MT6397_BUCK_MODE_FORCE_PWM>; 1322 regulator-always-on; 1323 }; 1324 1325 mt6366_vgpu_reg: vgpu { 1326 /* 1327 * Called "ppvar_dvdd_gpu" in the schematic. 1328 * Called "ppvar_dvdd_vgpu" here to match 1329 * regulator coupling requirements. 1330 */ 1331 regulator-name = "ppvar_dvdd_vgpu"; 1332 regulator-min-microvolt = <500000>; 1333 regulator-max-microvolt = <950000>; 1334 regulator-ramp-delay = <6250>; 1335 regulator-enable-ramp-delay = <200>; 1336 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1337 MT6397_BUCK_MODE_FORCE_PWM>; 1338 regulator-coupled-with = <&mt6366_vsram_gpu_reg>; 1339 regulator-coupled-max-spread = <10000>; 1340 }; 1341 1342 mt6366_vproc11_reg: vproc11 { 1343 regulator-name = "ppvar_dvdd_proc_bc_mt6366"; 1344 regulator-min-microvolt = <600000>; 1345 regulator-max-microvolt = <1200000>; 1346 regulator-ramp-delay = <6250>; 1347 regulator-enable-ramp-delay = <200>; 1348 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1349 MT6397_BUCK_MODE_FORCE_PWM>; 1350 regulator-always-on; 1351 }; 1352 1353 mt6366_vproc12_reg: vproc12 { 1354 regulator-name = "ppvar_dvdd_proc_lc"; 1355 regulator-min-microvolt = <600000>; 1356 regulator-max-microvolt = <1200000>; 1357 regulator-ramp-delay = <6250>; 1358 regulator-enable-ramp-delay = <200>; 1359 regulator-allowed-modes = <MT6397_BUCK_MODE_AUTO 1360 MT6397_BUCK_MODE_FORCE_PWM>; 1361 regulator-always-on; 1362 }; 1363 1364 mt6366_vs1_reg: vs1 { 1365 regulator-name = "pp2000_vs1"; 1366 regulator-min-microvolt = <2000000>; 1367 regulator-max-microvolt = <2000000>; 1368 regulator-ramp-delay = <12500>; 1369 regulator-enable-ramp-delay = <0>; 1370 regulator-always-on; 1371 }; 1372 1373 mt6366_vs2_reg: vs2 { 1374 regulator-name = "pp1350_vs2"; 1375 regulator-min-microvolt = <1350000>; 1376 regulator-max-microvolt = <1350000>; 1377 regulator-ramp-delay = <12500>; 1378 regulator-enable-ramp-delay = <0>; 1379 regulator-always-on; 1380 }; 1381 1382 va12 { 1383 regulator-name = "pp1200_va12"; 1384 regulator-min-microvolt = <1200000>; 1385 regulator-max-microvolt = <1200000>; 1386 regulator-enable-ramp-delay = <270>; 1387 regulator-always-on; 1388 }; 1389 1390 mt6366_vaud28_reg: vaud28 { 1391 regulator-name = "pp2800_vaud28"; 1392 regulator-min-microvolt = <2800000>; 1393 regulator-max-microvolt = <2800000>; 1394 regulator-enable-ramp-delay = <270>; 1395 }; 1396 1397 mt6366_vaux18_reg: vaux18 { 1398 regulator-name = "pp1840_vaux18"; 1399 regulator-min-microvolt = <1800000>; 1400 regulator-max-microvolt = <1840000>; 1401 regulator-enable-ramp-delay = <270>; 1402 }; 1403 1404 mt6366_vbif28_reg: vbif28 { 1405 regulator-name = "pp2800_vbif28"; 1406 regulator-min-microvolt = <2800000>; 1407 regulator-max-microvolt = <2800000>; 1408 regulator-enable-ramp-delay = <270>; 1409 }; 1410 1411 mt6366_vcn18_reg: vcn18 { 1412 regulator-name = "pp1800_vcn18_x"; 1413 regulator-min-microvolt = <1800000>; 1414 regulator-max-microvolt = <1800000>; 1415 regulator-enable-ramp-delay = <270>; 1416 }; 1417 1418 mt6366_vcn28_reg: vcn28 { 1419 regulator-name = "pp2800_vcn28_x"; 1420 regulator-min-microvolt = <2800000>; 1421 regulator-max-microvolt = <2800000>; 1422 regulator-enable-ramp-delay = <270>; 1423 }; 1424 1425 mt6366_vefuse_reg: vefuse { 1426 regulator-name = "pp1800_vefuse"; 1427 regulator-min-microvolt = <1800000>; 1428 regulator-max-microvolt = <1800000>; 1429 regulator-enable-ramp-delay = <270>; 1430 }; 1431 1432 mt6366_vfe28_reg: vfe28 { 1433 regulator-name = "pp2800_vfe28_x"; 1434 regulator-min-microvolt = <2800000>; 1435 regulator-max-microvolt = <2800000>; 1436 regulator-enable-ramp-delay = <270>; 1437 }; 1438 1439 mt6366_vemc_reg: vemc { 1440 regulator-name = "pp3000_vemc"; 1441 regulator-min-microvolt = <3000000>; 1442 regulator-max-microvolt = <3000000>; 1443 regulator-enable-ramp-delay = <60>; 1444 }; 1445 1446 mt6366_vibr_reg: vibr { 1447 regulator-name = "pp2800_vibr_x"; 1448 regulator-min-microvolt = <2800000>; 1449 regulator-max-microvolt = <2800000>; 1450 regulator-enable-ramp-delay = <60>; 1451 }; 1452 1453 mt6366_vio18_reg: vio18 { 1454 regulator-name = "pp1800_vio18_s3"; 1455 regulator-min-microvolt = <1800000>; 1456 regulator-max-microvolt = <1800000>; 1457 regulator-enable-ramp-delay = <2700>; 1458 regulator-always-on; 1459 }; 1460 1461 mt6366_vio28_reg: vio28 { 1462 regulator-name = "pp2800_vio28_x"; 1463 regulator-min-microvolt = <2800000>; 1464 regulator-max-microvolt = <2800000>; 1465 regulator-enable-ramp-delay = <270>; 1466 }; 1467 1468 mt6366_vm18_reg: vm18 { 1469 regulator-name = "pp1800_emi_vdd1"; 1470 regulator-min-microvolt = <1800000>; 1471 regulator-max-microvolt = <1840000>; 1472 regulator-enable-ramp-delay = <325>; 1473 regulator-always-on; 1474 }; 1475 1476 mt6366_vmc_reg: vmc { 1477 regulator-name = "pp3000_vmc"; 1478 regulator-min-microvolt = <3000000>; 1479 regulator-max-microvolt = <3000000>; 1480 regulator-enable-ramp-delay = <60>; 1481 }; 1482 1483 mt6366_vmddr_reg: vmddr { 1484 regulator-name = "pm0750_emi_vmddr"; 1485 regulator-min-microvolt = <700000>; 1486 regulator-max-microvolt = <750000>; 1487 regulator-enable-ramp-delay = <325>; 1488 regulator-always-on; 1489 }; 1490 1491 mt6366_vmch_reg: vmch { 1492 regulator-name = "pp3000_vmch"; 1493 regulator-min-microvolt = <3000000>; 1494 regulator-max-microvolt = <3000000>; 1495 regulator-enable-ramp-delay = <60>; 1496 }; 1497 1498 mt6366_vcn33_reg: vcn33 { 1499 regulator-name = "pp3300_vcn33_x"; 1500 regulator-min-microvolt = <3300000>; 1501 regulator-max-microvolt = <3300000>; 1502 regulator-enable-ramp-delay = <270>; 1503 }; 1504 1505 vdram2 { 1506 regulator-name = "pp0600_emi_vddq"; 1507 regulator-min-microvolt = <600000>; 1508 regulator-max-microvolt = <600000>; 1509 regulator-enable-ramp-delay = <3300>; 1510 regulator-always-on; 1511 }; 1512 1513 mt6366_vrf12_reg: vrf12 { 1514 regulator-name = "pp1200_vrf12_x"; 1515 regulator-min-microvolt = <1200000>; 1516 regulator-max-microvolt = <1200000>; 1517 regulator-enable-ramp-delay = <120>; 1518 }; 1519 1520 mt6366_vrf18_reg: vrf18 { 1521 regulator-name = "pp1800_vrf18_x"; 1522 regulator-min-microvolt = <1800000>; 1523 regulator-max-microvolt = <1800000>; 1524 regulator-enable-ramp-delay = <120>; 1525 }; 1526 1527 vsim1 { 1528 regulator-name = "pp1860_vsim1_x"; 1529 regulator-min-microvolt = <1800000>; 1530 regulator-max-microvolt = <1860000>; 1531 regulator-enable-ramp-delay = <540>; 1532 }; 1533 1534 mt6366_vsim2_reg: vsim2 { 1535 regulator-name = "pp2760_vsim2_x"; 1536 regulator-min-microvolt = <2700000>; 1537 regulator-max-microvolt = <2760000>; 1538 regulator-enable-ramp-delay = <540>; 1539 }; 1540 1541 mt6366_vsram_gpu_reg: vsram-gpu { 1542 regulator-name = "pp0900_dvdd_sram_gpu"; 1543 regulator-min-microvolt = <850000>; 1544 regulator-max-microvolt = <1050000>; 1545 regulator-ramp-delay = <6250>; 1546 regulator-enable-ramp-delay = <240>; 1547 regulator-coupled-with = <&mt6366_vgpu_reg>; 1548 regulator-coupled-max-spread = <10000>; 1549 }; 1550 1551 mt6366_vsram_others_reg: vsram-others { 1552 regulator-name = "pp0900_dvdd_sram_core"; 1553 regulator-min-microvolt = <900000>; 1554 regulator-max-microvolt = <900000>; 1555 regulator-ramp-delay = <6250>; 1556 regulator-enable-ramp-delay = <240>; 1557 regulator-always-on; 1558 }; 1559 1560 mt6366_vsram_proc11_reg: vsram-proc11 { 1561 regulator-name = "pp0900_dvdd_sram_bc"; 1562 regulator-min-microvolt = <850000>; 1563 regulator-max-microvolt = <1120000>; 1564 regulator-ramp-delay = <6250>; 1565 regulator-enable-ramp-delay = <240>; 1566 regulator-always-on; 1567 }; 1568 1569 mt6366_vsram_proc12_reg: vsram-proc12 { 1570 regulator-name = "pp0900_dvdd_sram_lc"; 1571 regulator-min-microvolt = <850000>; 1572 regulator-max-microvolt = <1120000>; 1573 regulator-ramp-delay = <6250>; 1574 regulator-enable-ramp-delay = <240>; 1575 regulator-always-on; 1576 }; 1577 1578 vusb { 1579 regulator-name = "pp3070_vusb"; 1580 regulator-min-microvolt = <3000000>; 1581 regulator-max-microvolt = <3070000>; 1582 regulator-enable-ramp-delay = <270>; 1583 regulator-always-on; 1584 }; 1585 1586 vxo22 { 1587 regulator-name = "pp2240_vxo22"; 1588 regulator-min-microvolt = <2200000>; 1589 regulator-max-microvolt = <2240000>; 1590 regulator-enable-ramp-delay = <120>; 1591 /* Feeds DCXO internally */ 1592 regulator-always-on; 1593 }; 1594 }; 1595 1596 rtc { 1597 compatible = "mediatek,mt6366-rtc", "mediatek,mt6358-rtc"; 1598 }; 1599 }; 1600}; 1601 1602&scp { 1603 pinctrl-names = "default"; 1604 pinctrl-0 = <&scp_pins>; 1605 firmware-name = "mediatek/mt8186/scp.img"; 1606 memory-region = <&scp_mem>; 1607 status = "okay"; 1608 1609 cros-ec-rpmsg { 1610 compatible = "google,cros-ec-rpmsg"; 1611 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1612 }; 1613}; 1614 1615&spi1 { 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&spi1_pins>; 1618 mediatek,pad-select = <0>; 1619 status = "okay"; 1620 1621 cros_ec: ec@0 { 1622 compatible = "google,cros-ec-spi"; 1623 reg = <0>; 1624 interrupts-extended = <&pio 13 IRQ_TYPE_LEVEL_LOW>; 1625 pinctrl-names = "default"; 1626 pinctrl-0 = <&ec_ap_int>; 1627 spi-max-frequency = <1000000>; 1628 1629 i2c_tunnel: i2c-tunnel { 1630 compatible = "google,cros-ec-i2c-tunnel"; 1631 google,remote-bus = <1>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 }; 1635 1636 typec { 1637 compatible = "google,cros-ec-typec"; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 usb_c0: connector@0 { 1642 compatible = "usb-c-connector"; 1643 reg = <0>; 1644 label = "left"; 1645 power-role = "dual"; 1646 data-role = "host"; 1647 try-power-role = "source"; 1648 }; 1649 1650 usb_c1: connector@1 { 1651 compatible = "usb-c-connector"; 1652 reg = <1>; 1653 label = "right"; 1654 power-role = "dual"; 1655 data-role = "host"; 1656 try-power-role = "source"; 1657 }; 1658 }; 1659 }; 1660}; 1661 1662&spi2 { 1663 pinctrl-names = "default"; 1664 pinctrl-0 = <&spi2_pins>; 1665 cs-gpios = <&pio 45 GPIO_ACTIVE_LOW>; 1666 mediatek,pad-select = <0>; 1667 status = "okay"; 1668 1669 tpm@0 { 1670 compatible = "google,cr50"; 1671 reg = <0>; 1672 interrupts-extended = <&pio 15 IRQ_TYPE_EDGE_RISING>; 1673 pinctrl-names = "default"; 1674 pinctrl-0 = <&gsc_int>; 1675 spi-max-frequency = <1000000>; 1676 }; 1677}; 1678 1679&ssusb0 { 1680 status = "okay"; 1681}; 1682 1683&ssusb1 { 1684 status = "okay"; 1685}; 1686 1687&u3phy0 { 1688 status = "okay"; 1689}; 1690 1691&u3phy1 { 1692 status = "okay"; 1693}; 1694 1695&uart0 { 1696 status = "okay"; 1697}; 1698 1699&usb_host0 { 1700 vbus-supply = <&pp3300_s3>; 1701 status = "okay"; 1702}; 1703 1704&usb_host1 { 1705 vbus-supply = <&usb_p1_vbus>; 1706 status = "okay"; 1707}; 1708 1709&watchdog { 1710 mediatek,reset-by-toprgu; 1711}; 1712 1713#include <arm/cros-ec-keyboard.dtsi> 1714#include <arm/cros-ec-sbs.dtsi> 1715