xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-evb.dts (revision db6da59cf27b5661ced03754ae0550f8914eda9e) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8/dts-v1/;
9#include "mt8183.dtsi"
10#include "mt6358.dtsi"
11
12/ {
13	model = "MediaTek MT8183 evaluation board";
14	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
15
16	aliases {
17		serial0 = &uart0;
18	};
19
20	memory@40000000 {
21		device_type = "memory";
22		reg = <0 0x40000000 0 0x80000000>;
23	};
24
25	chosen {
26		stdout-path = "serial0:921600n8";
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33		scp_mem_reserved: scp_mem_region {
34			compatible = "shared-dma-pool";
35			reg = <0 0x50000000 0 0x2900000>;
36			no-map;
37		};
38	};
39
40	ntc@0 {
41		compatible = "murata,ncp03wf104";
42		pullup-uv = <1800000>;
43		pullup-ohm = <390000>;
44		pulldown-ohm = <0>;
45		io-channels = <&auxadc 0>;
46	};
47};
48
49&auxadc {
50	status = "okay";
51};
52
53&gpu {
54	mali-supply = <&mt6358_vgpu_reg>;
55};
56
57&i2c0 {
58	pinctrl-names = "default";
59	pinctrl-0 = <&i2c_pins_0>;
60	status = "okay";
61	clock-frequency = <100000>;
62};
63
64&i2c1 {
65	pinctrl-names = "default";
66	pinctrl-0 = <&i2c_pins_1>;
67	status = "okay";
68	clock-frequency = <100000>;
69};
70
71&i2c2 {
72	pinctrl-names = "default";
73	pinctrl-0 = <&i2c_pins_2>;
74	status = "okay";
75	clock-frequency = <100000>;
76};
77
78&i2c3 {
79	pinctrl-names = "default";
80	pinctrl-0 = <&i2c_pins_3>;
81	status = "okay";
82	clock-frequency = <100000>;
83};
84
85&i2c4 {
86	pinctrl-names = "default";
87	pinctrl-0 = <&i2c_pins_4>;
88	status = "okay";
89	clock-frequency = <1000000>;
90};
91
92&i2c5 {
93	pinctrl-names = "default";
94	pinctrl-0 = <&i2c_pins_5>;
95	status = "okay";
96	clock-frequency = <1000000>;
97};
98
99&mmc0 {
100	status = "okay";
101	pinctrl-names = "default", "state_uhs";
102	pinctrl-0 = <&mmc0_pins_default>;
103	pinctrl-1 = <&mmc0_pins_uhs>;
104	bus-width = <8>;
105	max-frequency = <200000000>;
106	cap-mmc-highspeed;
107	mmc-hs200-1_8v;
108	mmc-hs400-1_8v;
109	cap-mmc-hw-reset;
110	no-sdio;
111	no-sd;
112	hs400-ds-delay = <0x12814>;
113	vmmc-supply = <&mt6358_vemc_reg>;
114	vqmmc-supply = <&mt6358_vio18_reg>;
115	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
116	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
117	non-removable;
118};
119
120&mmc1 {
121	status = "okay";
122	pinctrl-names = "default", "state_uhs";
123	pinctrl-0 = <&mmc1_pins_default>;
124	pinctrl-1 = <&mmc1_pins_uhs>;
125	bus-width = <4>;
126	max-frequency = <200000000>;
127	cap-sd-highspeed;
128	sd-uhs-sdr50;
129	sd-uhs-sdr104;
130	cap-sdio-irq;
131	no-mmc;
132	no-sd;
133	vmmc-supply = <&mt6358_vmch_reg>;
134	vqmmc-supply = <&mt6358_vmc_reg>;
135	keep-power-in-suspend;
136	wakeup-source;
137	non-removable;
138};
139
140&mt6358_vgpu_reg {
141	regulator-min-microvolt = <625000>;
142	regulator-max-microvolt = <900000>;
143
144	regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
145	regulator-coupled-max-spread = <100000>;
146};
147
148&mt6358_vsram_gpu_reg {
149	regulator-min-microvolt = <850000>;
150	regulator-max-microvolt = <1000000>;
151
152	regulator-coupled-with = <&mt6358_vgpu_reg>;
153	regulator-coupled-max-spread = <100000>;
154};
155
156&pio {
157	i2c_pins_0: i2c0{
158		pins_i2c{
159			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
160				 <PINMUX_GPIO83__FUNC_SCL0>;
161			mediatek,pull-up-adv = <3>;
162			mediatek,drive-strength-adv = <00>;
163		};
164	};
165
166	i2c_pins_1: i2c1{
167		pins_i2c{
168			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
169				 <PINMUX_GPIO84__FUNC_SCL1>;
170			mediatek,pull-up-adv = <3>;
171			mediatek,drive-strength-adv = <00>;
172		};
173	};
174
175	i2c_pins_2: i2c2{
176		pins_i2c{
177			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
178				 <PINMUX_GPIO104__FUNC_SDA2>;
179			mediatek,pull-up-adv = <3>;
180			mediatek,drive-strength-adv = <00>;
181		};
182	};
183
184	i2c_pins_3: i2c3{
185		pins_i2c{
186			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
187				 <PINMUX_GPIO51__FUNC_SDA3>;
188			mediatek,pull-up-adv = <3>;
189			mediatek,drive-strength-adv = <00>;
190		};
191	};
192
193	i2c_pins_4: i2c4{
194		pins_i2c{
195			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
196				 <PINMUX_GPIO106__FUNC_SDA4>;
197			mediatek,pull-up-adv = <3>;
198			mediatek,drive-strength-adv = <00>;
199		};
200	};
201
202	i2c_pins_5: i2c5{
203		pins_i2c{
204			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
205				 <PINMUX_GPIO49__FUNC_SDA5>;
206			mediatek,pull-up-adv = <3>;
207			mediatek,drive-strength-adv = <00>;
208		};
209	};
210
211	spi_pins_0: spi0{
212		pins_spi{
213			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
214				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
215				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
216				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
217			bias-disable;
218		};
219	};
220
221	mmc0_pins_default: mmc0default {
222		pins_cmd_dat {
223			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
224				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
225				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
226				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
227				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
228				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
229				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
230				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
231				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
232			input-enable;
233			bias-pull-up;
234		};
235
236		pins_clk {
237			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
238			bias-pull-down;
239		};
240
241		pins_rst {
242			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
243			bias-pull-up;
244		};
245	};
246
247	mmc0_pins_uhs: mmc0 {
248		pins_cmd_dat {
249			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
250				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
251				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
252				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
253				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
254				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
255				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
256				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
257				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
258			input-enable;
259			drive-strength = <MTK_DRIVE_10mA>;
260			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
261		};
262
263		pins_clk {
264			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
265			drive-strength = <MTK_DRIVE_10mA>;
266			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
267		};
268
269		pins_ds {
270			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
271			drive-strength = <MTK_DRIVE_10mA>;
272			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
273		};
274
275		pins_rst {
276			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
277			drive-strength = <MTK_DRIVE_10mA>;
278			bias-pull-up;
279		};
280	};
281
282	mmc1_pins_default: mmc1default {
283		pins_cmd_dat {
284			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
285				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
286				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
287				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
288				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
289			input-enable;
290			bias-pull-up;
291		};
292
293		pins_clk {
294			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
295			input-enable;
296			bias-pull-down;
297		};
298
299		pins_pmu {
300			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
301				   <PINMUX_GPIO166__FUNC_GPIO166>;
302			output-high;
303		};
304	};
305
306	mmc1_pins_uhs: mmc1 {
307		pins_cmd_dat {
308			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
309				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
310				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
311				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
312				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
313			drive-strength = <MTK_DRIVE_6mA>;
314			input-enable;
315			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
316		};
317
318		pins_clk {
319			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
320			drive-strength = <MTK_DRIVE_6mA>;
321			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
322			input-enable;
323		};
324	};
325
326	spi_pins_1: spi1{
327		pins_spi{
328			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
329				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
330				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
331				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
332			bias-disable;
333		};
334	};
335
336	spi_pins_2: spi2{
337		pins_spi{
338			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
339				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
340				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
341				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
342			bias-disable;
343		};
344	};
345
346	spi_pins_3: spi3{
347		pins_spi{
348			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
349				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
350				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
351				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
352			bias-disable;
353		};
354	};
355
356	spi_pins_4: spi4{
357		pins_spi{
358			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
359				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
360				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
361				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
362			bias-disable;
363		};
364	};
365
366	spi_pins_5: spi5{
367		pins_spi{
368			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
369				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
370				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
371				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
372			bias-disable;
373		};
374	};
375
376	pwm_pins_1: pwm1 {
377		pins_pwm {
378			pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
379		};
380	};
381};
382
383&mfg {
384	domain-supply = <&mt6358_vgpu_reg>;
385};
386
387&spi0 {
388	pinctrl-names = "default";
389	pinctrl-0 = <&spi_pins_0>;
390	mediatek,pad-select = <0>;
391	status = "okay";
392};
393
394&spi1 {
395	pinctrl-names = "default";
396	pinctrl-0 = <&spi_pins_1>;
397	mediatek,pad-select = <0>;
398	status = "okay";
399};
400
401&spi2 {
402	pinctrl-names = "default";
403	pinctrl-0 = <&spi_pins_2>;
404	mediatek,pad-select = <0>;
405	status = "okay";
406};
407
408&spi3 {
409	pinctrl-names = "default";
410	pinctrl-0 = <&spi_pins_3>;
411	mediatek,pad-select = <0>;
412	status = "okay";
413};
414
415&spi4 {
416	pinctrl-names = "default";
417	pinctrl-0 = <&spi_pins_4>;
418	mediatek,pad-select = <0>;
419	status = "okay";
420};
421
422&spi5 {
423	pinctrl-names = "default";
424	pinctrl-0 = <&spi_pins_5>;
425	mediatek,pad-select = <0>;
426	status = "okay";
427
428};
429
430&cci {
431	proc-supply = <&mt6358_vproc12_reg>;
432};
433
434&cpu0 {
435	proc-supply = <&mt6358_vproc12_reg>;
436};
437
438&cpu1 {
439	proc-supply = <&mt6358_vproc12_reg>;
440};
441
442&cpu2 {
443	proc-supply = <&mt6358_vproc12_reg>;
444};
445
446&cpu3 {
447	proc-supply = <&mt6358_vproc12_reg>;
448};
449
450&cpu4 {
451	proc-supply = <&mt6358_vproc11_reg>;
452};
453
454&cpu5 {
455	proc-supply = <&mt6358_vproc11_reg>;
456};
457
458&cpu6 {
459	proc-supply = <&mt6358_vproc11_reg>;
460};
461
462&cpu7 {
463	proc-supply = <&mt6358_vproc11_reg>;
464};
465
466&uart0 {
467	status = "okay";
468};
469
470&pwm1 {
471	status = "okay";
472	pinctrl-0 = <&pwm_pins_1>;
473	pinctrl-names = "default";
474};
475