1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8/dts-v1/; 9#include "mt8183.dtsi" 10#include "mt6358.dtsi" 11 12/ { 13 model = "MediaTek MT8183 evaluation board"; 14 compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; 15 16 aliases { 17 serial0 = &uart0; 18 }; 19 20 memory@40000000 { 21 device_type = "memory"; 22 reg = <0 0x40000000 0 0x80000000>; 23 }; 24 25 chosen { 26 stdout-path = "serial0:921600n8"; 27 }; 28 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 scp_mem_reserved: scp_mem_region { 34 compatible = "shared-dma-pool"; 35 reg = <0 0x50000000 0 0x2900000>; 36 no-map; 37 }; 38 }; 39 40 ntc@0 { 41 compatible = "murata,ncp03wf104"; 42 pullup-uv = <1800000>; 43 pullup-ohm = <390000>; 44 pulldown-ohm = <0>; 45 io-channels = <&auxadc 0>; 46 }; 47}; 48 49&auxadc { 50 status = "okay"; 51}; 52 53&gpu { 54 mali-supply = <&mt6358_vgpu_reg>; 55}; 56 57&i2c0 { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&i2c_pins_0>; 60 status = "okay"; 61 clock-frequency = <100000>; 62}; 63 64&i2c1 { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&i2c_pins_1>; 67 status = "okay"; 68 clock-frequency = <100000>; 69}; 70 71&i2c2 { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&i2c_pins_2>; 74 status = "okay"; 75 clock-frequency = <100000>; 76}; 77 78&i2c3 { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&i2c_pins_3>; 81 status = "okay"; 82 clock-frequency = <100000>; 83}; 84 85&i2c4 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&i2c_pins_4>; 88 status = "okay"; 89 clock-frequency = <1000000>; 90}; 91 92&i2c5 { 93 pinctrl-names = "default"; 94 pinctrl-0 = <&i2c_pins_5>; 95 status = "okay"; 96 clock-frequency = <1000000>; 97}; 98 99&mmc0 { 100 status = "okay"; 101 pinctrl-names = "default", "state_uhs"; 102 pinctrl-0 = <&mmc0_pins_default>; 103 pinctrl-1 = <&mmc0_pins_uhs>; 104 bus-width = <8>; 105 max-frequency = <200000000>; 106 cap-mmc-highspeed; 107 mmc-hs200-1_8v; 108 mmc-hs400-1_8v; 109 cap-mmc-hw-reset; 110 no-sdio; 111 no-sd; 112 hs400-ds-delay = <0x12814>; 113 vmmc-supply = <&mt6358_vemc_reg>; 114 vqmmc-supply = <&mt6358_vio18_reg>; 115 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 116 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 117 non-removable; 118}; 119 120&mmc1 { 121 status = "okay"; 122 pinctrl-names = "default", "state_uhs"; 123 pinctrl-0 = <&mmc1_pins_default>; 124 pinctrl-1 = <&mmc1_pins_uhs>; 125 bus-width = <4>; 126 max-frequency = <200000000>; 127 cap-sd-highspeed; 128 sd-uhs-sdr50; 129 sd-uhs-sdr104; 130 cap-sdio-irq; 131 no-mmc; 132 no-sd; 133 vmmc-supply = <&mt6358_vmch_reg>; 134 vqmmc-supply = <&mt6358_vmc_reg>; 135 keep-power-in-suspend; 136 wakeup-source; 137 non-removable; 138}; 139 140&mt6358_vgpu_reg { 141 regulator-coupled-with = <&mt6358_vsram_gpu_reg>; 142 regulator-coupled-max-spread = <100000>; 143}; 144 145&mt6358_vsram_gpu_reg { 146 regulator-coupled-with = <&mt6358_vgpu_reg>; 147 regulator-coupled-max-spread = <100000>; 148}; 149 150&pio { 151 i2c_pins_0: i2c0{ 152 pins_i2c{ 153 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 154 <PINMUX_GPIO83__FUNC_SCL0>; 155 mediatek,pull-up-adv = <3>; 156 mediatek,drive-strength-adv = <00>; 157 }; 158 }; 159 160 i2c_pins_1: i2c1{ 161 pins_i2c{ 162 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 163 <PINMUX_GPIO84__FUNC_SCL1>; 164 mediatek,pull-up-adv = <3>; 165 mediatek,drive-strength-adv = <00>; 166 }; 167 }; 168 169 i2c_pins_2: i2c2{ 170 pins_i2c{ 171 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 172 <PINMUX_GPIO104__FUNC_SDA2>; 173 mediatek,pull-up-adv = <3>; 174 mediatek,drive-strength-adv = <00>; 175 }; 176 }; 177 178 i2c_pins_3: i2c3{ 179 pins_i2c{ 180 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 181 <PINMUX_GPIO51__FUNC_SDA3>; 182 mediatek,pull-up-adv = <3>; 183 mediatek,drive-strength-adv = <00>; 184 }; 185 }; 186 187 i2c_pins_4: i2c4{ 188 pins_i2c{ 189 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 190 <PINMUX_GPIO106__FUNC_SDA4>; 191 mediatek,pull-up-adv = <3>; 192 mediatek,drive-strength-adv = <00>; 193 }; 194 }; 195 196 i2c_pins_5: i2c5{ 197 pins_i2c{ 198 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 199 <PINMUX_GPIO49__FUNC_SDA5>; 200 mediatek,pull-up-adv = <3>; 201 mediatek,drive-strength-adv = <00>; 202 }; 203 }; 204 205 spi_pins_0: spi0{ 206 pins_spi{ 207 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 208 <PINMUX_GPIO86__FUNC_SPI0_CSB>, 209 <PINMUX_GPIO87__FUNC_SPI0_MO>, 210 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 211 bias-disable; 212 }; 213 }; 214 215 mmc0_pins_default: mmc0default { 216 pins_cmd_dat { 217 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 218 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 219 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 220 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 221 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 222 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 223 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 224 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 225 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 226 input-enable; 227 bias-pull-up; 228 }; 229 230 pins_clk { 231 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 232 bias-pull-down; 233 }; 234 235 pins_rst { 236 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 237 bias-pull-up; 238 }; 239 }; 240 241 mmc0_pins_uhs: mmc0 { 242 pins_cmd_dat { 243 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 244 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 245 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 246 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 247 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 248 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 249 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 250 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 251 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 252 input-enable; 253 drive-strength = <MTK_DRIVE_10mA>; 254 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 255 }; 256 257 pins_clk { 258 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 259 drive-strength = <MTK_DRIVE_10mA>; 260 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 261 }; 262 263 pins_ds { 264 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 265 drive-strength = <MTK_DRIVE_10mA>; 266 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 267 }; 268 269 pins_rst { 270 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 271 drive-strength = <MTK_DRIVE_10mA>; 272 bias-pull-up; 273 }; 274 }; 275 276 mmc1_pins_default: mmc1default { 277 pins_cmd_dat { 278 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 279 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 280 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 281 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 282 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 283 input-enable; 284 bias-pull-up; 285 }; 286 287 pins_clk { 288 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 289 input-enable; 290 bias-pull-down; 291 }; 292 293 pins_pmu { 294 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>, 295 <PINMUX_GPIO166__FUNC_GPIO166>; 296 output-high; 297 }; 298 }; 299 300 mmc1_pins_uhs: mmc1 { 301 pins_cmd_dat { 302 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 303 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 304 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 305 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 306 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 307 drive-strength = <MTK_DRIVE_6mA>; 308 input-enable; 309 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 310 }; 311 312 pins_clk { 313 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 314 drive-strength = <MTK_DRIVE_6mA>; 315 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 316 input-enable; 317 }; 318 }; 319 320 spi_pins_1: spi1{ 321 pins_spi{ 322 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 323 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 324 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 325 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 326 bias-disable; 327 }; 328 }; 329 330 spi_pins_2: spi2{ 331 pins_spi{ 332 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 333 <PINMUX_GPIO1__FUNC_SPI2_MO>, 334 <PINMUX_GPIO2__FUNC_SPI2_CLK>, 335 <PINMUX_GPIO94__FUNC_SPI2_MI>; 336 bias-disable; 337 }; 338 }; 339 340 spi_pins_3: spi3{ 341 pins_spi{ 342 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 343 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 344 <PINMUX_GPIO23__FUNC_SPI3_MO>, 345 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 346 bias-disable; 347 }; 348 }; 349 350 spi_pins_4: spi4{ 351 pins_spi{ 352 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 353 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 354 <PINMUX_GPIO19__FUNC_SPI4_MO>, 355 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 356 bias-disable; 357 }; 358 }; 359 360 spi_pins_5: spi5{ 361 pins_spi{ 362 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 363 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 364 <PINMUX_GPIO15__FUNC_SPI5_MO>, 365 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 366 bias-disable; 367 }; 368 }; 369 370 pwm_pins_1: pwm1 { 371 pins_pwm { 372 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>; 373 }; 374 }; 375}; 376 377&mfg { 378 domain-supply = <&mt6358_vgpu_reg>; 379}; 380 381&spi0 { 382 pinctrl-names = "default"; 383 pinctrl-0 = <&spi_pins_0>; 384 mediatek,pad-select = <0>; 385 status = "okay"; 386}; 387 388&spi1 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&spi_pins_1>; 391 mediatek,pad-select = <0>; 392 status = "okay"; 393}; 394 395&spi2 { 396 pinctrl-names = "default"; 397 pinctrl-0 = <&spi_pins_2>; 398 mediatek,pad-select = <0>; 399 status = "okay"; 400}; 401 402&spi3 { 403 pinctrl-names = "default"; 404 pinctrl-0 = <&spi_pins_3>; 405 mediatek,pad-select = <0>; 406 status = "okay"; 407}; 408 409&spi4 { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&spi_pins_4>; 412 mediatek,pad-select = <0>; 413 status = "okay"; 414}; 415 416&spi5 { 417 pinctrl-names = "default"; 418 pinctrl-0 = <&spi_pins_5>; 419 mediatek,pad-select = <0>; 420 status = "okay"; 421 422}; 423 424&cci { 425 proc-supply = <&mt6358_vproc12_reg>; 426}; 427 428&cpu0 { 429 proc-supply = <&mt6358_vproc12_reg>; 430}; 431 432&cpu1 { 433 proc-supply = <&mt6358_vproc12_reg>; 434}; 435 436&cpu2 { 437 proc-supply = <&mt6358_vproc12_reg>; 438}; 439 440&cpu3 { 441 proc-supply = <&mt6358_vproc12_reg>; 442}; 443 444&cpu4 { 445 proc-supply = <&mt6358_vproc11_reg>; 446}; 447 448&cpu5 { 449 proc-supply = <&mt6358_vproc11_reg>; 450}; 451 452&cpu6 { 453 proc-supply = <&mt6358_vproc11_reg>; 454}; 455 456&cpu7 { 457 proc-supply = <&mt6358_vproc11_reg>; 458}; 459 460&uart0 { 461 status = "okay"; 462}; 463 464&pwm1 { 465 status = "okay"; 466 pinctrl-0 = <&pwm_pins_1>; 467 pinctrl-names = "default"; 468}; 469