xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt8183-evb.dts (revision 2d9ad4cfaf4d32a64a4ed556e5bcab9121215026) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8/dts-v1/;
9#include "mt8183.dtsi"
10#include "mt6358.dtsi"
11
12/ {
13	model = "MediaTek MT8183 evaluation board";
14	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
15
16	aliases {
17		serial0 = &uart0;
18	};
19
20	memory@40000000 {
21		device_type = "memory";
22		reg = <0 0x40000000 0 0x80000000>;
23	};
24
25	chosen {
26		stdout-path = "serial0:921600n8";
27	};
28};
29
30&auxadc {
31	status = "okay";
32};
33
34&i2c0 {
35	pinctrl-names = "default";
36	pinctrl-0 = <&i2c_pins_0>;
37	status = "okay";
38	clock-frequency = <100000>;
39};
40
41&i2c1 {
42	pinctrl-names = "default";
43	pinctrl-0 = <&i2c_pins_1>;
44	status = "okay";
45	clock-frequency = <100000>;
46};
47
48&i2c2 {
49	pinctrl-names = "default";
50	pinctrl-0 = <&i2c_pins_2>;
51	status = "okay";
52	clock-frequency = <100000>;
53};
54
55&i2c3 {
56	pinctrl-names = "default";
57	pinctrl-0 = <&i2c_pins_3>;
58	status = "okay";
59	clock-frequency = <100000>;
60};
61
62&i2c4 {
63	pinctrl-names = "default";
64	pinctrl-0 = <&i2c_pins_4>;
65	status = "okay";
66	clock-frequency = <1000000>;
67};
68
69&i2c5 {
70	pinctrl-names = "default";
71	pinctrl-0 = <&i2c_pins_5>;
72	status = "okay";
73	clock-frequency = <1000000>;
74};
75
76&mmc0 {
77	status = "okay";
78	pinctrl-names = "default", "state_uhs";
79	pinctrl-0 = <&mmc0_pins_default>;
80	pinctrl-1 = <&mmc0_pins_uhs>;
81	bus-width = <8>;
82	max-frequency = <200000000>;
83	cap-mmc-highspeed;
84	mmc-hs200-1_8v;
85	mmc-hs400-1_8v;
86	cap-mmc-hw-reset;
87	no-sdio;
88	no-sd;
89	hs400-ds-delay = <0x12814>;
90	vmmc-supply = <&mt6358_vemc_reg>;
91	vqmmc-supply = <&mt6358_vio18_reg>;
92	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
93	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
94	non-removable;
95};
96
97&mmc1 {
98	status = "okay";
99	pinctrl-names = "default", "state_uhs";
100	pinctrl-0 = <&mmc1_pins_default>;
101	pinctrl-1 = <&mmc1_pins_uhs>;
102	bus-width = <4>;
103	max-frequency = <200000000>;
104	cap-sd-highspeed;
105	sd-uhs-sdr50;
106	sd-uhs-sdr104;
107	cap-sdio-irq;
108	no-mmc;
109	no-sd;
110	vmmc-supply = <&mt6358_vmch_reg>;
111	vqmmc-supply = <&mt6358_vmc_reg>;
112	keep-power-in-suspend;
113	enable-sdio-wakeup;
114	non-removable;
115};
116
117&pio {
118	i2c_pins_0: i2c0{
119		pins_i2c{
120			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
121				 <PINMUX_GPIO83__FUNC_SCL0>;
122			mediatek,pull-up-adv = <3>;
123			mediatek,drive-strength-adv = <00>;
124		};
125	};
126
127	i2c_pins_1: i2c1{
128		pins_i2c{
129			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
130				 <PINMUX_GPIO84__FUNC_SCL1>;
131			mediatek,pull-up-adv = <3>;
132			mediatek,drive-strength-adv = <00>;
133		};
134	};
135
136	i2c_pins_2: i2c2{
137		pins_i2c{
138			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
139				 <PINMUX_GPIO104__FUNC_SDA2>;
140			mediatek,pull-up-adv = <3>;
141			mediatek,drive-strength-adv = <00>;
142		};
143	};
144
145	i2c_pins_3: i2c3{
146		pins_i2c{
147			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
148				 <PINMUX_GPIO51__FUNC_SDA3>;
149			mediatek,pull-up-adv = <3>;
150			mediatek,drive-strength-adv = <00>;
151		};
152	};
153
154	i2c_pins_4: i2c4{
155		pins_i2c{
156			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
157				 <PINMUX_GPIO106__FUNC_SDA4>;
158			mediatek,pull-up-adv = <3>;
159			mediatek,drive-strength-adv = <00>;
160		};
161	};
162
163	i2c_pins_5: i2c5{
164		pins_i2c{
165			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
166				 <PINMUX_GPIO49__FUNC_SDA5>;
167			mediatek,pull-up-adv = <3>;
168			mediatek,drive-strength-adv = <00>;
169		};
170	};
171
172	spi_pins_0: spi0{
173		pins_spi{
174			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
175				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
176				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
177				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
178			bias-disable;
179		};
180	};
181
182	mmc0_pins_default: mmc0default {
183		pins_cmd_dat {
184			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
185				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
186				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
187				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
188				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
189				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
190				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
191				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
192				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
193			input-enable;
194			bias-pull-up;
195		};
196
197		pins_clk {
198			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
199			bias-pull-down;
200		};
201
202		pins_rst {
203			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
204			bias-pull-up;
205		};
206	};
207
208	mmc0_pins_uhs: mmc0 {
209		pins_cmd_dat {
210			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
211				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
212				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
213				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
214				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
215				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
216				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
217				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
218				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
219			input-enable;
220			drive-strength = <MTK_DRIVE_10mA>;
221			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
222		};
223
224		pins_clk {
225			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
226			drive-strength = <MTK_DRIVE_10mA>;
227			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
228		};
229
230		pins_ds {
231			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
232			drive-strength = <MTK_DRIVE_10mA>;
233			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
234		};
235
236		pins_rst {
237			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
238			drive-strength = <MTK_DRIVE_10mA>;
239			bias-pull-up;
240		};
241	};
242
243	mmc1_pins_default: mmc1default {
244		pins_cmd_dat {
245			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
246				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
247				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
248				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
249				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
250			input-enable;
251			bias-pull-up;
252		};
253
254		pins_clk {
255			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
256			input-enable;
257			bias-pull-down;
258		};
259
260		pins_pmu {
261			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
262				   <PINMUX_GPIO166__FUNC_GPIO166>;
263			output-high;
264		};
265	};
266
267	mmc1_pins_uhs: mmc1 {
268		pins_cmd_dat {
269			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
270				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
271				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
272				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
273				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
274			drive-strength = <MTK_DRIVE_6mA>;
275			input-enable;
276			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
277		};
278
279		pins_clk {
280			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
281			drive-strength = <MTK_DRIVE_6mA>;
282			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
283			input-enable;
284		};
285	};
286
287	spi_pins_1: spi1{
288		pins_spi{
289			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
290				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
291				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
292				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
293			bias-disable;
294		};
295	};
296
297	spi_pins_2: spi2{
298		pins_spi{
299			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
300				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
301				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
302				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
303			bias-disable;
304		};
305	};
306
307	spi_pins_3: spi3{
308		pins_spi{
309			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
310				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
311				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
312				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
313			bias-disable;
314		};
315	};
316
317	spi_pins_4: spi4{
318		pins_spi{
319			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
320				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
321				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
322				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
323			bias-disable;
324		};
325	};
326
327	spi_pins_5: spi5{
328		pins_spi{
329			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
330				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
331				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
332				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
333			bias-disable;
334		};
335	};
336};
337
338&spi0 {
339	pinctrl-names = "default";
340	pinctrl-0 = <&spi_pins_0>;
341	mediatek,pad-select = <0>;
342	status = "okay";
343};
344
345&spi1 {
346	pinctrl-names = "default";
347	pinctrl-0 = <&spi_pins_1>;
348	mediatek,pad-select = <0>;
349	status = "okay";
350};
351
352&spi2 {
353	pinctrl-names = "default";
354	pinctrl-0 = <&spi_pins_2>;
355	mediatek,pad-select = <0>;
356	status = "okay";
357};
358
359&spi3 {
360	pinctrl-names = "default";
361	pinctrl-0 = <&spi_pins_3>;
362	mediatek,pad-select = <0>;
363	status = "okay";
364};
365
366&spi4 {
367	pinctrl-names = "default";
368	pinctrl-0 = <&spi_pins_4>;
369	mediatek,pad-select = <0>;
370	status = "okay";
371};
372
373&spi5 {
374	pinctrl-names = "default";
375	pinctrl-0 = <&spi_pins_5>;
376	mediatek,pad-select = <0>;
377	status = "okay";
378
379};
380
381&uart0 {
382	status = "okay";
383};
384