108d73b65SFabien Parent// SPDX-License-Identifier: GPL-2.0 208d73b65SFabien Parent/* 308d73b65SFabien Parent * Copyright (c) 2020 MediaTek Inc. 408d73b65SFabien Parent * Copyright (c) 2020 BayLibre, SAS. 508d73b65SFabien Parent * Author: Fabien Parent <fparent@baylibre.com> 608d73b65SFabien Parent */ 708d73b65SFabien Parent 808d73b65SFabien Parent#include <dt-bindings/clock/mt8167-clk.h> 908d73b65SFabien Parent#include <dt-bindings/memory/mt8167-larb-port.h> 10763e13f2SFabien Parent#include <dt-bindings/power/mt8167-power.h> 1108d73b65SFabien Parent 1208d73b65SFabien Parent#include "mt8167-pinfunc.h" 1308d73b65SFabien Parent 1408d73b65SFabien Parent#include "mt8516.dtsi" 1508d73b65SFabien Parent 1608d73b65SFabien Parent/ { 1708d73b65SFabien Parent compatible = "mediatek,mt8167"; 1808d73b65SFabien Parent 1908d73b65SFabien Parent soc { 2008d73b65SFabien Parent topckgen: topckgen@10000000 { 2108d73b65SFabien Parent compatible = "mediatek,mt8167-topckgen", "syscon"; 2208d73b65SFabien Parent reg = <0 0x10000000 0 0x1000>; 2308d73b65SFabien Parent #clock-cells = <1>; 2408d73b65SFabien Parent }; 2508d73b65SFabien Parent 2608d73b65SFabien Parent infracfg: infracfg@10001000 { 2708d73b65SFabien Parent compatible = "mediatek,mt8167-infracfg", "syscon"; 2808d73b65SFabien Parent reg = <0 0x10001000 0 0x1000>; 2908d73b65SFabien Parent #clock-cells = <1>; 3008d73b65SFabien Parent }; 3108d73b65SFabien Parent 3208d73b65SFabien Parent apmixedsys: apmixedsys@10018000 { 3308d73b65SFabien Parent compatible = "mediatek,mt8167-apmixedsys", "syscon"; 3408d73b65SFabien Parent reg = <0 0x10018000 0 0x710>; 3508d73b65SFabien Parent #clock-cells = <1>; 3608d73b65SFabien Parent }; 3708d73b65SFabien Parent 38763e13f2SFabien Parent scpsys: syscon@10006000 { 39763e13f2SFabien Parent compatible = "syscon", "simple-mfd"; 40763e13f2SFabien Parent reg = <0 0x10006000 0 0x1000>; 41763e13f2SFabien Parent #power-domain-cells = <1>; 42763e13f2SFabien Parent 43763e13f2SFabien Parent spm: power-controller { 44763e13f2SFabien Parent compatible = "mediatek,mt8167-power-controller"; 45763e13f2SFabien Parent #address-cells = <1>; 46763e13f2SFabien Parent #size-cells = <0>; 47763e13f2SFabien Parent #power-domain-cells = <1>; 48763e13f2SFabien Parent 49763e13f2SFabien Parent /* power domains of the SoC */ 50763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MM { 51763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MM>; 52763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_SMI_MM>; 53763e13f2SFabien Parent clock-names = "mm"; 54763e13f2SFabien Parent #power-domain-cells = <0>; 55763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 56763e13f2SFabien Parent }; 57763e13f2SFabien Parent 58763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_VDEC { 59763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_VDEC>; 60763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_SMI_MM>, 61763e13f2SFabien Parent <&topckgen CLK_TOP_RG_VDEC>; 62763e13f2SFabien Parent clock-names = "mm", "vdec"; 63763e13f2SFabien Parent #power-domain-cells = <0>; 64763e13f2SFabien Parent }; 65763e13f2SFabien Parent 66763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_ISP { 67763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_ISP>; 68763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_SMI_MM>; 69763e13f2SFabien Parent clock-names = "mm"; 70763e13f2SFabien Parent #power-domain-cells = <0>; 71763e13f2SFabien Parent }; 72763e13f2SFabien Parent 73763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { 74763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>; 75763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, 76763e13f2SFabien Parent <&topckgen CLK_TOP_RG_SLOW_MFG>; 77763e13f2SFabien Parent clock-names = "axi_mfg", "mfg"; 78763e13f2SFabien Parent #address-cells = <1>; 79763e13f2SFabien Parent #size-cells = <0>; 80763e13f2SFabien Parent #power-domain-cells = <1>; 81763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 82763e13f2SFabien Parent 83763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MFG_2D { 84763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MFG_2D>; 85763e13f2SFabien Parent #address-cells = <1>; 86763e13f2SFabien Parent #size-cells = <0>; 87763e13f2SFabien Parent #power-domain-cells = <1>; 88763e13f2SFabien Parent 89763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MFG { 90763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MFG>; 91763e13f2SFabien Parent #power-domain-cells = <0>; 92763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 93763e13f2SFabien Parent }; 94763e13f2SFabien Parent }; 95763e13f2SFabien Parent }; 96763e13f2SFabien Parent 97763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_CONN { 98763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_CONN>; 99763e13f2SFabien Parent #power-domain-cells = <0>; 100763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 101763e13f2SFabien Parent }; 102763e13f2SFabien Parent }; 103763e13f2SFabien Parent }; 104763e13f2SFabien Parent 10508d73b65SFabien Parent imgsys: syscon@15000000 { 10608d73b65SFabien Parent compatible = "mediatek,mt8167-imgsys", "syscon"; 10708d73b65SFabien Parent reg = <0 0x15000000 0 0x1000>; 10808d73b65SFabien Parent #clock-cells = <1>; 10908d73b65SFabien Parent }; 11008d73b65SFabien Parent 11108d73b65SFabien Parent vdecsys: syscon@16000000 { 11208d73b65SFabien Parent compatible = "mediatek,mt8167-vdecsys", "syscon"; 11308d73b65SFabien Parent reg = <0 0x16000000 0 0x1000>; 11408d73b65SFabien Parent #clock-cells = <1>; 11508d73b65SFabien Parent }; 11608d73b65SFabien Parent 11708d73b65SFabien Parent pio: pinctrl@1000b000 { 11808d73b65SFabien Parent compatible = "mediatek,mt8167-pinctrl"; 11908d73b65SFabien Parent reg = <0 0x1000b000 0 0x1000>; 12008d73b65SFabien Parent mediatek,pctl-regmap = <&syscfg_pctl>; 12108d73b65SFabien Parent pins-are-numbered; 12208d73b65SFabien Parent gpio-controller; 12308d73b65SFabien Parent #gpio-cells = <2>; 12408d73b65SFabien Parent interrupt-controller; 12508d73b65SFabien Parent #interrupt-cells = <2>; 12608d73b65SFabien Parent interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 12708d73b65SFabien Parent }; 12897e37d44SFabien Parent 12997e37d44SFabien Parent mmsys: mmsys@14000000 { 13097e37d44SFabien Parent compatible = "mediatek,mt8167-mmsys", "syscon"; 13197e37d44SFabien Parent reg = <0 0x14000000 0 0x1000>; 13297e37d44SFabien Parent #clock-cells = <1>; 13397e37d44SFabien Parent }; 134e7ead62eSFabien Parent 135e7ead62eSFabien Parent smi_common: smi@14017000 { 136e7ead62eSFabien Parent compatible = "mediatek,mt8167-smi-common"; 137e7ead62eSFabien Parent reg = <0 0x14017000 0 0x1000>; 138e7ead62eSFabien Parent clocks = <&mmsys CLK_MM_SMI_COMMON>, 139e7ead62eSFabien Parent <&mmsys CLK_MM_SMI_COMMON>; 140e7ead62eSFabien Parent clock-names = "apb", "smi"; 141e7ead62eSFabien Parent power-domains = <&spm MT8167_POWER_DOMAIN_MM>; 142e7ead62eSFabien Parent }; 1431a191c97SFabien Parent 1441a191c97SFabien Parent larb0: larb@14016000 { 1451a191c97SFabien Parent compatible = "mediatek,mt8167-smi-larb"; 1461a191c97SFabien Parent reg = <0 0x14016000 0 0x1000>; 1471a191c97SFabien Parent mediatek,smi = <&smi_common>; 1481a191c97SFabien Parent clocks = <&mmsys CLK_MM_SMI_LARB0>, 1491a191c97SFabien Parent <&mmsys CLK_MM_SMI_LARB0>; 1501a191c97SFabien Parent clock-names = "apb", "smi"; 1511a191c97SFabien Parent power-domains = <&spm MT8167_POWER_DOMAIN_MM>; 1521a191c97SFabien Parent }; 1531a191c97SFabien Parent 1541a191c97SFabien Parent larb1: larb@15001000 { 1551a191c97SFabien Parent compatible = "mediatek,mt8167-smi-larb"; 1561a191c97SFabien Parent reg = <0 0x15001000 0 0x1000>; 1571a191c97SFabien Parent mediatek,smi = <&smi_common>; 1581a191c97SFabien Parent clocks = <&imgsys CLK_IMG_LARB1_SMI>, 1591a191c97SFabien Parent <&imgsys CLK_IMG_LARB1_SMI>; 1601a191c97SFabien Parent clock-names = "apb", "smi"; 1611a191c97SFabien Parent power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; 1621a191c97SFabien Parent }; 1631a191c97SFabien Parent 1641a191c97SFabien Parent larb2: larb@16010000 { 1651a191c97SFabien Parent compatible = "mediatek,mt8167-smi-larb"; 1661a191c97SFabien Parent reg = <0 0x16010000 0 0x1000>; 1671a191c97SFabien Parent mediatek,smi = <&smi_common>; 1681a191c97SFabien Parent clocks = <&vdecsys CLK_VDEC_CKEN>, 1691a191c97SFabien Parent <&vdecsys CLK_VDEC_LARB1_CKEN>; 1701a191c97SFabien Parent clock-names = "apb", "smi"; 1711a191c97SFabien Parent power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; 1721a191c97SFabien Parent }; 173*d9fb91fdSFabien Parent 174*d9fb91fdSFabien Parent iommu: m4u@10203000 { 175*d9fb91fdSFabien Parent compatible = "mediatek,mt8167-m4u"; 176*d9fb91fdSFabien Parent reg = <0 0x10203000 0 0x1000>; 177*d9fb91fdSFabien Parent mediatek,larbs = <&larb0 &larb1 &larb2>; 178*d9fb91fdSFabien Parent interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; 179*d9fb91fdSFabien Parent #iommu-cells = <1>; 180*d9fb91fdSFabien Parent }; 18108d73b65SFabien Parent }; 18208d73b65SFabien Parent}; 183