108d73b65SFabien Parent// SPDX-License-Identifier: GPL-2.0 208d73b65SFabien Parent/* 308d73b65SFabien Parent * Copyright (c) 2020 MediaTek Inc. 408d73b65SFabien Parent * Copyright (c) 2020 BayLibre, SAS. 508d73b65SFabien Parent * Author: Fabien Parent <fparent@baylibre.com> 608d73b65SFabien Parent */ 708d73b65SFabien Parent 808d73b65SFabien Parent#include <dt-bindings/clock/mt8167-clk.h> 908d73b65SFabien Parent#include <dt-bindings/memory/mt8167-larb-port.h> 10*763e13f2SFabien Parent#include <dt-bindings/power/mt8167-power.h> 1108d73b65SFabien Parent 1208d73b65SFabien Parent#include "mt8167-pinfunc.h" 1308d73b65SFabien Parent 1408d73b65SFabien Parent#include "mt8516.dtsi" 1508d73b65SFabien Parent 1608d73b65SFabien Parent/ { 1708d73b65SFabien Parent compatible = "mediatek,mt8167"; 1808d73b65SFabien Parent 1908d73b65SFabien Parent soc { 2008d73b65SFabien Parent topckgen: topckgen@10000000 { 2108d73b65SFabien Parent compatible = "mediatek,mt8167-topckgen", "syscon"; 2208d73b65SFabien Parent reg = <0 0x10000000 0 0x1000>; 2308d73b65SFabien Parent #clock-cells = <1>; 2408d73b65SFabien Parent }; 2508d73b65SFabien Parent 2608d73b65SFabien Parent infracfg: infracfg@10001000 { 2708d73b65SFabien Parent compatible = "mediatek,mt8167-infracfg", "syscon"; 2808d73b65SFabien Parent reg = <0 0x10001000 0 0x1000>; 2908d73b65SFabien Parent #clock-cells = <1>; 3008d73b65SFabien Parent }; 3108d73b65SFabien Parent 3208d73b65SFabien Parent apmixedsys: apmixedsys@10018000 { 3308d73b65SFabien Parent compatible = "mediatek,mt8167-apmixedsys", "syscon"; 3408d73b65SFabien Parent reg = <0 0x10018000 0 0x710>; 3508d73b65SFabien Parent #clock-cells = <1>; 3608d73b65SFabien Parent }; 3708d73b65SFabien Parent 38*763e13f2SFabien Parent scpsys: syscon@10006000 { 39*763e13f2SFabien Parent compatible = "syscon", "simple-mfd"; 40*763e13f2SFabien Parent reg = <0 0x10006000 0 0x1000>; 41*763e13f2SFabien Parent #power-domain-cells = <1>; 42*763e13f2SFabien Parent 43*763e13f2SFabien Parent spm: power-controller { 44*763e13f2SFabien Parent compatible = "mediatek,mt8167-power-controller"; 45*763e13f2SFabien Parent #address-cells = <1>; 46*763e13f2SFabien Parent #size-cells = <0>; 47*763e13f2SFabien Parent #power-domain-cells = <1>; 48*763e13f2SFabien Parent 49*763e13f2SFabien Parent /* power domains of the SoC */ 50*763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MM { 51*763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MM>; 52*763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_SMI_MM>; 53*763e13f2SFabien Parent clock-names = "mm"; 54*763e13f2SFabien Parent #power-domain-cells = <0>; 55*763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 56*763e13f2SFabien Parent }; 57*763e13f2SFabien Parent 58*763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_VDEC { 59*763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_VDEC>; 60*763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_SMI_MM>, 61*763e13f2SFabien Parent <&topckgen CLK_TOP_RG_VDEC>; 62*763e13f2SFabien Parent clock-names = "mm", "vdec"; 63*763e13f2SFabien Parent #power-domain-cells = <0>; 64*763e13f2SFabien Parent }; 65*763e13f2SFabien Parent 66*763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_ISP { 67*763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_ISP>; 68*763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_SMI_MM>; 69*763e13f2SFabien Parent clock-names = "mm"; 70*763e13f2SFabien Parent #power-domain-cells = <0>; 71*763e13f2SFabien Parent }; 72*763e13f2SFabien Parent 73*763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { 74*763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>; 75*763e13f2SFabien Parent clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, 76*763e13f2SFabien Parent <&topckgen CLK_TOP_RG_SLOW_MFG>; 77*763e13f2SFabien Parent clock-names = "axi_mfg", "mfg"; 78*763e13f2SFabien Parent #address-cells = <1>; 79*763e13f2SFabien Parent #size-cells = <0>; 80*763e13f2SFabien Parent #power-domain-cells = <1>; 81*763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 82*763e13f2SFabien Parent 83*763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MFG_2D { 84*763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MFG_2D>; 85*763e13f2SFabien Parent #address-cells = <1>; 86*763e13f2SFabien Parent #size-cells = <0>; 87*763e13f2SFabien Parent #power-domain-cells = <1>; 88*763e13f2SFabien Parent 89*763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_MFG { 90*763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_MFG>; 91*763e13f2SFabien Parent #power-domain-cells = <0>; 92*763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 93*763e13f2SFabien Parent }; 94*763e13f2SFabien Parent }; 95*763e13f2SFabien Parent }; 96*763e13f2SFabien Parent 97*763e13f2SFabien Parent power-domain@MT8167_POWER_DOMAIN_CONN { 98*763e13f2SFabien Parent reg = <MT8167_POWER_DOMAIN_CONN>; 99*763e13f2SFabien Parent #power-domain-cells = <0>; 100*763e13f2SFabien Parent mediatek,infracfg = <&infracfg>; 101*763e13f2SFabien Parent }; 102*763e13f2SFabien Parent }; 103*763e13f2SFabien Parent }; 104*763e13f2SFabien Parent 10508d73b65SFabien Parent imgsys: syscon@15000000 { 10608d73b65SFabien Parent compatible = "mediatek,mt8167-imgsys", "syscon"; 10708d73b65SFabien Parent reg = <0 0x15000000 0 0x1000>; 10808d73b65SFabien Parent #clock-cells = <1>; 10908d73b65SFabien Parent }; 11008d73b65SFabien Parent 11108d73b65SFabien Parent vdecsys: syscon@16000000 { 11208d73b65SFabien Parent compatible = "mediatek,mt8167-vdecsys", "syscon"; 11308d73b65SFabien Parent reg = <0 0x16000000 0 0x1000>; 11408d73b65SFabien Parent #clock-cells = <1>; 11508d73b65SFabien Parent }; 11608d73b65SFabien Parent 11708d73b65SFabien Parent pio: pinctrl@1000b000 { 11808d73b65SFabien Parent compatible = "mediatek,mt8167-pinctrl"; 11908d73b65SFabien Parent reg = <0 0x1000b000 0 0x1000>; 12008d73b65SFabien Parent mediatek,pctl-regmap = <&syscfg_pctl>; 12108d73b65SFabien Parent pins-are-numbered; 12208d73b65SFabien Parent gpio-controller; 12308d73b65SFabien Parent #gpio-cells = <2>; 12408d73b65SFabien Parent interrupt-controller; 12508d73b65SFabien Parent #interrupt-cells = <2>; 12608d73b65SFabien Parent interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 12708d73b65SFabien Parent }; 12808d73b65SFabien Parent }; 12908d73b65SFabien Parent}; 130