1*08d73b65SFabien Parent// SPDX-License-Identifier: GPL-2.0 2*08d73b65SFabien Parent/* 3*08d73b65SFabien Parent * Copyright (c) 2020 MediaTek Inc. 4*08d73b65SFabien Parent * Copyright (c) 2020 BayLibre, SAS. 5*08d73b65SFabien Parent * Author: Fabien Parent <fparent@baylibre.com> 6*08d73b65SFabien Parent */ 7*08d73b65SFabien Parent 8*08d73b65SFabien Parent#include <dt-bindings/clock/mt8167-clk.h> 9*08d73b65SFabien Parent#include <dt-bindings/memory/mt8167-larb-port.h> 10*08d73b65SFabien Parent 11*08d73b65SFabien Parent#include "mt8167-pinfunc.h" 12*08d73b65SFabien Parent 13*08d73b65SFabien Parent#include "mt8516.dtsi" 14*08d73b65SFabien Parent 15*08d73b65SFabien Parent/ { 16*08d73b65SFabien Parent compatible = "mediatek,mt8167"; 17*08d73b65SFabien Parent 18*08d73b65SFabien Parent soc { 19*08d73b65SFabien Parent topckgen: topckgen@10000000 { 20*08d73b65SFabien Parent compatible = "mediatek,mt8167-topckgen", "syscon"; 21*08d73b65SFabien Parent reg = <0 0x10000000 0 0x1000>; 22*08d73b65SFabien Parent #clock-cells = <1>; 23*08d73b65SFabien Parent }; 24*08d73b65SFabien Parent 25*08d73b65SFabien Parent infracfg: infracfg@10001000 { 26*08d73b65SFabien Parent compatible = "mediatek,mt8167-infracfg", "syscon"; 27*08d73b65SFabien Parent reg = <0 0x10001000 0 0x1000>; 28*08d73b65SFabien Parent #clock-cells = <1>; 29*08d73b65SFabien Parent }; 30*08d73b65SFabien Parent 31*08d73b65SFabien Parent apmixedsys: apmixedsys@10018000 { 32*08d73b65SFabien Parent compatible = "mediatek,mt8167-apmixedsys", "syscon"; 33*08d73b65SFabien Parent reg = <0 0x10018000 0 0x710>; 34*08d73b65SFabien Parent #clock-cells = <1>; 35*08d73b65SFabien Parent }; 36*08d73b65SFabien Parent 37*08d73b65SFabien Parent imgsys: syscon@15000000 { 38*08d73b65SFabien Parent compatible = "mediatek,mt8167-imgsys", "syscon"; 39*08d73b65SFabien Parent reg = <0 0x15000000 0 0x1000>; 40*08d73b65SFabien Parent #clock-cells = <1>; 41*08d73b65SFabien Parent }; 42*08d73b65SFabien Parent 43*08d73b65SFabien Parent vdecsys: syscon@16000000 { 44*08d73b65SFabien Parent compatible = "mediatek,mt8167-vdecsys", "syscon"; 45*08d73b65SFabien Parent reg = <0 0x16000000 0 0x1000>; 46*08d73b65SFabien Parent #clock-cells = <1>; 47*08d73b65SFabien Parent }; 48*08d73b65SFabien Parent 49*08d73b65SFabien Parent pio: pinctrl@1000b000 { 50*08d73b65SFabien Parent compatible = "mediatek,mt8167-pinctrl"; 51*08d73b65SFabien Parent reg = <0 0x1000b000 0 0x1000>; 52*08d73b65SFabien Parent mediatek,pctl-regmap = <&syscfg_pctl>; 53*08d73b65SFabien Parent pins-are-numbered; 54*08d73b65SFabien Parent gpio-controller; 55*08d73b65SFabien Parent #gpio-cells = <2>; 56*08d73b65SFabien Parent interrupt-controller; 57*08d73b65SFabien Parent #interrupt-cells = <2>; 58*08d73b65SFabien Parent interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 59*08d73b65SFabien Parent }; 60*08d73b65SFabien Parent }; 61*08d73b65SFabien Parent}; 62