1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4 5/ { 6 compatible = "mediatek,mt7988a"; 7 interrupt-parent = <&gic>; 8 #address-cells = <2>; 9 #size-cells = <2>; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 compatible = "arm,cortex-a73"; 17 reg = <0x0>; 18 device_type = "cpu"; 19 enable-method = "psci"; 20 }; 21 22 cpu@1 { 23 compatible = "arm,cortex-a73"; 24 reg = <0x1>; 25 device_type = "cpu"; 26 enable-method = "psci"; 27 }; 28 29 cpu@2 { 30 compatible = "arm,cortex-a73"; 31 reg = <0x2>; 32 device_type = "cpu"; 33 enable-method = "psci"; 34 }; 35 36 cpu@3 { 37 compatible = "arm,cortex-a73"; 38 reg = <0x3>; 39 device_type = "cpu"; 40 enable-method = "psci"; 41 }; 42 }; 43 44 oscillator-40m { 45 compatible = "fixed-clock"; 46 clock-frequency = <40000000>; 47 #clock-cells = <0>; 48 clock-output-names = "clkxtal"; 49 }; 50 51 pmu { 52 compatible = "arm,cortex-a73-pmu"; 53 interrupt-parent = <&gic>; 54 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 55 }; 56 57 psci { 58 compatible = "arm,psci-0.2"; 59 method = "smc"; 60 }; 61 62 soc { 63 compatible = "simple-bus"; 64 ranges; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 68 gic: interrupt-controller@c000000 { 69 compatible = "arm,gic-v3"; 70 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 71 <0 0x0c080000 0 0x200000>, /* GICR */ 72 <0 0x0c400000 0 0x2000>, /* GICC */ 73 <0 0x0c410000 0 0x1000>, /* GICH */ 74 <0 0x0c420000 0 0x2000>; /* GICV */ 75 interrupt-parent = <&gic>; 76 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-controller; 78 #interrupt-cells = <3>; 79 }; 80 81 clock-controller@10001000 { 82 compatible = "mediatek,mt7988-infracfg", "syscon"; 83 reg = <0 0x10001000 0 0x1000>; 84 #clock-cells = <1>; 85 }; 86 87 clock-controller@1001b000 { 88 compatible = "mediatek,mt7988-topckgen", "syscon"; 89 reg = <0 0x1001b000 0 0x1000>; 90 #clock-cells = <1>; 91 }; 92 93 watchdog: watchdog@1001c000 { 94 compatible = "mediatek,mt7988-wdt"; 95 reg = <0 0x1001c000 0 0x1000>; 96 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 97 #reset-cells = <1>; 98 }; 99 100 clock-controller@1001e000 { 101 compatible = "mediatek,mt7988-apmixedsys"; 102 reg = <0 0x1001e000 0 0x1000>; 103 #clock-cells = <1>; 104 }; 105 106 clock-controller@11f40000 { 107 compatible = "mediatek,mt7988-xfi-pll"; 108 reg = <0 0x11f40000 0 0x1000>; 109 resets = <&watchdog 16>; 110 #clock-cells = <1>; 111 }; 112 113 clock-controller@15000000 { 114 compatible = "mediatek,mt7988-ethsys", "syscon"; 115 reg = <0 0x15000000 0 0x1000>; 116 #clock-cells = <1>; 117 #reset-cells = <1>; 118 }; 119 120 clock-controller@15031000 { 121 compatible = "mediatek,mt7988-ethwarp"; 122 reg = <0 0x15031000 0 0x1000>; 123 #clock-cells = <1>; 124 #reset-cells = <1>; 125 }; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupt-parent = <&gic>; 131 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 132 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 133 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 134 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 135 }; 136}; 137