1f40c0f80SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2f40c0f80SSam Shih/* 3f40c0f80SSam Shih * Copyright (C) 2021 MediaTek Inc. 4f40c0f80SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com> 5f40c0f80SSam Shih */ 6f40c0f80SSam Shih 7f40c0f80SSam Shih/dts-v1/; 8f40c0f80SSam Shih#include "mt7986b.dtsi" 9f40c0f80SSam Shih 10f40c0f80SSam Shih/ { 11f40c0f80SSam Shih model = "MediaTek MT7986b RFB"; 12f40c0f80SSam Shih compatible = "mediatek,mt7986b-rfb"; 13f40c0f80SSam Shih 14f40c0f80SSam Shih aliases { 15f40c0f80SSam Shih serial0 = &uart0; 16f40c0f80SSam Shih }; 17f40c0f80SSam Shih 18f40c0f80SSam Shih chosen { 19f40c0f80SSam Shih stdout-path = "serial0:115200n8"; 20f40c0f80SSam Shih }; 21f40c0f80SSam Shih 22809967d7SSam Shih memory@40000000 { 23809967d7SSam Shih device_type = "memory"; 24f40c0f80SSam Shih reg = <0 0x40000000 0 0x40000000>; 25f40c0f80SSam Shih }; 26f40c0f80SSam Shih}; 27f40c0f80SSam Shih 28f40c0f80SSam Shih&uart0 { 29f40c0f80SSam Shih status = "okay"; 30f40c0f80SSam Shih}; 31082ff36bSLorenzo Bianconi 32082ff36bSLorenzo Bianconið { 33082ff36bSLorenzo Bianconi status = "okay"; 34082ff36bSLorenzo Bianconi 35082ff36bSLorenzo Bianconi gmac0: mac@0 { 36082ff36bSLorenzo Bianconi compatible = "mediatek,eth-mac"; 37082ff36bSLorenzo Bianconi reg = <0>; 38082ff36bSLorenzo Bianconi phy-mode = "2500base-x"; 39082ff36bSLorenzo Bianconi 40082ff36bSLorenzo Bianconi fixed-link { 41082ff36bSLorenzo Bianconi speed = <2500>; 42082ff36bSLorenzo Bianconi full-duplex; 43082ff36bSLorenzo Bianconi pause; 44082ff36bSLorenzo Bianconi }; 45082ff36bSLorenzo Bianconi }; 46082ff36bSLorenzo Bianconi 47082ff36bSLorenzo Bianconi mdio: mdio-bus { 48082ff36bSLorenzo Bianconi #address-cells = <1>; 49082ff36bSLorenzo Bianconi #size-cells = <0>; 50082ff36bSLorenzo Bianconi 51082ff36bSLorenzo Bianconi switch@0 { 52082ff36bSLorenzo Bianconi compatible = "mediatek,mt7531"; 53082ff36bSLorenzo Bianconi reg = <31>; 54082ff36bSLorenzo Bianconi reset-gpios = <&pio 5 0>; 55082ff36bSLorenzo Bianconi 56082ff36bSLorenzo Bianconi ports { 57082ff36bSLorenzo Bianconi #address-cells = <1>; 58082ff36bSLorenzo Bianconi #size-cells = <0>; 59082ff36bSLorenzo Bianconi 60082ff36bSLorenzo Bianconi port@0 { 61082ff36bSLorenzo Bianconi reg = <0>; 62082ff36bSLorenzo Bianconi label = "lan0"; 63082ff36bSLorenzo Bianconi }; 64082ff36bSLorenzo Bianconi 65082ff36bSLorenzo Bianconi port@1 { 66082ff36bSLorenzo Bianconi reg = <1>; 67082ff36bSLorenzo Bianconi label = "lan1"; 68082ff36bSLorenzo Bianconi }; 69082ff36bSLorenzo Bianconi 70082ff36bSLorenzo Bianconi port@2 { 71082ff36bSLorenzo Bianconi reg = <2>; 72082ff36bSLorenzo Bianconi label = "lan2"; 73082ff36bSLorenzo Bianconi }; 74082ff36bSLorenzo Bianconi 75082ff36bSLorenzo Bianconi port@3 { 76082ff36bSLorenzo Bianconi reg = <3>; 77082ff36bSLorenzo Bianconi label = "lan3"; 78082ff36bSLorenzo Bianconi }; 79082ff36bSLorenzo Bianconi 80082ff36bSLorenzo Bianconi port@4 { 81082ff36bSLorenzo Bianconi reg = <4>; 82082ff36bSLorenzo Bianconi label = "lan4"; 83082ff36bSLorenzo Bianconi }; 84082ff36bSLorenzo Bianconi 85082ff36bSLorenzo Bianconi port@6 { 86082ff36bSLorenzo Bianconi reg = <6>; 87082ff36bSLorenzo Bianconi label = "cpu"; 88082ff36bSLorenzo Bianconi ethernet = <&gmac0>; 89082ff36bSLorenzo Bianconi phy-mode = "2500base-x"; 90082ff36bSLorenzo Bianconi 91082ff36bSLorenzo Bianconi fixed-link { 92082ff36bSLorenzo Bianconi speed = <2500>; 93082ff36bSLorenzo Bianconi full-duplex; 94082ff36bSLorenzo Bianconi pause; 95082ff36bSLorenzo Bianconi }; 96082ff36bSLorenzo Bianconi }; 97082ff36bSLorenzo Bianconi }; 98082ff36bSLorenzo Bianconi }; 99082ff36bSLorenzo Bianconi }; 100082ff36bSLorenzo Bianconi}; 101*300218b0SPeter Chiu 102*300218b0SPeter Chiu&wifi { 103*300218b0SPeter Chiu status = "okay"; 104*300218b0SPeter Chiu pinctrl-names = "default", "dbdc"; 105*300218b0SPeter Chiu pinctrl-0 = <&wf_2g_5g_pins>; 106*300218b0SPeter Chiu pinctrl-1 = <&wf_dbdc_pins>; 107*300218b0SPeter Chiu}; 108*300218b0SPeter Chiu 109*300218b0SPeter Chiu&pio { 110*300218b0SPeter Chiu wf_2g_5g_pins: wf-2g-5g-pins { 111*300218b0SPeter Chiu mux { 112*300218b0SPeter Chiu function = "wifi"; 113*300218b0SPeter Chiu groups = "wf_2g", "wf_5g"; 114*300218b0SPeter Chiu }; 115*300218b0SPeter Chiu conf { 116*300218b0SPeter Chiu pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 117*300218b0SPeter Chiu "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 118*300218b0SPeter Chiu "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 119*300218b0SPeter Chiu "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", 120*300218b0SPeter Chiu "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", 121*300218b0SPeter Chiu "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", 122*300218b0SPeter Chiu "WF1_TOP_CLK", "WF1_TOP_DATA"; 123*300218b0SPeter Chiu drive-strength = <4>; 124*300218b0SPeter Chiu }; 125*300218b0SPeter Chiu }; 126*300218b0SPeter Chiu 127*300218b0SPeter Chiu wf_dbdc_pins: wf-dbdc-pins { 128*300218b0SPeter Chiu mux { 129*300218b0SPeter Chiu function = "wifi"; 130*300218b0SPeter Chiu groups = "wf_dbdc"; 131*300218b0SPeter Chiu }; 132*300218b0SPeter Chiu conf { 133*300218b0SPeter Chiu pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 134*300218b0SPeter Chiu "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 135*300218b0SPeter Chiu "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 136*300218b0SPeter Chiu "WF0_TOP_CLK", "WF0_TOP_DATA"; 137*300218b0SPeter Chiu drive-strength = <4>; 138*300218b0SPeter Chiu }; 139*300218b0SPeter Chiu }; 140*300218b0SPeter Chiu}; 141