xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt7986b-rfb.dts (revision 082ff36bd5c010f77227d881a199c7548f0a6aaf)
1f40c0f80SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2f40c0f80SSam Shih/*
3f40c0f80SSam Shih * Copyright (C) 2021 MediaTek Inc.
4f40c0f80SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com>
5f40c0f80SSam Shih */
6f40c0f80SSam Shih
7f40c0f80SSam Shih/dts-v1/;
8f40c0f80SSam Shih#include "mt7986b.dtsi"
9f40c0f80SSam Shih
10f40c0f80SSam Shih/ {
11f40c0f80SSam Shih	model = "MediaTek MT7986b RFB";
12f40c0f80SSam Shih	compatible = "mediatek,mt7986b-rfb";
13f40c0f80SSam Shih
14f40c0f80SSam Shih	aliases {
15f40c0f80SSam Shih		serial0 = &uart0;
16f40c0f80SSam Shih	};
17f40c0f80SSam Shih
18f40c0f80SSam Shih	chosen {
19f40c0f80SSam Shih		stdout-path = "serial0:115200n8";
20f40c0f80SSam Shih	};
21f40c0f80SSam Shih
22809967d7SSam Shih	memory@40000000 {
23809967d7SSam Shih		device_type = "memory";
24f40c0f80SSam Shih		reg = <0 0x40000000 0 0x40000000>;
25f40c0f80SSam Shih	};
26f40c0f80SSam Shih};
27f40c0f80SSam Shih
28f40c0f80SSam Shih&uart0 {
29f40c0f80SSam Shih	status = "okay";
30f40c0f80SSam Shih};
31*082ff36bSLorenzo Bianconi
32*082ff36bSLorenzo Bianconi&eth {
33*082ff36bSLorenzo Bianconi	status = "okay";
34*082ff36bSLorenzo Bianconi
35*082ff36bSLorenzo Bianconi	gmac0: mac@0 {
36*082ff36bSLorenzo Bianconi		compatible = "mediatek,eth-mac";
37*082ff36bSLorenzo Bianconi		reg = <0>;
38*082ff36bSLorenzo Bianconi		phy-mode = "2500base-x";
39*082ff36bSLorenzo Bianconi
40*082ff36bSLorenzo Bianconi		fixed-link {
41*082ff36bSLorenzo Bianconi			speed = <2500>;
42*082ff36bSLorenzo Bianconi			full-duplex;
43*082ff36bSLorenzo Bianconi			pause;
44*082ff36bSLorenzo Bianconi		};
45*082ff36bSLorenzo Bianconi	};
46*082ff36bSLorenzo Bianconi
47*082ff36bSLorenzo Bianconi	mdio: mdio-bus {
48*082ff36bSLorenzo Bianconi		#address-cells = <1>;
49*082ff36bSLorenzo Bianconi		#size-cells = <0>;
50*082ff36bSLorenzo Bianconi
51*082ff36bSLorenzo Bianconi		switch@0 {
52*082ff36bSLorenzo Bianconi			compatible = "mediatek,mt7531";
53*082ff36bSLorenzo Bianconi			reg = <31>;
54*082ff36bSLorenzo Bianconi			reset-gpios = <&pio 5 0>;
55*082ff36bSLorenzo Bianconi
56*082ff36bSLorenzo Bianconi			ports {
57*082ff36bSLorenzo Bianconi				#address-cells = <1>;
58*082ff36bSLorenzo Bianconi				#size-cells = <0>;
59*082ff36bSLorenzo Bianconi
60*082ff36bSLorenzo Bianconi				port@0 {
61*082ff36bSLorenzo Bianconi					reg = <0>;
62*082ff36bSLorenzo Bianconi					label = "lan0";
63*082ff36bSLorenzo Bianconi				};
64*082ff36bSLorenzo Bianconi
65*082ff36bSLorenzo Bianconi				port@1 {
66*082ff36bSLorenzo Bianconi					reg = <1>;
67*082ff36bSLorenzo Bianconi					label = "lan1";
68*082ff36bSLorenzo Bianconi				};
69*082ff36bSLorenzo Bianconi
70*082ff36bSLorenzo Bianconi				port@2 {
71*082ff36bSLorenzo Bianconi					reg = <2>;
72*082ff36bSLorenzo Bianconi					label = "lan2";
73*082ff36bSLorenzo Bianconi				};
74*082ff36bSLorenzo Bianconi
75*082ff36bSLorenzo Bianconi				port@3 {
76*082ff36bSLorenzo Bianconi					reg = <3>;
77*082ff36bSLorenzo Bianconi					label = "lan3";
78*082ff36bSLorenzo Bianconi				};
79*082ff36bSLorenzo Bianconi
80*082ff36bSLorenzo Bianconi				port@4 {
81*082ff36bSLorenzo Bianconi					reg = <4>;
82*082ff36bSLorenzo Bianconi					label = "lan4";
83*082ff36bSLorenzo Bianconi				};
84*082ff36bSLorenzo Bianconi
85*082ff36bSLorenzo Bianconi				port@6 {
86*082ff36bSLorenzo Bianconi					reg = <6>;
87*082ff36bSLorenzo Bianconi					label = "cpu";
88*082ff36bSLorenzo Bianconi					ethernet = <&gmac0>;
89*082ff36bSLorenzo Bianconi					phy-mode = "2500base-x";
90*082ff36bSLorenzo Bianconi
91*082ff36bSLorenzo Bianconi					fixed-link {
92*082ff36bSLorenzo Bianconi						speed = <2500>;
93*082ff36bSLorenzo Bianconi						full-duplex;
94*082ff36bSLorenzo Bianconi						pause;
95*082ff36bSLorenzo Bianconi					};
96*082ff36bSLorenzo Bianconi				};
97*082ff36bSLorenzo Bianconi			};
98*082ff36bSLorenzo Bianconi		};
99*082ff36bSLorenzo Bianconi	};
100*082ff36bSLorenzo Bianconi};
101