xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt7986a-rfb.dts (revision fbaac5b1057de34d3776df9fc904b7c7e634d945)
150137c15SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT)
250137c15SSam Shih/*
350137c15SSam Shih * Copyright (C) 2021 MediaTek Inc.
450137c15SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com>
550137c15SSam Shih */
650137c15SSam Shih
750137c15SSam Shih/dts-v1/;
850137c15SSam Shih#include "mt7986a.dtsi"
950137c15SSam Shih
1050137c15SSam Shih/ {
1150137c15SSam Shih	model = "MediaTek MT7986a RFB";
1250137c15SSam Shih	compatible = "mediatek,mt7986a-rfb";
1350137c15SSam Shih
1450137c15SSam Shih	aliases {
1550137c15SSam Shih		serial0 = &uart0;
1650137c15SSam Shih	};
1750137c15SSam Shih
1850137c15SSam Shih	chosen {
1950137c15SSam Shih		stdout-path = "serial0:115200n8";
2050137c15SSam Shih	};
2150137c15SSam Shih
22*fbaac5b1SSam Shih	memory@40000000 {
23*fbaac5b1SSam Shih		device_type = "memory";
2450137c15SSam Shih		reg = <0 0x40000000 0 0x40000000>;
2550137c15SSam Shih	};
2650137c15SSam Shih};
2750137c15SSam Shih
2850137c15SSam Shih&uart0 {
2950137c15SSam Shih	status = "okay";
3050137c15SSam Shih};
3150137c15SSam Shih
3250137c15SSam Shih&uart1 {
33c3a064a3SSam Shih	pinctrl-names = "default";
34c3a064a3SSam Shih	pinctrl-0 = <&uart1_pins>;
3550137c15SSam Shih	status = "okay";
3650137c15SSam Shih};
3750137c15SSam Shih
3850137c15SSam Shih&uart2 {
39c3a064a3SSam Shih	pinctrl-names = "default";
40c3a064a3SSam Shih	pinctrl-0 = <&uart2_pins>;
4150137c15SSam Shih	status = "okay";
4250137c15SSam Shih};
43c3a064a3SSam Shih
44c3a064a3SSam Shih&pio {
45c3a064a3SSam Shih	uart1_pins: uart1-pins {
46c3a064a3SSam Shih		mux {
47c3a064a3SSam Shih			function = "uart";
48c3a064a3SSam Shih			groups = "uart1";
49c3a064a3SSam Shih		};
50c3a064a3SSam Shih	};
51c3a064a3SSam Shih
52c3a064a3SSam Shih	uart2_pins: uart2-pins {
53c3a064a3SSam Shih		mux {
54c3a064a3SSam Shih			function = "uart";
55c3a064a3SSam Shih			groups = "uart2";
56c3a064a3SSam Shih		};
57c3a064a3SSam Shih	};
58c3a064a3SSam Shih};
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