150137c15SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT) 250137c15SSam Shih/* 350137c15SSam Shih * Copyright (C) 2021 MediaTek Inc. 450137c15SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com> 550137c15SSam Shih */ 650137c15SSam Shih 750137c15SSam Shih/dts-v1/; 850137c15SSam Shih#include "mt7986a.dtsi" 950137c15SSam Shih 1050137c15SSam Shih/ { 1150137c15SSam Shih model = "MediaTek MT7986a RFB"; 1250137c15SSam Shih compatible = "mediatek,mt7986a-rfb"; 1350137c15SSam Shih 1450137c15SSam Shih aliases { 1550137c15SSam Shih serial0 = &uart0; 1650137c15SSam Shih }; 1750137c15SSam Shih 1850137c15SSam Shih chosen { 1950137c15SSam Shih stdout-path = "serial0:115200n8"; 2050137c15SSam Shih }; 2150137c15SSam Shih 2250137c15SSam Shih memory { 2350137c15SSam Shih reg = <0 0x40000000 0 0x40000000>; 2450137c15SSam Shih }; 2550137c15SSam Shih}; 2650137c15SSam Shih 2750137c15SSam Shih&uart0 { 2850137c15SSam Shih status = "okay"; 2950137c15SSam Shih}; 3050137c15SSam Shih 3150137c15SSam Shih&uart1 { 32*c3a064a3SSam Shih pinctrl-names = "default"; 33*c3a064a3SSam Shih pinctrl-0 = <&uart1_pins>; 3450137c15SSam Shih status = "okay"; 3550137c15SSam Shih}; 3650137c15SSam Shih 3750137c15SSam Shih&uart2 { 38*c3a064a3SSam Shih pinctrl-names = "default"; 39*c3a064a3SSam Shih pinctrl-0 = <&uart2_pins>; 4050137c15SSam Shih status = "okay"; 4150137c15SSam Shih}; 42*c3a064a3SSam Shih 43*c3a064a3SSam Shih&pio { 44*c3a064a3SSam Shih uart1_pins: uart1-pins { 45*c3a064a3SSam Shih mux { 46*c3a064a3SSam Shih function = "uart"; 47*c3a064a3SSam Shih groups = "uart1"; 48*c3a064a3SSam Shih }; 49*c3a064a3SSam Shih }; 50*c3a064a3SSam Shih 51*c3a064a3SSam Shih uart2_pins: uart2-pins { 52*c3a064a3SSam Shih mux { 53*c3a064a3SSam Shih function = "uart"; 54*c3a064a3SSam Shih groups = "uart2"; 55*c3a064a3SSam Shih }; 56*c3a064a3SSam Shih }; 57*c3a064a3SSam Shih}; 58