xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt7986a-rfb.dts (revision 965f2c0491ebbb6995233c0b167fb9e0cf0853da)
150137c15SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT)
250137c15SSam Shih/*
350137c15SSam Shih * Copyright (C) 2021 MediaTek Inc.
450137c15SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com>
550137c15SSam Shih */
650137c15SSam Shih
750137c15SSam Shih/dts-v1/;
850137c15SSam Shih#include "mt7986a.dtsi"
950137c15SSam Shih
1050137c15SSam Shih/ {
1150137c15SSam Shih	model = "MediaTek MT7986a RFB";
1250137c15SSam Shih	compatible = "mediatek,mt7986a-rfb";
1350137c15SSam Shih
1450137c15SSam Shih	aliases {
1550137c15SSam Shih		serial0 = &uart0;
1650137c15SSam Shih	};
1750137c15SSam Shih
1850137c15SSam Shih	chosen {
1950137c15SSam Shih		stdout-path = "serial0:115200n8";
2050137c15SSam Shih	};
2150137c15SSam Shih
22fbaac5b1SSam Shih	memory@40000000 {
23fbaac5b1SSam Shih		device_type = "memory";
2450137c15SSam Shih		reg = <0 0x40000000 0 0x40000000>;
2550137c15SSam Shih	};
2650137c15SSam Shih};
2750137c15SSam Shih
28082ff36bSLorenzo Bianconi&eth {
29082ff36bSLorenzo Bianconi	status = "okay";
30082ff36bSLorenzo Bianconi
31082ff36bSLorenzo Bianconi	gmac0: mac@0 {
32082ff36bSLorenzo Bianconi		compatible = "mediatek,eth-mac";
33082ff36bSLorenzo Bianconi		reg = <0>;
34082ff36bSLorenzo Bianconi		phy-mode = "2500base-x";
35082ff36bSLorenzo Bianconi
36082ff36bSLorenzo Bianconi		fixed-link {
37082ff36bSLorenzo Bianconi			speed = <2500>;
38082ff36bSLorenzo Bianconi			full-duplex;
39082ff36bSLorenzo Bianconi			pause;
40082ff36bSLorenzo Bianconi		};
41082ff36bSLorenzo Bianconi	};
42082ff36bSLorenzo Bianconi
43082ff36bSLorenzo Bianconi	mdio: mdio-bus {
44082ff36bSLorenzo Bianconi		#address-cells = <1>;
45082ff36bSLorenzo Bianconi		#size-cells = <0>;
46082ff36bSLorenzo Bianconi	};
47082ff36bSLorenzo Bianconi};
48082ff36bSLorenzo Bianconi
49082ff36bSLorenzo Bianconi&mdio {
50082ff36bSLorenzo Bianconi	switch: switch@0 {
51082ff36bSLorenzo Bianconi		compatible = "mediatek,mt7531";
52082ff36bSLorenzo Bianconi		reg = <31>;
53082ff36bSLorenzo Bianconi		reset-gpios = <&pio 5 0>;
54082ff36bSLorenzo Bianconi	};
55082ff36bSLorenzo Bianconi};
56082ff36bSLorenzo Bianconi
57*965f2c04SSam Shih&pio {
58*965f2c04SSam Shih	uart1_pins: uart1-pins {
59*965f2c04SSam Shih		mux {
60*965f2c04SSam Shih			function = "uart";
61*965f2c04SSam Shih			groups = "uart1";
62*965f2c04SSam Shih		};
63*965f2c04SSam Shih	};
64*965f2c04SSam Shih
65*965f2c04SSam Shih	uart2_pins: uart2-pins {
66*965f2c04SSam Shih		mux {
67*965f2c04SSam Shih			function = "uart";
68*965f2c04SSam Shih			groups = "uart2";
69*965f2c04SSam Shih		};
70*965f2c04SSam Shih	};
71*965f2c04SSam Shih
72*965f2c04SSam Shih	wf_2g_5g_pins: wf-2g-5g-pins {
73*965f2c04SSam Shih		mux {
74*965f2c04SSam Shih			function = "wifi";
75*965f2c04SSam Shih			groups = "wf_2g", "wf_5g";
76*965f2c04SSam Shih		};
77*965f2c04SSam Shih		conf {
78*965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
79*965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
80*965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
81*965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
82*965f2c04SSam Shih			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
83*965f2c04SSam Shih			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
84*965f2c04SSam Shih			       "WF1_TOP_CLK", "WF1_TOP_DATA";
85*965f2c04SSam Shih			drive-strength = <4>;
86*965f2c04SSam Shih		};
87*965f2c04SSam Shih	};
88*965f2c04SSam Shih
89*965f2c04SSam Shih	wf_dbdc_pins: wf-dbdc-pins {
90*965f2c04SSam Shih		mux {
91*965f2c04SSam Shih			function = "wifi";
92*965f2c04SSam Shih			groups = "wf_dbdc";
93*965f2c04SSam Shih		};
94*965f2c04SSam Shih		conf {
95*965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
96*965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
97*965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
98*965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA";
99*965f2c04SSam Shih			drive-strength = <4>;
100*965f2c04SSam Shih		};
101*965f2c04SSam Shih	};
102*965f2c04SSam Shih};
103*965f2c04SSam Shih
104082ff36bSLorenzo Bianconi&switch {
105082ff36bSLorenzo Bianconi	ports {
106082ff36bSLorenzo Bianconi		#address-cells = <1>;
107082ff36bSLorenzo Bianconi		#size-cells = <0>;
108082ff36bSLorenzo Bianconi
109082ff36bSLorenzo Bianconi		port@0 {
110082ff36bSLorenzo Bianconi			reg = <0>;
111082ff36bSLorenzo Bianconi			label = "lan0";
112082ff36bSLorenzo Bianconi		};
113082ff36bSLorenzo Bianconi
114082ff36bSLorenzo Bianconi		port@1 {
115082ff36bSLorenzo Bianconi			reg = <1>;
116082ff36bSLorenzo Bianconi			label = "lan1";
117082ff36bSLorenzo Bianconi		};
118082ff36bSLorenzo Bianconi
119082ff36bSLorenzo Bianconi		port@2 {
120082ff36bSLorenzo Bianconi			reg = <2>;
121082ff36bSLorenzo Bianconi			label = "lan2";
122082ff36bSLorenzo Bianconi		};
123082ff36bSLorenzo Bianconi
124082ff36bSLorenzo Bianconi		port@3 {
125082ff36bSLorenzo Bianconi			reg = <3>;
126082ff36bSLorenzo Bianconi			label = "lan3";
127082ff36bSLorenzo Bianconi		};
128082ff36bSLorenzo Bianconi
129082ff36bSLorenzo Bianconi		port@4 {
130082ff36bSLorenzo Bianconi			reg = <4>;
131082ff36bSLorenzo Bianconi			label = "lan4";
132082ff36bSLorenzo Bianconi		};
133082ff36bSLorenzo Bianconi
134082ff36bSLorenzo Bianconi		port@6 {
135082ff36bSLorenzo Bianconi			reg = <6>;
136082ff36bSLorenzo Bianconi			label = "cpu";
137082ff36bSLorenzo Bianconi			ethernet = <&gmac0>;
138082ff36bSLorenzo Bianconi			phy-mode = "2500base-x";
139082ff36bSLorenzo Bianconi
140082ff36bSLorenzo Bianconi			fixed-link {
141082ff36bSLorenzo Bianconi				speed = <2500>;
142082ff36bSLorenzo Bianconi				full-duplex;
143082ff36bSLorenzo Bianconi				pause;
144082ff36bSLorenzo Bianconi			};
145082ff36bSLorenzo Bianconi		};
146082ff36bSLorenzo Bianconi	};
147082ff36bSLorenzo Bianconi};
148082ff36bSLorenzo Bianconi
14950137c15SSam Shih&uart0 {
15050137c15SSam Shih	status = "okay";
15150137c15SSam Shih};
15250137c15SSam Shih
15350137c15SSam Shih&uart1 {
154c3a064a3SSam Shih	pinctrl-names = "default";
155c3a064a3SSam Shih	pinctrl-0 = <&uart1_pins>;
15650137c15SSam Shih	status = "okay";
15750137c15SSam Shih};
15850137c15SSam Shih
15950137c15SSam Shih&uart2 {
160c3a064a3SSam Shih	pinctrl-names = "default";
161c3a064a3SSam Shih	pinctrl-0 = <&uart2_pins>;
16250137c15SSam Shih	status = "okay";
16350137c15SSam Shih};
164c3a064a3SSam Shih
165300218b0SPeter Chiu&wifi {
166300218b0SPeter Chiu	status = "okay";
167300218b0SPeter Chiu	pinctrl-names = "default", "dbdc";
168300218b0SPeter Chiu	pinctrl-0 = <&wf_2g_5g_pins>;
169300218b0SPeter Chiu	pinctrl-1 = <&wf_dbdc_pins>;
170300218b0SPeter Chiu};
171