xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt7986a-rfb.dts (revision 918aed7abd2d554f33e51fffefa8172b93a36f56)
150137c15SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT)
250137c15SSam Shih/*
350137c15SSam Shih * Copyright (C) 2021 MediaTek Inc.
450137c15SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com>
550137c15SSam Shih */
650137c15SSam Shih
750137c15SSam Shih/dts-v1/;
8513b49d1SSam Shih#include <dt-bindings/pinctrl/mt65xx.h>
9513b49d1SSam Shih
1050137c15SSam Shih#include "mt7986a.dtsi"
1150137c15SSam Shih
1250137c15SSam Shih/ {
1350137c15SSam Shih	model = "MediaTek MT7986a RFB";
1426589630SMatthias Brugger	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
1550137c15SSam Shih
1650137c15SSam Shih	aliases {
1750137c15SSam Shih		serial0 = &uart0;
1850137c15SSam Shih	};
1950137c15SSam Shih
2050137c15SSam Shih	chosen {
2150137c15SSam Shih		stdout-path = "serial0:115200n8";
2250137c15SSam Shih	};
2350137c15SSam Shih
24fbaac5b1SSam Shih	memory@40000000 {
25fbaac5b1SSam Shih		device_type = "memory";
2650137c15SSam Shih		reg = <0 0x40000000 0 0x40000000>;
2750137c15SSam Shih	};
28513b49d1SSam Shih
29513b49d1SSam Shih	reg_1p8v: regulator-1p8v {
30513b49d1SSam Shih		compatible = "regulator-fixed";
31513b49d1SSam Shih		regulator-name = "fixed-1.8V";
32513b49d1SSam Shih		regulator-min-microvolt = <1800000>;
33513b49d1SSam Shih		regulator-max-microvolt = <1800000>;
34513b49d1SSam Shih		regulator-boot-on;
35513b49d1SSam Shih		regulator-always-on;
36513b49d1SSam Shih	};
37513b49d1SSam Shih
38513b49d1SSam Shih	reg_3p3v: regulator-3p3v {
39513b49d1SSam Shih		compatible = "regulator-fixed";
40513b49d1SSam Shih		regulator-name = "fixed-3.3V";
41513b49d1SSam Shih		regulator-min-microvolt = <3300000>;
42513b49d1SSam Shih		regulator-max-microvolt = <3300000>;
43513b49d1SSam Shih		regulator-boot-on;
44513b49d1SSam Shih		regulator-always-on;
45513b49d1SSam Shih	};
4650137c15SSam Shih};
4750137c15SSam Shih
48ecc5287cSSam Shih&crypto {
49ecc5287cSSam Shih	status = "okay";
50ecc5287cSSam Shih};
51ecc5287cSSam Shih
52082ff36bSLorenzo Bianconi&eth {
53082ff36bSLorenzo Bianconi	status = "okay";
54082ff36bSLorenzo Bianconi
55082ff36bSLorenzo Bianconi	gmac0: mac@0 {
56082ff36bSLorenzo Bianconi		compatible = "mediatek,eth-mac";
57082ff36bSLorenzo Bianconi		reg = <0>;
58082ff36bSLorenzo Bianconi		phy-mode = "2500base-x";
59082ff36bSLorenzo Bianconi
60082ff36bSLorenzo Bianconi		fixed-link {
61082ff36bSLorenzo Bianconi			speed = <2500>;
62082ff36bSLorenzo Bianconi			full-duplex;
63082ff36bSLorenzo Bianconi			pause;
64082ff36bSLorenzo Bianconi		};
65082ff36bSLorenzo Bianconi	};
66082ff36bSLorenzo Bianconi
67082ff36bSLorenzo Bianconi	mdio: mdio-bus {
68082ff36bSLorenzo Bianconi		#address-cells = <1>;
69082ff36bSLorenzo Bianconi		#size-cells = <0>;
70082ff36bSLorenzo Bianconi	};
71082ff36bSLorenzo Bianconi};
72082ff36bSLorenzo Bianconi
73082ff36bSLorenzo Bianconi&mdio {
74082ff36bSLorenzo Bianconi	switch: switch@0 {
75082ff36bSLorenzo Bianconi		compatible = "mediatek,mt7531";
76082ff36bSLorenzo Bianconi		reg = <31>;
77082ff36bSLorenzo Bianconi		reset-gpios = <&pio 5 0>;
78082ff36bSLorenzo Bianconi	};
79082ff36bSLorenzo Bianconi};
80082ff36bSLorenzo Bianconi
81513b49d1SSam Shih&mmc0 {
82513b49d1SSam Shih	pinctrl-names = "default", "state_uhs";
83513b49d1SSam Shih	pinctrl-0 = <&mmc0_pins_default>;
84513b49d1SSam Shih	pinctrl-1 = <&mmc0_pins_uhs>;
85513b49d1SSam Shih	bus-width = <8>;
86513b49d1SSam Shih	max-frequency = <200000000>;
87513b49d1SSam Shih	cap-mmc-highspeed;
88513b49d1SSam Shih	mmc-hs200-1_8v;
89513b49d1SSam Shih	mmc-hs400-1_8v;
90513b49d1SSam Shih	hs400-ds-delay = <0x14014>;
91513b49d1SSam Shih	vmmc-supply = <&reg_3p3v>;
92513b49d1SSam Shih	vqmmc-supply = <&reg_1p8v>;
93513b49d1SSam Shih	non-removable;
94513b49d1SSam Shih	no-sd;
95513b49d1SSam Shih	no-sdio;
96*918aed7aSSam Shih};
97*918aed7aSSam Shih
98*918aed7aSSam Shih&pcie {
99*918aed7aSSam Shih	pinctrl-names = "default";
100*918aed7aSSam Shih	pinctrl-0 = <&pcie_pins>;
101*918aed7aSSam Shih	status = "okay";
102*918aed7aSSam Shih};
103*918aed7aSSam Shih
104*918aed7aSSam Shih&pcie_phy {
105513b49d1SSam Shih	status = "okay";
106513b49d1SSam Shih};
107513b49d1SSam Shih
108965f2c04SSam Shih&pio {
109513b49d1SSam Shih	mmc0_pins_default: mmc0-pins {
110513b49d1SSam Shih		mux {
111513b49d1SSam Shih			function = "emmc";
112513b49d1SSam Shih			groups = "emmc_51";
113513b49d1SSam Shih		};
114513b49d1SSam Shih		conf-cmd-dat {
115513b49d1SSam Shih			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
116513b49d1SSam Shih			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
117513b49d1SSam Shih			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
118513b49d1SSam Shih			input-enable;
119513b49d1SSam Shih			drive-strength = <4>;
120513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
121513b49d1SSam Shih		};
122513b49d1SSam Shih		conf-clk {
123513b49d1SSam Shih			pins = "EMMC_CK";
124513b49d1SSam Shih			drive-strength = <6>;
125513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
126513b49d1SSam Shih		};
127513b49d1SSam Shih		conf-ds {
128513b49d1SSam Shih			pins = "EMMC_DSL";
129513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
130513b49d1SSam Shih		};
131513b49d1SSam Shih		conf-rst {
132513b49d1SSam Shih			pins = "EMMC_RSTB";
133513b49d1SSam Shih			drive-strength = <4>;
134513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
135513b49d1SSam Shih		};
136513b49d1SSam Shih	};
137513b49d1SSam Shih
138513b49d1SSam Shih	mmc0_pins_uhs: mmc0-uhs-pins {
139513b49d1SSam Shih		mux {
140513b49d1SSam Shih			function = "emmc";
141513b49d1SSam Shih			groups = "emmc_51";
142513b49d1SSam Shih		};
143513b49d1SSam Shih		conf-cmd-dat {
144513b49d1SSam Shih			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
145513b49d1SSam Shih			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
146513b49d1SSam Shih			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
147513b49d1SSam Shih			input-enable;
148513b49d1SSam Shih			drive-strength = <4>;
149513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
150513b49d1SSam Shih		};
151513b49d1SSam Shih		conf-clk {
152513b49d1SSam Shih			pins = "EMMC_CK";
153513b49d1SSam Shih			drive-strength = <6>;
154513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
155513b49d1SSam Shih		};
156513b49d1SSam Shih		conf-ds {
157513b49d1SSam Shih			pins = "EMMC_DSL";
158513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
159513b49d1SSam Shih		};
160513b49d1SSam Shih		conf-rst {
161513b49d1SSam Shih			pins = "EMMC_RSTB";
162513b49d1SSam Shih			drive-strength = <4>;
163513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
164513b49d1SSam Shih		};
165513b49d1SSam Shih	};
166513b49d1SSam Shih
167*918aed7aSSam Shih	pcie_pins: pcie-pins {
168*918aed7aSSam Shih		mux {
169*918aed7aSSam Shih			function = "pcie";
170*918aed7aSSam Shih			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
171*918aed7aSSam Shih		};
172*918aed7aSSam Shih	};
173*918aed7aSSam Shih
174885e153eSSam Shih	spi_flash_pins: spi-flash-pins {
175885e153eSSam Shih		mux {
176885e153eSSam Shih			function = "spi";
177885e153eSSam Shih			groups = "spi0", "spi0_wp_hold";
178885e153eSSam Shih		};
179885e153eSSam Shih	};
180885e153eSSam Shih
181885e153eSSam Shih	spic_pins: spic-pins {
182885e153eSSam Shih		mux {
183885e153eSSam Shih			function = "spi";
184885e153eSSam Shih			groups = "spi1_2";
185885e153eSSam Shih		};
186885e153eSSam Shih	};
187885e153eSSam Shih
188965f2c04SSam Shih	uart1_pins: uart1-pins {
189965f2c04SSam Shih		mux {
190965f2c04SSam Shih			function = "uart";
191965f2c04SSam Shih			groups = "uart1";
192965f2c04SSam Shih		};
193965f2c04SSam Shih	};
194965f2c04SSam Shih
195965f2c04SSam Shih	uart2_pins: uart2-pins {
196965f2c04SSam Shih		mux {
197965f2c04SSam Shih			function = "uart";
198965f2c04SSam Shih			groups = "uart2";
199965f2c04SSam Shih		};
200965f2c04SSam Shih	};
201965f2c04SSam Shih
202965f2c04SSam Shih	wf_2g_5g_pins: wf-2g-5g-pins {
203965f2c04SSam Shih		mux {
204965f2c04SSam Shih			function = "wifi";
205965f2c04SSam Shih			groups = "wf_2g", "wf_5g";
206965f2c04SSam Shih		};
207965f2c04SSam Shih		conf {
208965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
209965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
210965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
211965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
212965f2c04SSam Shih			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
213965f2c04SSam Shih			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
214965f2c04SSam Shih			       "WF1_TOP_CLK", "WF1_TOP_DATA";
215965f2c04SSam Shih			drive-strength = <4>;
216965f2c04SSam Shih		};
217965f2c04SSam Shih	};
218965f2c04SSam Shih
219965f2c04SSam Shih	wf_dbdc_pins: wf-dbdc-pins {
220965f2c04SSam Shih		mux {
221965f2c04SSam Shih			function = "wifi";
222965f2c04SSam Shih			groups = "wf_dbdc";
223965f2c04SSam Shih		};
224965f2c04SSam Shih		conf {
225965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
226965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
227965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
228965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA";
229965f2c04SSam Shih			drive-strength = <4>;
230965f2c04SSam Shih		};
231965f2c04SSam Shih	};
232965f2c04SSam Shih};
233965f2c04SSam Shih
234885e153eSSam Shih&spi0 {
235885e153eSSam Shih	pinctrl-names = "default";
236885e153eSSam Shih	pinctrl-0 = <&spi_flash_pins>;
237885e153eSSam Shih	cs-gpios = <0>, <0>;
238885e153eSSam Shih	status = "okay";
239885e153eSSam Shih	spi_nand: spi_nand@0 {
240885e153eSSam Shih		compatible = "spi-nand";
241885e153eSSam Shih		reg = <0>;
242885e153eSSam Shih		spi-max-frequency = <10000000>;
243885e153eSSam Shih		spi-tx-buswidth = <4>;
244885e153eSSam Shih		spi-rx-buswidth = <4>;
245885e153eSSam Shih	};
246885e153eSSam Shih};
247885e153eSSam Shih
248885e153eSSam Shih&spi1 {
249885e153eSSam Shih	pinctrl-names = "default";
250885e153eSSam Shih	pinctrl-0 = <&spic_pins>;
251885e153eSSam Shih	cs-gpios = <0>, <0>;
252885e153eSSam Shih	status = "okay";
253885e153eSSam Shih};
254885e153eSSam Shih
255e21cbfc3SSam Shih&ssusb {
256e21cbfc3SSam Shih	status = "okay";
257e21cbfc3SSam Shih};
258e21cbfc3SSam Shih
259082ff36bSLorenzo Bianconi&switch {
260082ff36bSLorenzo Bianconi	ports {
261082ff36bSLorenzo Bianconi		#address-cells = <1>;
262082ff36bSLorenzo Bianconi		#size-cells = <0>;
263082ff36bSLorenzo Bianconi
264082ff36bSLorenzo Bianconi		port@0 {
265082ff36bSLorenzo Bianconi			reg = <0>;
266082ff36bSLorenzo Bianconi			label = "lan0";
267082ff36bSLorenzo Bianconi		};
268082ff36bSLorenzo Bianconi
269082ff36bSLorenzo Bianconi		port@1 {
270082ff36bSLorenzo Bianconi			reg = <1>;
271082ff36bSLorenzo Bianconi			label = "lan1";
272082ff36bSLorenzo Bianconi		};
273082ff36bSLorenzo Bianconi
274082ff36bSLorenzo Bianconi		port@2 {
275082ff36bSLorenzo Bianconi			reg = <2>;
276082ff36bSLorenzo Bianconi			label = "lan2";
277082ff36bSLorenzo Bianconi		};
278082ff36bSLorenzo Bianconi
279082ff36bSLorenzo Bianconi		port@3 {
280082ff36bSLorenzo Bianconi			reg = <3>;
281082ff36bSLorenzo Bianconi			label = "lan3";
282082ff36bSLorenzo Bianconi		};
283082ff36bSLorenzo Bianconi
284082ff36bSLorenzo Bianconi		port@4 {
285082ff36bSLorenzo Bianconi			reg = <4>;
286082ff36bSLorenzo Bianconi			label = "lan4";
287082ff36bSLorenzo Bianconi		};
288082ff36bSLorenzo Bianconi
289082ff36bSLorenzo Bianconi		port@6 {
290082ff36bSLorenzo Bianconi			reg = <6>;
291082ff36bSLorenzo Bianconi			label = "cpu";
292082ff36bSLorenzo Bianconi			ethernet = <&gmac0>;
293082ff36bSLorenzo Bianconi			phy-mode = "2500base-x";
294082ff36bSLorenzo Bianconi
295082ff36bSLorenzo Bianconi			fixed-link {
296082ff36bSLorenzo Bianconi				speed = <2500>;
297082ff36bSLorenzo Bianconi				full-duplex;
298082ff36bSLorenzo Bianconi				pause;
299082ff36bSLorenzo Bianconi			};
300082ff36bSLorenzo Bianconi		};
301082ff36bSLorenzo Bianconi	};
302082ff36bSLorenzo Bianconi};
303082ff36bSLorenzo Bianconi
30450137c15SSam Shih&uart0 {
30550137c15SSam Shih	status = "okay";
30650137c15SSam Shih};
30750137c15SSam Shih
30850137c15SSam Shih&uart1 {
309c3a064a3SSam Shih	pinctrl-names = "default";
310c3a064a3SSam Shih	pinctrl-0 = <&uart1_pins>;
31150137c15SSam Shih	status = "okay";
31250137c15SSam Shih};
31350137c15SSam Shih
31450137c15SSam Shih&uart2 {
315c3a064a3SSam Shih	pinctrl-names = "default";
316c3a064a3SSam Shih	pinctrl-0 = <&uart2_pins>;
31750137c15SSam Shih	status = "okay";
31850137c15SSam Shih};
319c3a064a3SSam Shih
320e21cbfc3SSam Shih&usb_phy {
321e21cbfc3SSam Shih	status = "okay";
322e21cbfc3SSam Shih};
323e21cbfc3SSam Shih
324300218b0SPeter Chiu&wifi {
325300218b0SPeter Chiu	status = "okay";
326300218b0SPeter Chiu	pinctrl-names = "default", "dbdc";
327300218b0SPeter Chiu	pinctrl-0 = <&wf_2g_5g_pins>;
328300218b0SPeter Chiu	pinctrl-1 = <&wf_dbdc_pins>;
329300218b0SPeter Chiu};
330