150137c15SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT) 250137c15SSam Shih/* 350137c15SSam Shih * Copyright (C) 2021 MediaTek Inc. 450137c15SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com> 550137c15SSam Shih */ 650137c15SSam Shih 750137c15SSam Shih/dts-v1/; 8513b49d1SSam Shih#include <dt-bindings/pinctrl/mt65xx.h> 9513b49d1SSam Shih 1050137c15SSam Shih#include "mt7986a.dtsi" 1150137c15SSam Shih 1250137c15SSam Shih/ { 1350137c15SSam Shih model = "MediaTek MT7986a RFB"; 14380d18fbSAngeloGioacchino Del Regno chassis-type = "embedded"; 1526589630SMatthias Brugger compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; 1650137c15SSam Shih 1750137c15SSam Shih aliases { 1850137c15SSam Shih serial0 = &uart0; 1950137c15SSam Shih }; 2050137c15SSam Shih 2150137c15SSam Shih chosen { 2250137c15SSam Shih stdout-path = "serial0:115200n8"; 2350137c15SSam Shih }; 2450137c15SSam Shih 25fbaac5b1SSam Shih memory@40000000 { 26fbaac5b1SSam Shih device_type = "memory"; 2750137c15SSam Shih reg = <0 0x40000000 0 0x40000000>; 2850137c15SSam Shih }; 29513b49d1SSam Shih 30513b49d1SSam Shih reg_1p8v: regulator-1p8v { 31513b49d1SSam Shih compatible = "regulator-fixed"; 32513b49d1SSam Shih regulator-name = "fixed-1.8V"; 33513b49d1SSam Shih regulator-min-microvolt = <1800000>; 34513b49d1SSam Shih regulator-max-microvolt = <1800000>; 35513b49d1SSam Shih regulator-boot-on; 36513b49d1SSam Shih regulator-always-on; 37513b49d1SSam Shih }; 38513b49d1SSam Shih 39513b49d1SSam Shih reg_3p3v: regulator-3p3v { 40513b49d1SSam Shih compatible = "regulator-fixed"; 41513b49d1SSam Shih regulator-name = "fixed-3.3V"; 42513b49d1SSam Shih regulator-min-microvolt = <3300000>; 43513b49d1SSam Shih regulator-max-microvolt = <3300000>; 44513b49d1SSam Shih regulator-boot-on; 45513b49d1SSam Shih regulator-always-on; 46513b49d1SSam Shih }; 4750137c15SSam Shih}; 4850137c15SSam Shih 49ecc5287cSSam Shih&crypto { 50ecc5287cSSam Shih status = "okay"; 51ecc5287cSSam Shih}; 52ecc5287cSSam Shih 53082ff36bSLorenzo Bianconið { 54082ff36bSLorenzo Bianconi status = "okay"; 55082ff36bSLorenzo Bianconi 56082ff36bSLorenzo Bianconi gmac0: mac@0 { 57082ff36bSLorenzo Bianconi compatible = "mediatek,eth-mac"; 58082ff36bSLorenzo Bianconi reg = <0>; 59082ff36bSLorenzo Bianconi phy-mode = "2500base-x"; 60082ff36bSLorenzo Bianconi 61082ff36bSLorenzo Bianconi fixed-link { 62082ff36bSLorenzo Bianconi speed = <2500>; 63082ff36bSLorenzo Bianconi full-duplex; 64082ff36bSLorenzo Bianconi pause; 65082ff36bSLorenzo Bianconi }; 66082ff36bSLorenzo Bianconi }; 67082ff36bSLorenzo Bianconi 68*43ec7fc9SArınç ÜNAL gmac1: mac@1 { 69*43ec7fc9SArınç ÜNAL compatible = "mediatek,eth-mac"; 70*43ec7fc9SArınç ÜNAL reg = <1>; 71*43ec7fc9SArınç ÜNAL phy-mode = "rgmii"; 72*43ec7fc9SArınç ÜNAL 73*43ec7fc9SArınç ÜNAL fixed-link { 74*43ec7fc9SArınç ÜNAL speed = <1000>; 75*43ec7fc9SArınç ÜNAL full-duplex; 76*43ec7fc9SArınç ÜNAL pause; 77*43ec7fc9SArınç ÜNAL }; 78*43ec7fc9SArınç ÜNAL }; 79*43ec7fc9SArınç ÜNAL 80082ff36bSLorenzo Bianconi mdio: mdio-bus { 81082ff36bSLorenzo Bianconi #address-cells = <1>; 82082ff36bSLorenzo Bianconi #size-cells = <0>; 83082ff36bSLorenzo Bianconi }; 84082ff36bSLorenzo Bianconi}; 85082ff36bSLorenzo Bianconi 86082ff36bSLorenzo Bianconi&mdio { 87082ff36bSLorenzo Bianconi switch: switch@0 { 88082ff36bSLorenzo Bianconi compatible = "mediatek,mt7531"; 89082ff36bSLorenzo Bianconi reg = <31>; 90082ff36bSLorenzo Bianconi reset-gpios = <&pio 5 0>; 91082ff36bSLorenzo Bianconi }; 92082ff36bSLorenzo Bianconi}; 93082ff36bSLorenzo Bianconi 94513b49d1SSam Shih&mmc0 { 95513b49d1SSam Shih pinctrl-names = "default", "state_uhs"; 96513b49d1SSam Shih pinctrl-0 = <&mmc0_pins_default>; 97513b49d1SSam Shih pinctrl-1 = <&mmc0_pins_uhs>; 98513b49d1SSam Shih bus-width = <8>; 99513b49d1SSam Shih max-frequency = <200000000>; 100513b49d1SSam Shih cap-mmc-highspeed; 101513b49d1SSam Shih mmc-hs200-1_8v; 102513b49d1SSam Shih mmc-hs400-1_8v; 103513b49d1SSam Shih hs400-ds-delay = <0x14014>; 104513b49d1SSam Shih vmmc-supply = <®_3p3v>; 105513b49d1SSam Shih vqmmc-supply = <®_1p8v>; 106513b49d1SSam Shih non-removable; 107513b49d1SSam Shih no-sd; 108513b49d1SSam Shih no-sdio; 109918aed7aSSam Shih}; 110918aed7aSSam Shih 111918aed7aSSam Shih&pcie { 112918aed7aSSam Shih pinctrl-names = "default"; 113918aed7aSSam Shih pinctrl-0 = <&pcie_pins>; 114918aed7aSSam Shih status = "okay"; 115918aed7aSSam Shih}; 116918aed7aSSam Shih 117918aed7aSSam Shih&pcie_phy { 118513b49d1SSam Shih status = "okay"; 119513b49d1SSam Shih}; 120513b49d1SSam Shih 121965f2c04SSam Shih&pio { 122513b49d1SSam Shih mmc0_pins_default: mmc0-pins { 123513b49d1SSam Shih mux { 124513b49d1SSam Shih function = "emmc"; 125513b49d1SSam Shih groups = "emmc_51"; 126513b49d1SSam Shih }; 127513b49d1SSam Shih conf-cmd-dat { 128513b49d1SSam Shih pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", 129513b49d1SSam Shih "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", 130513b49d1SSam Shih "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; 131513b49d1SSam Shih input-enable; 132513b49d1SSam Shih drive-strength = <4>; 133513b49d1SSam Shih bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 134513b49d1SSam Shih }; 135513b49d1SSam Shih conf-clk { 136513b49d1SSam Shih pins = "EMMC_CK"; 137513b49d1SSam Shih drive-strength = <6>; 138513b49d1SSam Shih bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 139513b49d1SSam Shih }; 140513b49d1SSam Shih conf-ds { 141513b49d1SSam Shih pins = "EMMC_DSL"; 142513b49d1SSam Shih bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 143513b49d1SSam Shih }; 144513b49d1SSam Shih conf-rst { 145513b49d1SSam Shih pins = "EMMC_RSTB"; 146513b49d1SSam Shih drive-strength = <4>; 147513b49d1SSam Shih bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 148513b49d1SSam Shih }; 149513b49d1SSam Shih }; 150513b49d1SSam Shih 151513b49d1SSam Shih mmc0_pins_uhs: mmc0-uhs-pins { 152513b49d1SSam Shih mux { 153513b49d1SSam Shih function = "emmc"; 154513b49d1SSam Shih groups = "emmc_51"; 155513b49d1SSam Shih }; 156513b49d1SSam Shih conf-cmd-dat { 157513b49d1SSam Shih pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", 158513b49d1SSam Shih "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", 159513b49d1SSam Shih "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; 160513b49d1SSam Shih input-enable; 161513b49d1SSam Shih drive-strength = <4>; 162513b49d1SSam Shih bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 163513b49d1SSam Shih }; 164513b49d1SSam Shih conf-clk { 165513b49d1SSam Shih pins = "EMMC_CK"; 166513b49d1SSam Shih drive-strength = <6>; 167513b49d1SSam Shih bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 168513b49d1SSam Shih }; 169513b49d1SSam Shih conf-ds { 170513b49d1SSam Shih pins = "EMMC_DSL"; 171513b49d1SSam Shih bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 172513b49d1SSam Shih }; 173513b49d1SSam Shih conf-rst { 174513b49d1SSam Shih pins = "EMMC_RSTB"; 175513b49d1SSam Shih drive-strength = <4>; 176513b49d1SSam Shih bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 177513b49d1SSam Shih }; 178513b49d1SSam Shih }; 179513b49d1SSam Shih 180918aed7aSSam Shih pcie_pins: pcie-pins { 181918aed7aSSam Shih mux { 182918aed7aSSam Shih function = "pcie"; 183918aed7aSSam Shih groups = "pcie_clk", "pcie_wake", "pcie_pereset"; 184918aed7aSSam Shih }; 185918aed7aSSam Shih }; 186918aed7aSSam Shih 187885e153eSSam Shih spi_flash_pins: spi-flash-pins { 188885e153eSSam Shih mux { 189885e153eSSam Shih function = "spi"; 190885e153eSSam Shih groups = "spi0", "spi0_wp_hold"; 191885e153eSSam Shih }; 192885e153eSSam Shih }; 193885e153eSSam Shih 194885e153eSSam Shih spic_pins: spic-pins { 195885e153eSSam Shih mux { 196885e153eSSam Shih function = "spi"; 197885e153eSSam Shih groups = "spi1_2"; 198885e153eSSam Shih }; 199885e153eSSam Shih }; 200885e153eSSam Shih 201965f2c04SSam Shih uart1_pins: uart1-pins { 202965f2c04SSam Shih mux { 203965f2c04SSam Shih function = "uart"; 204965f2c04SSam Shih groups = "uart1"; 205965f2c04SSam Shih }; 206965f2c04SSam Shih }; 207965f2c04SSam Shih 208965f2c04SSam Shih uart2_pins: uart2-pins { 209965f2c04SSam Shih mux { 210965f2c04SSam Shih function = "uart"; 211965f2c04SSam Shih groups = "uart2"; 212965f2c04SSam Shih }; 213965f2c04SSam Shih }; 214965f2c04SSam Shih 215965f2c04SSam Shih wf_2g_5g_pins: wf-2g-5g-pins { 216965f2c04SSam Shih mux { 217965f2c04SSam Shih function = "wifi"; 218965f2c04SSam Shih groups = "wf_2g", "wf_5g"; 219965f2c04SSam Shih }; 220965f2c04SSam Shih conf { 221965f2c04SSam Shih pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 222965f2c04SSam Shih "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 223965f2c04SSam Shih "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 224965f2c04SSam Shih "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", 225965f2c04SSam Shih "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", 226965f2c04SSam Shih "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", 227965f2c04SSam Shih "WF1_TOP_CLK", "WF1_TOP_DATA"; 228965f2c04SSam Shih drive-strength = <4>; 229965f2c04SSam Shih }; 230965f2c04SSam Shih }; 231965f2c04SSam Shih 232965f2c04SSam Shih wf_dbdc_pins: wf-dbdc-pins { 233965f2c04SSam Shih mux { 234965f2c04SSam Shih function = "wifi"; 235965f2c04SSam Shih groups = "wf_dbdc"; 236965f2c04SSam Shih }; 237965f2c04SSam Shih conf { 238965f2c04SSam Shih pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 239965f2c04SSam Shih "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 240965f2c04SSam Shih "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 241965f2c04SSam Shih "WF0_TOP_CLK", "WF0_TOP_DATA"; 242965f2c04SSam Shih drive-strength = <4>; 243965f2c04SSam Shih }; 244965f2c04SSam Shih }; 245965f2c04SSam Shih}; 246965f2c04SSam Shih 247885e153eSSam Shih&spi0 { 248885e153eSSam Shih pinctrl-names = "default"; 249885e153eSSam Shih pinctrl-0 = <&spi_flash_pins>; 250885e153eSSam Shih cs-gpios = <0>, <0>; 251885e153eSSam Shih status = "okay"; 252bbe266c7SRafał Miłecki 253bbe266c7SRafał Miłecki spi_nand: flash@0 { 254885e153eSSam Shih compatible = "spi-nand"; 255885e153eSSam Shih reg = <0>; 256885e153eSSam Shih spi-max-frequency = <10000000>; 2574e7dc18aSRafał Miłecki spi-tx-bus-width = <4>; 2584e7dc18aSRafał Miłecki spi-rx-bus-width = <4>; 259885e153eSSam Shih }; 260885e153eSSam Shih}; 261885e153eSSam Shih 262885e153eSSam Shih&spi1 { 263885e153eSSam Shih pinctrl-names = "default"; 264885e153eSSam Shih pinctrl-0 = <&spic_pins>; 265885e153eSSam Shih cs-gpios = <0>, <0>; 266885e153eSSam Shih status = "okay"; 267885e153eSSam Shih}; 268885e153eSSam Shih 269e21cbfc3SSam Shih&ssusb { 270e21cbfc3SSam Shih status = "okay"; 271e21cbfc3SSam Shih}; 272e21cbfc3SSam Shih 273082ff36bSLorenzo Bianconi&switch { 274082ff36bSLorenzo Bianconi ports { 275082ff36bSLorenzo Bianconi #address-cells = <1>; 276082ff36bSLorenzo Bianconi #size-cells = <0>; 277082ff36bSLorenzo Bianconi 278082ff36bSLorenzo Bianconi port@0 { 279082ff36bSLorenzo Bianconi reg = <0>; 280082ff36bSLorenzo Bianconi label = "lan0"; 281082ff36bSLorenzo Bianconi }; 282082ff36bSLorenzo Bianconi 283082ff36bSLorenzo Bianconi port@1 { 284082ff36bSLorenzo Bianconi reg = <1>; 285082ff36bSLorenzo Bianconi label = "lan1"; 286082ff36bSLorenzo Bianconi }; 287082ff36bSLorenzo Bianconi 288082ff36bSLorenzo Bianconi port@2 { 289082ff36bSLorenzo Bianconi reg = <2>; 290082ff36bSLorenzo Bianconi label = "lan2"; 291082ff36bSLorenzo Bianconi }; 292082ff36bSLorenzo Bianconi 293082ff36bSLorenzo Bianconi port@3 { 294082ff36bSLorenzo Bianconi reg = <3>; 295082ff36bSLorenzo Bianconi label = "lan3"; 296082ff36bSLorenzo Bianconi }; 297082ff36bSLorenzo Bianconi 298082ff36bSLorenzo Bianconi port@4 { 299082ff36bSLorenzo Bianconi reg = <4>; 300082ff36bSLorenzo Bianconi label = "lan4"; 301082ff36bSLorenzo Bianconi }; 302082ff36bSLorenzo Bianconi 303*43ec7fc9SArınç ÜNAL port@5 { 304*43ec7fc9SArınç ÜNAL reg = <5>; 305*43ec7fc9SArınç ÜNAL ethernet = <&gmac1>; 306*43ec7fc9SArınç ÜNAL phy-mode = "rgmii"; 307*43ec7fc9SArınç ÜNAL 308*43ec7fc9SArınç ÜNAL fixed-link { 309*43ec7fc9SArınç ÜNAL speed = <1000>; 310*43ec7fc9SArınç ÜNAL full-duplex; 311*43ec7fc9SArınç ÜNAL pause; 312*43ec7fc9SArınç ÜNAL }; 313*43ec7fc9SArınç ÜNAL }; 314*43ec7fc9SArınç ÜNAL 315082ff36bSLorenzo Bianconi port@6 { 316082ff36bSLorenzo Bianconi reg = <6>; 317082ff36bSLorenzo Bianconi label = "cpu"; 318082ff36bSLorenzo Bianconi ethernet = <&gmac0>; 319082ff36bSLorenzo Bianconi phy-mode = "2500base-x"; 320082ff36bSLorenzo Bianconi 321082ff36bSLorenzo Bianconi fixed-link { 322082ff36bSLorenzo Bianconi speed = <2500>; 323082ff36bSLorenzo Bianconi full-duplex; 324082ff36bSLorenzo Bianconi pause; 325082ff36bSLorenzo Bianconi }; 326082ff36bSLorenzo Bianconi }; 327082ff36bSLorenzo Bianconi }; 328082ff36bSLorenzo Bianconi}; 329082ff36bSLorenzo Bianconi 33050137c15SSam Shih&uart0 { 33150137c15SSam Shih status = "okay"; 33250137c15SSam Shih}; 33350137c15SSam Shih 33450137c15SSam Shih&uart1 { 335c3a064a3SSam Shih pinctrl-names = "default"; 336c3a064a3SSam Shih pinctrl-0 = <&uart1_pins>; 33750137c15SSam Shih status = "okay"; 33850137c15SSam Shih}; 33950137c15SSam Shih 34050137c15SSam Shih&uart2 { 341c3a064a3SSam Shih pinctrl-names = "default"; 342c3a064a3SSam Shih pinctrl-0 = <&uart2_pins>; 34350137c15SSam Shih status = "okay"; 34450137c15SSam Shih}; 345c3a064a3SSam Shih 346e21cbfc3SSam Shih&usb_phy { 347e21cbfc3SSam Shih status = "okay"; 348e21cbfc3SSam Shih}; 349e21cbfc3SSam Shih 350300218b0SPeter Chiu&wifi { 351300218b0SPeter Chiu status = "okay"; 352300218b0SPeter Chiu pinctrl-names = "default", "dbdc"; 353300218b0SPeter Chiu pinctrl-0 = <&wf_2g_5g_pins>; 354300218b0SPeter Chiu pinctrl-1 = <&wf_dbdc_pins>; 355300218b0SPeter Chiu}; 356