xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt7986a-rfb.dts (revision 380d18fb2758058bf4bf037aebfafcf7b7ecbca5)
150137c15SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT)
250137c15SSam Shih/*
350137c15SSam Shih * Copyright (C) 2021 MediaTek Inc.
450137c15SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com>
550137c15SSam Shih */
650137c15SSam Shih
750137c15SSam Shih/dts-v1/;
8513b49d1SSam Shih#include <dt-bindings/pinctrl/mt65xx.h>
9513b49d1SSam Shih
1050137c15SSam Shih#include "mt7986a.dtsi"
1150137c15SSam Shih
1250137c15SSam Shih/ {
1350137c15SSam Shih	model = "MediaTek MT7986a RFB";
14*380d18fbSAngeloGioacchino Del Regno	chassis-type = "embedded";
1526589630SMatthias Brugger	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
1650137c15SSam Shih
1750137c15SSam Shih	aliases {
1850137c15SSam Shih		serial0 = &uart0;
1950137c15SSam Shih	};
2050137c15SSam Shih
2150137c15SSam Shih	chosen {
2250137c15SSam Shih		stdout-path = "serial0:115200n8";
2350137c15SSam Shih	};
2450137c15SSam Shih
25fbaac5b1SSam Shih	memory@40000000 {
26fbaac5b1SSam Shih		device_type = "memory";
2750137c15SSam Shih		reg = <0 0x40000000 0 0x40000000>;
2850137c15SSam Shih	};
29513b49d1SSam Shih
30513b49d1SSam Shih	reg_1p8v: regulator-1p8v {
31513b49d1SSam Shih		compatible = "regulator-fixed";
32513b49d1SSam Shih		regulator-name = "fixed-1.8V";
33513b49d1SSam Shih		regulator-min-microvolt = <1800000>;
34513b49d1SSam Shih		regulator-max-microvolt = <1800000>;
35513b49d1SSam Shih		regulator-boot-on;
36513b49d1SSam Shih		regulator-always-on;
37513b49d1SSam Shih	};
38513b49d1SSam Shih
39513b49d1SSam Shih	reg_3p3v: regulator-3p3v {
40513b49d1SSam Shih		compatible = "regulator-fixed";
41513b49d1SSam Shih		regulator-name = "fixed-3.3V";
42513b49d1SSam Shih		regulator-min-microvolt = <3300000>;
43513b49d1SSam Shih		regulator-max-microvolt = <3300000>;
44513b49d1SSam Shih		regulator-boot-on;
45513b49d1SSam Shih		regulator-always-on;
46513b49d1SSam Shih	};
4750137c15SSam Shih};
4850137c15SSam Shih
49ecc5287cSSam Shih&crypto {
50ecc5287cSSam Shih	status = "okay";
51ecc5287cSSam Shih};
52ecc5287cSSam Shih
53082ff36bSLorenzo Bianconi&eth {
54082ff36bSLorenzo Bianconi	status = "okay";
55082ff36bSLorenzo Bianconi
56082ff36bSLorenzo Bianconi	gmac0: mac@0 {
57082ff36bSLorenzo Bianconi		compatible = "mediatek,eth-mac";
58082ff36bSLorenzo Bianconi		reg = <0>;
59082ff36bSLorenzo Bianconi		phy-mode = "2500base-x";
60082ff36bSLorenzo Bianconi
61082ff36bSLorenzo Bianconi		fixed-link {
62082ff36bSLorenzo Bianconi			speed = <2500>;
63082ff36bSLorenzo Bianconi			full-duplex;
64082ff36bSLorenzo Bianconi			pause;
65082ff36bSLorenzo Bianconi		};
66082ff36bSLorenzo Bianconi	};
67082ff36bSLorenzo Bianconi
68082ff36bSLorenzo Bianconi	mdio: mdio-bus {
69082ff36bSLorenzo Bianconi		#address-cells = <1>;
70082ff36bSLorenzo Bianconi		#size-cells = <0>;
71082ff36bSLorenzo Bianconi	};
72082ff36bSLorenzo Bianconi};
73082ff36bSLorenzo Bianconi
74082ff36bSLorenzo Bianconi&mdio {
75082ff36bSLorenzo Bianconi	switch: switch@0 {
76082ff36bSLorenzo Bianconi		compatible = "mediatek,mt7531";
77082ff36bSLorenzo Bianconi		reg = <31>;
78082ff36bSLorenzo Bianconi		reset-gpios = <&pio 5 0>;
79082ff36bSLorenzo Bianconi	};
80082ff36bSLorenzo Bianconi};
81082ff36bSLorenzo Bianconi
82513b49d1SSam Shih&mmc0 {
83513b49d1SSam Shih	pinctrl-names = "default", "state_uhs";
84513b49d1SSam Shih	pinctrl-0 = <&mmc0_pins_default>;
85513b49d1SSam Shih	pinctrl-1 = <&mmc0_pins_uhs>;
86513b49d1SSam Shih	bus-width = <8>;
87513b49d1SSam Shih	max-frequency = <200000000>;
88513b49d1SSam Shih	cap-mmc-highspeed;
89513b49d1SSam Shih	mmc-hs200-1_8v;
90513b49d1SSam Shih	mmc-hs400-1_8v;
91513b49d1SSam Shih	hs400-ds-delay = <0x14014>;
92513b49d1SSam Shih	vmmc-supply = <&reg_3p3v>;
93513b49d1SSam Shih	vqmmc-supply = <&reg_1p8v>;
94513b49d1SSam Shih	non-removable;
95513b49d1SSam Shih	no-sd;
96513b49d1SSam Shih	no-sdio;
97918aed7aSSam Shih};
98918aed7aSSam Shih
99918aed7aSSam Shih&pcie {
100918aed7aSSam Shih	pinctrl-names = "default";
101918aed7aSSam Shih	pinctrl-0 = <&pcie_pins>;
102918aed7aSSam Shih	status = "okay";
103918aed7aSSam Shih};
104918aed7aSSam Shih
105918aed7aSSam Shih&pcie_phy {
106513b49d1SSam Shih	status = "okay";
107513b49d1SSam Shih};
108513b49d1SSam Shih
109965f2c04SSam Shih&pio {
110513b49d1SSam Shih	mmc0_pins_default: mmc0-pins {
111513b49d1SSam Shih		mux {
112513b49d1SSam Shih			function = "emmc";
113513b49d1SSam Shih			groups = "emmc_51";
114513b49d1SSam Shih		};
115513b49d1SSam Shih		conf-cmd-dat {
116513b49d1SSam Shih			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
117513b49d1SSam Shih			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
118513b49d1SSam Shih			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
119513b49d1SSam Shih			input-enable;
120513b49d1SSam Shih			drive-strength = <4>;
121513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
122513b49d1SSam Shih		};
123513b49d1SSam Shih		conf-clk {
124513b49d1SSam Shih			pins = "EMMC_CK";
125513b49d1SSam Shih			drive-strength = <6>;
126513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
127513b49d1SSam Shih		};
128513b49d1SSam Shih		conf-ds {
129513b49d1SSam Shih			pins = "EMMC_DSL";
130513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
131513b49d1SSam Shih		};
132513b49d1SSam Shih		conf-rst {
133513b49d1SSam Shih			pins = "EMMC_RSTB";
134513b49d1SSam Shih			drive-strength = <4>;
135513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
136513b49d1SSam Shih		};
137513b49d1SSam Shih	};
138513b49d1SSam Shih
139513b49d1SSam Shih	mmc0_pins_uhs: mmc0-uhs-pins {
140513b49d1SSam Shih		mux {
141513b49d1SSam Shih			function = "emmc";
142513b49d1SSam Shih			groups = "emmc_51";
143513b49d1SSam Shih		};
144513b49d1SSam Shih		conf-cmd-dat {
145513b49d1SSam Shih			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
146513b49d1SSam Shih			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
147513b49d1SSam Shih			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
148513b49d1SSam Shih			input-enable;
149513b49d1SSam Shih			drive-strength = <4>;
150513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
151513b49d1SSam Shih		};
152513b49d1SSam Shih		conf-clk {
153513b49d1SSam Shih			pins = "EMMC_CK";
154513b49d1SSam Shih			drive-strength = <6>;
155513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
156513b49d1SSam Shih		};
157513b49d1SSam Shih		conf-ds {
158513b49d1SSam Shih			pins = "EMMC_DSL";
159513b49d1SSam Shih			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
160513b49d1SSam Shih		};
161513b49d1SSam Shih		conf-rst {
162513b49d1SSam Shih			pins = "EMMC_RSTB";
163513b49d1SSam Shih			drive-strength = <4>;
164513b49d1SSam Shih			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
165513b49d1SSam Shih		};
166513b49d1SSam Shih	};
167513b49d1SSam Shih
168918aed7aSSam Shih	pcie_pins: pcie-pins {
169918aed7aSSam Shih		mux {
170918aed7aSSam Shih			function = "pcie";
171918aed7aSSam Shih			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
172918aed7aSSam Shih		};
173918aed7aSSam Shih	};
174918aed7aSSam Shih
175885e153eSSam Shih	spi_flash_pins: spi-flash-pins {
176885e153eSSam Shih		mux {
177885e153eSSam Shih			function = "spi";
178885e153eSSam Shih			groups = "spi0", "spi0_wp_hold";
179885e153eSSam Shih		};
180885e153eSSam Shih	};
181885e153eSSam Shih
182885e153eSSam Shih	spic_pins: spic-pins {
183885e153eSSam Shih		mux {
184885e153eSSam Shih			function = "spi";
185885e153eSSam Shih			groups = "spi1_2";
186885e153eSSam Shih		};
187885e153eSSam Shih	};
188885e153eSSam Shih
189965f2c04SSam Shih	uart1_pins: uart1-pins {
190965f2c04SSam Shih		mux {
191965f2c04SSam Shih			function = "uart";
192965f2c04SSam Shih			groups = "uart1";
193965f2c04SSam Shih		};
194965f2c04SSam Shih	};
195965f2c04SSam Shih
196965f2c04SSam Shih	uart2_pins: uart2-pins {
197965f2c04SSam Shih		mux {
198965f2c04SSam Shih			function = "uart";
199965f2c04SSam Shih			groups = "uart2";
200965f2c04SSam Shih		};
201965f2c04SSam Shih	};
202965f2c04SSam Shih
203965f2c04SSam Shih	wf_2g_5g_pins: wf-2g-5g-pins {
204965f2c04SSam Shih		mux {
205965f2c04SSam Shih			function = "wifi";
206965f2c04SSam Shih			groups = "wf_2g", "wf_5g";
207965f2c04SSam Shih		};
208965f2c04SSam Shih		conf {
209965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
210965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
211965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
212965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
213965f2c04SSam Shih			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
214965f2c04SSam Shih			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
215965f2c04SSam Shih			       "WF1_TOP_CLK", "WF1_TOP_DATA";
216965f2c04SSam Shih			drive-strength = <4>;
217965f2c04SSam Shih		};
218965f2c04SSam Shih	};
219965f2c04SSam Shih
220965f2c04SSam Shih	wf_dbdc_pins: wf-dbdc-pins {
221965f2c04SSam Shih		mux {
222965f2c04SSam Shih			function = "wifi";
223965f2c04SSam Shih			groups = "wf_dbdc";
224965f2c04SSam Shih		};
225965f2c04SSam Shih		conf {
226965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
227965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
228965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
229965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA";
230965f2c04SSam Shih			drive-strength = <4>;
231965f2c04SSam Shih		};
232965f2c04SSam Shih	};
233965f2c04SSam Shih};
234965f2c04SSam Shih
235885e153eSSam Shih&spi0 {
236885e153eSSam Shih	pinctrl-names = "default";
237885e153eSSam Shih	pinctrl-0 = <&spi_flash_pins>;
238885e153eSSam Shih	cs-gpios = <0>, <0>;
239885e153eSSam Shih	status = "okay";
240885e153eSSam Shih	spi_nand: spi_nand@0 {
241885e153eSSam Shih		compatible = "spi-nand";
242885e153eSSam Shih		reg = <0>;
243885e153eSSam Shih		spi-max-frequency = <10000000>;
244885e153eSSam Shih		spi-tx-buswidth = <4>;
245885e153eSSam Shih		spi-rx-buswidth = <4>;
246885e153eSSam Shih	};
247885e153eSSam Shih};
248885e153eSSam Shih
249885e153eSSam Shih&spi1 {
250885e153eSSam Shih	pinctrl-names = "default";
251885e153eSSam Shih	pinctrl-0 = <&spic_pins>;
252885e153eSSam Shih	cs-gpios = <0>, <0>;
253885e153eSSam Shih	status = "okay";
254885e153eSSam Shih};
255885e153eSSam Shih
256e21cbfc3SSam Shih&ssusb {
257e21cbfc3SSam Shih	status = "okay";
258e21cbfc3SSam Shih};
259e21cbfc3SSam Shih
260082ff36bSLorenzo Bianconi&switch {
261082ff36bSLorenzo Bianconi	ports {
262082ff36bSLorenzo Bianconi		#address-cells = <1>;
263082ff36bSLorenzo Bianconi		#size-cells = <0>;
264082ff36bSLorenzo Bianconi
265082ff36bSLorenzo Bianconi		port@0 {
266082ff36bSLorenzo Bianconi			reg = <0>;
267082ff36bSLorenzo Bianconi			label = "lan0";
268082ff36bSLorenzo Bianconi		};
269082ff36bSLorenzo Bianconi
270082ff36bSLorenzo Bianconi		port@1 {
271082ff36bSLorenzo Bianconi			reg = <1>;
272082ff36bSLorenzo Bianconi			label = "lan1";
273082ff36bSLorenzo Bianconi		};
274082ff36bSLorenzo Bianconi
275082ff36bSLorenzo Bianconi		port@2 {
276082ff36bSLorenzo Bianconi			reg = <2>;
277082ff36bSLorenzo Bianconi			label = "lan2";
278082ff36bSLorenzo Bianconi		};
279082ff36bSLorenzo Bianconi
280082ff36bSLorenzo Bianconi		port@3 {
281082ff36bSLorenzo Bianconi			reg = <3>;
282082ff36bSLorenzo Bianconi			label = "lan3";
283082ff36bSLorenzo Bianconi		};
284082ff36bSLorenzo Bianconi
285082ff36bSLorenzo Bianconi		port@4 {
286082ff36bSLorenzo Bianconi			reg = <4>;
287082ff36bSLorenzo Bianconi			label = "lan4";
288082ff36bSLorenzo Bianconi		};
289082ff36bSLorenzo Bianconi
290082ff36bSLorenzo Bianconi		port@6 {
291082ff36bSLorenzo Bianconi			reg = <6>;
292082ff36bSLorenzo Bianconi			label = "cpu";
293082ff36bSLorenzo Bianconi			ethernet = <&gmac0>;
294082ff36bSLorenzo Bianconi			phy-mode = "2500base-x";
295082ff36bSLorenzo Bianconi
296082ff36bSLorenzo Bianconi			fixed-link {
297082ff36bSLorenzo Bianconi				speed = <2500>;
298082ff36bSLorenzo Bianconi				full-duplex;
299082ff36bSLorenzo Bianconi				pause;
300082ff36bSLorenzo Bianconi			};
301082ff36bSLorenzo Bianconi		};
302082ff36bSLorenzo Bianconi	};
303082ff36bSLorenzo Bianconi};
304082ff36bSLorenzo Bianconi
30550137c15SSam Shih&uart0 {
30650137c15SSam Shih	status = "okay";
30750137c15SSam Shih};
30850137c15SSam Shih
30950137c15SSam Shih&uart1 {
310c3a064a3SSam Shih	pinctrl-names = "default";
311c3a064a3SSam Shih	pinctrl-0 = <&uart1_pins>;
31250137c15SSam Shih	status = "okay";
31350137c15SSam Shih};
31450137c15SSam Shih
31550137c15SSam Shih&uart2 {
316c3a064a3SSam Shih	pinctrl-names = "default";
317c3a064a3SSam Shih	pinctrl-0 = <&uart2_pins>;
31850137c15SSam Shih	status = "okay";
31950137c15SSam Shih};
320c3a064a3SSam Shih
321e21cbfc3SSam Shih&usb_phy {
322e21cbfc3SSam Shih	status = "okay";
323e21cbfc3SSam Shih};
324e21cbfc3SSam Shih
325300218b0SPeter Chiu&wifi {
326300218b0SPeter Chiu	status = "okay";
327300218b0SPeter Chiu	pinctrl-names = "default", "dbdc";
328300218b0SPeter Chiu	pinctrl-0 = <&wf_2g_5g_pins>;
329300218b0SPeter Chiu	pinctrl-1 = <&wf_dbdc_pins>;
330300218b0SPeter Chiu};
331