xref: /linux/scripts/dtc/include-prefixes/arm64/mediatek/mt7986a-rfb.dts (revision 2658963084567eb9505292470d40f7322006a69a)
150137c15SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT)
250137c15SSam Shih/*
350137c15SSam Shih * Copyright (C) 2021 MediaTek Inc.
450137c15SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com>
550137c15SSam Shih */
650137c15SSam Shih
750137c15SSam Shih/dts-v1/;
850137c15SSam Shih#include "mt7986a.dtsi"
950137c15SSam Shih
1050137c15SSam Shih/ {
1150137c15SSam Shih	model = "MediaTek MT7986a RFB";
12*26589630SMatthias Brugger	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
1350137c15SSam Shih
1450137c15SSam Shih	aliases {
1550137c15SSam Shih		serial0 = &uart0;
1650137c15SSam Shih	};
1750137c15SSam Shih
1850137c15SSam Shih	chosen {
1950137c15SSam Shih		stdout-path = "serial0:115200n8";
2050137c15SSam Shih	};
2150137c15SSam Shih
22fbaac5b1SSam Shih	memory@40000000 {
23fbaac5b1SSam Shih		device_type = "memory";
2450137c15SSam Shih		reg = <0 0x40000000 0 0x40000000>;
2550137c15SSam Shih	};
2650137c15SSam Shih};
2750137c15SSam Shih
28ecc5287cSSam Shih&crypto {
29ecc5287cSSam Shih	status = "okay";
30ecc5287cSSam Shih};
31ecc5287cSSam Shih
32082ff36bSLorenzo Bianconi&eth {
33082ff36bSLorenzo Bianconi	status = "okay";
34082ff36bSLorenzo Bianconi
35082ff36bSLorenzo Bianconi	gmac0: mac@0 {
36082ff36bSLorenzo Bianconi		compatible = "mediatek,eth-mac";
37082ff36bSLorenzo Bianconi		reg = <0>;
38082ff36bSLorenzo Bianconi		phy-mode = "2500base-x";
39082ff36bSLorenzo Bianconi
40082ff36bSLorenzo Bianconi		fixed-link {
41082ff36bSLorenzo Bianconi			speed = <2500>;
42082ff36bSLorenzo Bianconi			full-duplex;
43082ff36bSLorenzo Bianconi			pause;
44082ff36bSLorenzo Bianconi		};
45082ff36bSLorenzo Bianconi	};
46082ff36bSLorenzo Bianconi
47082ff36bSLorenzo Bianconi	mdio: mdio-bus {
48082ff36bSLorenzo Bianconi		#address-cells = <1>;
49082ff36bSLorenzo Bianconi		#size-cells = <0>;
50082ff36bSLorenzo Bianconi	};
51082ff36bSLorenzo Bianconi};
52082ff36bSLorenzo Bianconi
53082ff36bSLorenzo Bianconi&mdio {
54082ff36bSLorenzo Bianconi	switch: switch@0 {
55082ff36bSLorenzo Bianconi		compatible = "mediatek,mt7531";
56082ff36bSLorenzo Bianconi		reg = <31>;
57082ff36bSLorenzo Bianconi		reset-gpios = <&pio 5 0>;
58082ff36bSLorenzo Bianconi	};
59082ff36bSLorenzo Bianconi};
60082ff36bSLorenzo Bianconi
61965f2c04SSam Shih&pio {
62965f2c04SSam Shih	uart1_pins: uart1-pins {
63965f2c04SSam Shih		mux {
64965f2c04SSam Shih			function = "uart";
65965f2c04SSam Shih			groups = "uart1";
66965f2c04SSam Shih		};
67965f2c04SSam Shih	};
68965f2c04SSam Shih
69965f2c04SSam Shih	uart2_pins: uart2-pins {
70965f2c04SSam Shih		mux {
71965f2c04SSam Shih			function = "uart";
72965f2c04SSam Shih			groups = "uart2";
73965f2c04SSam Shih		};
74965f2c04SSam Shih	};
75965f2c04SSam Shih
76965f2c04SSam Shih	wf_2g_5g_pins: wf-2g-5g-pins {
77965f2c04SSam Shih		mux {
78965f2c04SSam Shih			function = "wifi";
79965f2c04SSam Shih			groups = "wf_2g", "wf_5g";
80965f2c04SSam Shih		};
81965f2c04SSam Shih		conf {
82965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
83965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
84965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
85965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
86965f2c04SSam Shih			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
87965f2c04SSam Shih			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
88965f2c04SSam Shih			       "WF1_TOP_CLK", "WF1_TOP_DATA";
89965f2c04SSam Shih			drive-strength = <4>;
90965f2c04SSam Shih		};
91965f2c04SSam Shih	};
92965f2c04SSam Shih
93965f2c04SSam Shih	wf_dbdc_pins: wf-dbdc-pins {
94965f2c04SSam Shih		mux {
95965f2c04SSam Shih			function = "wifi";
96965f2c04SSam Shih			groups = "wf_dbdc";
97965f2c04SSam Shih		};
98965f2c04SSam Shih		conf {
99965f2c04SSam Shih			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
100965f2c04SSam Shih			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
101965f2c04SSam Shih			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
102965f2c04SSam Shih			       "WF0_TOP_CLK", "WF0_TOP_DATA";
103965f2c04SSam Shih			drive-strength = <4>;
104965f2c04SSam Shih		};
105965f2c04SSam Shih	};
106965f2c04SSam Shih};
107965f2c04SSam Shih
108082ff36bSLorenzo Bianconi&switch {
109082ff36bSLorenzo Bianconi	ports {
110082ff36bSLorenzo Bianconi		#address-cells = <1>;
111082ff36bSLorenzo Bianconi		#size-cells = <0>;
112082ff36bSLorenzo Bianconi
113082ff36bSLorenzo Bianconi		port@0 {
114082ff36bSLorenzo Bianconi			reg = <0>;
115082ff36bSLorenzo Bianconi			label = "lan0";
116082ff36bSLorenzo Bianconi		};
117082ff36bSLorenzo Bianconi
118082ff36bSLorenzo Bianconi		port@1 {
119082ff36bSLorenzo Bianconi			reg = <1>;
120082ff36bSLorenzo Bianconi			label = "lan1";
121082ff36bSLorenzo Bianconi		};
122082ff36bSLorenzo Bianconi
123082ff36bSLorenzo Bianconi		port@2 {
124082ff36bSLorenzo Bianconi			reg = <2>;
125082ff36bSLorenzo Bianconi			label = "lan2";
126082ff36bSLorenzo Bianconi		};
127082ff36bSLorenzo Bianconi
128082ff36bSLorenzo Bianconi		port@3 {
129082ff36bSLorenzo Bianconi			reg = <3>;
130082ff36bSLorenzo Bianconi			label = "lan3";
131082ff36bSLorenzo Bianconi		};
132082ff36bSLorenzo Bianconi
133082ff36bSLorenzo Bianconi		port@4 {
134082ff36bSLorenzo Bianconi			reg = <4>;
135082ff36bSLorenzo Bianconi			label = "lan4";
136082ff36bSLorenzo Bianconi		};
137082ff36bSLorenzo Bianconi
138082ff36bSLorenzo Bianconi		port@6 {
139082ff36bSLorenzo Bianconi			reg = <6>;
140082ff36bSLorenzo Bianconi			label = "cpu";
141082ff36bSLorenzo Bianconi			ethernet = <&gmac0>;
142082ff36bSLorenzo Bianconi			phy-mode = "2500base-x";
143082ff36bSLorenzo Bianconi
144082ff36bSLorenzo Bianconi			fixed-link {
145082ff36bSLorenzo Bianconi				speed = <2500>;
146082ff36bSLorenzo Bianconi				full-duplex;
147082ff36bSLorenzo Bianconi				pause;
148082ff36bSLorenzo Bianconi			};
149082ff36bSLorenzo Bianconi		};
150082ff36bSLorenzo Bianconi	};
151082ff36bSLorenzo Bianconi};
152082ff36bSLorenzo Bianconi
15350137c15SSam Shih&uart0 {
15450137c15SSam Shih	status = "okay";
15550137c15SSam Shih};
15650137c15SSam Shih
15750137c15SSam Shih&uart1 {
158c3a064a3SSam Shih	pinctrl-names = "default";
159c3a064a3SSam Shih	pinctrl-0 = <&uart1_pins>;
16050137c15SSam Shih	status = "okay";
16150137c15SSam Shih};
16250137c15SSam Shih
16350137c15SSam Shih&uart2 {
164c3a064a3SSam Shih	pinctrl-names = "default";
165c3a064a3SSam Shih	pinctrl-0 = <&uart2_pins>;
16650137c15SSam Shih	status = "okay";
16750137c15SSam Shih};
168c3a064a3SSam Shih
169300218b0SPeter Chiu&wifi {
170300218b0SPeter Chiu	status = "okay";
171300218b0SPeter Chiu	pinctrl-names = "default", "dbdc";
172300218b0SPeter Chiu	pinctrl-0 = <&wf_2g_5g_pins>;
173300218b0SPeter Chiu	pinctrl-1 = <&wf_dbdc_pins>;
174300218b0SPeter Chiu};
175