xref: /linux/scripts/dtc/include-prefixes/arm64/intel/socfpga_agilex5_socdk_modular.dts (revision 6589b3d76db2d6adbf8f2084c303fb24252a0dc6)

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2025, Altera Corporation
 */
#include "socfpga_agilex5.dtsi"

/ {
	model = "SoCFPGA Agilex5 SoCDK - Modular development kit";
	compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5";

	aliases {
		serial0 = &uart0;
		ethernet2 = &gmac2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led0 {
			label = "hps_led0";
			gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0x0 0x80000000 0x0 0x0>;
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gmac2 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&emac2_phy0>;
	max-frame-size = <9000>;

	mdio0 {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		emac2_phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&osc1 {
	clock-frequency = <25000000>;
};

&qspi {
	status = "okay";
	flash@0 {
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;
		m25p,fast-read;
		cdns,read-delay = <2>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			qspi_boot: partition@0 {
				label = "u-boot";
				reg = <0x0 0x04200000>;
			};

			root: partition@4200000 {
				label = "root";
				reg = <0x04200000 0x0be00000>;
			};
		};
	};
};

&smmu {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&watchdog0 {
	status = "okay";
};