1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3670 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 * Copyright (C) 2018, Linaro Ltd. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "hisilicon,hi3670"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "psci"; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 device_type = "cpu"; 67 reg = <0x0 0x1>; 68 enable-method = "psci"; 69 }; 70 71 cpu2: cpu@2 { 72 compatible = "arm,cortex-a53", "arm,armv8"; 73 device_type = "cpu"; 74 reg = <0x0 0x2>; 75 enable-method = "psci"; 76 }; 77 78 cpu3: cpu@3 { 79 compatible = "arm,cortex-a53", "arm,armv8"; 80 device_type = "cpu"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 }; 84 85 cpu4: cpu@100 { 86 compatible = "arm,cortex-a73", "arm,armv8"; 87 device_type = "cpu"; 88 reg = <0x0 0x100>; 89 enable-method = "psci"; 90 }; 91 92 cpu5: cpu@101 { 93 compatible = "arm,cortex-a73", "arm,armv8"; 94 device_type = "cpu"; 95 reg = <0x0 0x101>; 96 enable-method = "psci"; 97 }; 98 99 cpu6: cpu@102 { 100 compatible = "arm,cortex-a73", "arm,armv8"; 101 device_type = "cpu"; 102 reg = <0x0 0x102>; 103 enable-method = "psci"; 104 }; 105 106 cpu7: cpu@103 { 107 compatible = "arm,cortex-a73", "arm,armv8"; 108 device_type = "cpu"; 109 reg = <0x0 0x103>; 110 enable-method = "psci"; 111 }; 112 }; 113 114 gic: interrupt-controller@e82b0000 { 115 compatible = "arm,gic-400"; 116 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 117 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 118 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 119 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 120 #interrupt-cells = <3>; 121 #address-cells = <0>; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 123 IRQ_TYPE_LEVEL_HIGH)>; 124 interrupt-controller; 125 }; 126 127 timer { 128 compatible = "arm,armv8-timer"; 129 interrupt-parent = <&gic>; 130 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 131 IRQ_TYPE_LEVEL_LOW)>, 132 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 133 IRQ_TYPE_LEVEL_LOW)>, 134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 135 IRQ_TYPE_LEVEL_LOW)>, 136 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 137 IRQ_TYPE_LEVEL_LOW)>; 138 clock-frequency = <1920000>; 139 }; 140 141 soc { 142 compatible = "simple-bus"; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges; 146 147 uart6_clk: clk_19_2M { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <19200000>; 151 }; 152 153 uart6: serial@fff32000 { 154 compatible = "arm,pl011", "arm,primecell"; 155 reg = <0x0 0xfff32000 0x0 0x1000>; 156 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&uart6_clk &uart6_clk>; 158 clock-names = "uartclk", "apb_pclk"; 159 status = "disabled"; 160 }; 161 }; 162}; 163