xref: /linux/scripts/dtc/include-prefixes/arm64/hisilicon/hi3670.dtsi (revision c00e3f8080d1ad8645ba51ae34817df830b44fa2)

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hisilicon Hi3670 SoC
 *
 * Copyright (C) 2016, Hisilicon Ltd.
 * Copyright (C) 2018, Linaro Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3670-clock.h>

/ {
	compatible = "hisilicon,hi3670";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x101>;
			enable-method = "psci";
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x102>;
			enable-method = "psci";
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x103>;
			enable-method = "psci";
		};
	};

	gic: interrupt-controller@e82b0000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
		      <0x0 0xe82b2000 0 0x2000>, /* GICC */
		      <0x0 0xe82b4000 0 0x2000>, /* GICH */
		      <0x0 0xe82b6000 0 0x2000>; /* GICV */
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
					 IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-controller;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <1920000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		crg_ctrl: crg_ctrl@fff35000 {
			compatible = "hisilicon,hi3670-crgctrl", "syscon";
			reg = <0x0 0xfff35000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		pctrl: pctrl@e8a09000 {
			compatible = "hisilicon,hi3670-pctrl", "syscon";
			reg = <0x0 0xe8a09000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		pmuctrl: crg_ctrl@fff34000 {
			compatible = "hisilicon,hi3670-pmuctrl", "syscon";
			reg = <0x0 0xfff34000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		sctrl: sctrl@fff0a000 {
			compatible = "hisilicon,hi3670-sctrl", "syscon";
			reg = <0x0 0xfff0a000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		iomcu: iomcu@ffd7e000 {
			compatible = "hisilicon,hi3670-iomcu", "syscon";
			reg = <0x0 0xffd7e000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		media1_crg: media1_crgctrl@e87ff000 {
			compatible = "hisilicon,hi3670-media1-crg", "syscon";
			reg = <0x0 0xe87ff000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		media2_crg: media2_crgctrl@e8900000 {
			compatible = "hisilicon,hi3670-media2-crg","syscon";
			reg = <0x0 0xe8900000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		uart6_clk: clk_19_2M {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		uart6: serial@fff32000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfff32000 0x0 0x1000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart6_clk &uart6_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};