xref: /linux/scripts/dtc/include-prefixes/arm64/freescale/imx95-tqma9596la.dtsi (revision 67f8bc848ee31831336bd478e57d2f993551902e)

// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright (c) 2024-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
 * D-82229 Seefeld, Germany.
 * Author: Alexander Stein
 * Author: Markus Niebel
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "imx95.dtsi"

/ {
	memory@80000000 {
		device_type = "memory";
		/*
		 * DRAM base addr, size : 2048 MiB DRAM
		 * should be corrected by bootloader
		 */
		reg = <0 0x80000000 0 0x80000000>;
	};

	reg_1v8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "V_1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "V_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_sdvmmc: regulator-sdvmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sdvmmc>;
		regulator-name = "SD_PWR_EN";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <12000>;
		enable-active-high;
		/* can be enabled by mainboard with SD-Card support */
		status = "disabled";
	};
};

&adc1 {
	vref-supply = <&reg_1v8>;
};

&flexspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi1>;
	status = "okay";

	flash0: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <66000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		vcc-supply = <&reg_1v8>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};
};

/* System Manager */
&gpio1 {
	status = "reserved";
};

/* System Manager */
&lpi2c1 {
	status = "reserved";
};

&lpi2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	status = "okay";

	pcf85063: rtc@51 {
		compatible = "nxp,pcf85063a";
		reg = <0x51>;
		quartz-load-femtofarads = <7000>;
	};

	m24c64: eeprom@54 {
		compatible = "atmel,24c64";
		reg = <0x54>;
		pagesize = <32>;
		vcc-supply = <&reg_3v3>;
	};

	/* protectable identification memory (part of M24C64-D @54) */
	eeprom@5c {
		compatible = "atmel,24c64d-wl";
		reg = <0x5c>;
		pagesize = <32>;
		vcc-supply = <&reg_3v3>;
	};

	imu@6b {
		compatible = "st,ism330dhcx";
		reg = <0x6b>;
		vdd-supply = <&reg_3v3>;
		vddio-supply = <&reg_3v3>;
	};
};

&thermal_zones {
	pf09-thermal {
		polling-delay = <2000>;
		polling-delay-passive = <250>;
		thermal-sensors = <&scmi_sensor 2>;

		trips {
			pf09_alert: trip0 {
				hysteresis = <2000>;
				temperature = <140000>;
				type = "passive";
			};

			pf09_crit: trip1 {
				hysteresis = <2000>;
				temperature = <155000>;
				type = "critical";
			};
		};
	};

	pf53arm-thermal {
		polling-delay = <2000>;
		polling-delay-passive = <250>;
		thermal-sensors = <&scmi_sensor 4>;

		cooling-maps {
			map0 {
				trip = <&pf5301_alert>;
				cooling-device =
					<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};

		trips {
			pf5301_alert: trip0 {
				hysteresis = <2000>;
				temperature = <140000>;
				type = "passive";
			};

			pf5301_crit: trip1 {
				hysteresis = <2000>;
				temperature = <155000>;
				type = "critical";
			};
		};
	};

	pf53soc-thermal {
		polling-delay = <2000>;
		polling-delay-passive = <250>;
		thermal-sensors = <&scmi_sensor 3>;

		trips {
			pf5302_alert: trip0 {
				hysteresis = <2000>;
				temperature = <140000>;
				type = "passive";
			};

			pf5302_crit: trip1 {
				hysteresis = <2000>;
				temperature = <155000>;
				type = "critical";
			};
		};
	};
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	no-sdio;
	no-sd;
	status = "okay";
};

&wdog3 {
	status = "okay";
};

&scmi_iomuxc {
	pinctrl_flexspi1: flexspi1grp {
		fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B	0x19e>,
			   <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0	0x19e>,
			   <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1	0x19e>,
			   <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2	0x19e>,
			   <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3	0x19e>,
			   /* SION to allow clock loopback from pad */
			   <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK	0x4000019e>,
			   <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS		0x4000019e>;
	};

	pinctrl_lpi2c2: lpi2c2grp {
		fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL	0x4000191e>,
			   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA	0x4000191e>;
	};

	pinctrl_sdvmmc: sdvmmcgrp {
		fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7	0x11e>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e>,
			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e>,
			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e>,
			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e>,
			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e>,
			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e>,
			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e>,
			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e>,
			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e>,
			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e>,
			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e>,
			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e>,
			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e>,
			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e>,
			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e>,
			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e>,
			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e>,
			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e>,
			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e>,
			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e>,
			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x15fe>,
			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x13fe>,
			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe>,
			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe>,
			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe>,
			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe>,
			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe>,
			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe>,
			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe>,
			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe>,
			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe>;
	};
};