1*6c41fe59SSherry Sun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*6c41fe59SSherry Sun/* 3*6c41fe59SSherry Sun * Copyright 2026 NXP 4*6c41fe59SSherry Sun */ 5*6c41fe59SSherry Sun 6*6c41fe59SSherry Sun#include "imx93.dtsi" 7*6c41fe59SSherry Sun 8*6c41fe59SSherry Sun/ { 9*6c41fe59SSherry Sun aliases { 10*6c41fe59SSherry Sun mmc2 = &usdhc3; 11*6c41fe59SSherry Sun }; 12*6c41fe59SSherry Sun 13*6c41fe59SSherry Sun reg_usdhc3_vmmc: regulator-usdhc3 { 14*6c41fe59SSherry Sun compatible = "regulator-fixed"; 15*6c41fe59SSherry Sun pinctrl-names = "default"; 16*6c41fe59SSherry Sun pinctrl-0 = <&pinctrl_reg_usdhc3_vmmc>; 17*6c41fe59SSherry Sun regulator-name = "WLAN_EN"; 18*6c41fe59SSherry Sun regulator-min-microvolt = <3300000>; 19*6c41fe59SSherry Sun regulator-max-microvolt = <3300000>; 20*6c41fe59SSherry Sun gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 21*6c41fe59SSherry Sun enable-active-high; 22*6c41fe59SSherry Sun }; 23*6c41fe59SSherry Sun 24*6c41fe59SSherry Sun usdhc3_pwrseq: usdhc3_pwrseq { 25*6c41fe59SSherry Sun compatible = "mmc-pwrseq-simple"; 26*6c41fe59SSherry Sun pinctrl-names = "default"; 27*6c41fe59SSherry Sun pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; 28*6c41fe59SSherry Sun reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 29*6c41fe59SSherry Sun }; 30*6c41fe59SSherry Sun}; 31*6c41fe59SSherry Sun 32*6c41fe59SSherry Sun&usdhc3 { 33*6c41fe59SSherry Sun pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 34*6c41fe59SSherry Sun pinctrl-0 = <&pinctrl_usdhc3>; 35*6c41fe59SSherry Sun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 36*6c41fe59SSherry Sun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 37*6c41fe59SSherry Sun pinctrl-3 = <&pinctrl_usdhc3_sleep>; 38*6c41fe59SSherry Sun mmc-pwrseq = <&usdhc3_pwrseq>; 39*6c41fe59SSherry Sun vmmc-supply = <®_usdhc3_vmmc>; 40*6c41fe59SSherry Sun bus-width = <4>; 41*6c41fe59SSherry Sun keep-power-in-suspend; 42*6c41fe59SSherry Sun non-removable; 43*6c41fe59SSherry Sun wakeup-source; 44*6c41fe59SSherry Sun status = "okay"; 45*6c41fe59SSherry Sun}; 46*6c41fe59SSherry Sun 47*6c41fe59SSherry Sun&iomuxc { 48*6c41fe59SSherry Sun pinctrl_reg_usdhc3_vmmc: regusdhc3vmmcgrp { 49*6c41fe59SSherry Sun fsl,pins = < 50*6c41fe59SSherry Sun /* 51*6c41fe59SSherry Sun * Enable open drain and internal pull-up to allow the IW610 JTAG 52*6c41fe59SSherry Sun * connector to control the PDn status. 53*6c41fe59SSherry Sun */ 54*6c41fe59SSherry Sun MX93_PAD_GPIO_IO29__GPIO2_IO29 0xb9e 55*6c41fe59SSherry Sun >; 56*6c41fe59SSherry Sun }; 57*6c41fe59SSherry Sun 58*6c41fe59SSherry Sun /* need to config the SION for data and cmd pad, refer to ERR052021 */ 59*6c41fe59SSherry Sun pinctrl_usdhc3: usdhc3grp { 60*6c41fe59SSherry Sun fsl,pins = < 61*6c41fe59SSherry Sun MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 62*6c41fe59SSherry Sun MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 63*6c41fe59SSherry Sun MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 64*6c41fe59SSherry Sun MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 65*6c41fe59SSherry Sun MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 66*6c41fe59SSherry Sun MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 67*6c41fe59SSherry Sun >; 68*6c41fe59SSherry Sun }; 69*6c41fe59SSherry Sun 70*6c41fe59SSherry Sun /* need to config the SION for data and cmd pad, refer to ERR052021 */ 71*6c41fe59SSherry Sun pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 72*6c41fe59SSherry Sun fsl,pins = < 73*6c41fe59SSherry Sun MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 74*6c41fe59SSherry Sun MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 75*6c41fe59SSherry Sun MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 76*6c41fe59SSherry Sun MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 77*6c41fe59SSherry Sun MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 78*6c41fe59SSherry Sun MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 79*6c41fe59SSherry Sun >; 80*6c41fe59SSherry Sun }; 81*6c41fe59SSherry Sun 82*6c41fe59SSherry Sun /* need to config the SION for data and cmd pad, refer to ERR052021 */ 83*6c41fe59SSherry Sun pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 84*6c41fe59SSherry Sun fsl,pins = < 85*6c41fe59SSherry Sun MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 86*6c41fe59SSherry Sun MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 87*6c41fe59SSherry Sun MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 88*6c41fe59SSherry Sun MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 89*6c41fe59SSherry Sun MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 90*6c41fe59SSherry Sun MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 91*6c41fe59SSherry Sun >; 92*6c41fe59SSherry Sun }; 93*6c41fe59SSherry Sun 94*6c41fe59SSherry Sun pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { 95*6c41fe59SSherry Sun fsl,pins = < 96*6c41fe59SSherry Sun MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e 97*6c41fe59SSherry Sun MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e 98*6c41fe59SSherry Sun MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e 99*6c41fe59SSherry Sun MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e 100*6c41fe59SSherry Sun MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e 101*6c41fe59SSherry Sun MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e 102*6c41fe59SSherry Sun >; 103*6c41fe59SSherry Sun }; 104*6c41fe59SSherry Sun 105*6c41fe59SSherry Sun pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { 106*6c41fe59SSherry Sun fsl,pins = < 107*6c41fe59SSherry Sun MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x39e 108*6c41fe59SSherry Sun >; 109*6c41fe59SSherry Sun }; 110*6c41fe59SSherry Sun}; 111