1*9ceb1cf5SLaurentiu Mihalcea /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2*9ceb1cf5SLaurentiu Mihalcea /* 3*9ceb1cf5SLaurentiu Mihalcea * Copyright 2025 NXP 4*9ceb1cf5SLaurentiu Mihalcea */ 5*9ceb1cf5SLaurentiu Mihalcea 6*9ceb1cf5SLaurentiu Mihalcea #ifndef __IMX8MP_AIPSTZ_H 7*9ceb1cf5SLaurentiu Mihalcea #define __IMX8MP_AIPSTZ_H 8*9ceb1cf5SLaurentiu Mihalcea 9*9ceb1cf5SLaurentiu Mihalcea /* consumer type - master or peripheral */ 10*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_MASTER 0x0 11*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_PERIPH 0x1 12*9ceb1cf5SLaurentiu Mihalcea 13*9ceb1cf5SLaurentiu Mihalcea /* master configuration options */ 14*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_MPL (1 << 0) 15*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_MTW (1 << 1) 16*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_MTR (1 << 2) 17*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_MBW (1 << 3) 18*9ceb1cf5SLaurentiu Mihalcea 19*9ceb1cf5SLaurentiu Mihalcea /* peripheral configuration options */ 20*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_TP (1 << 0) 21*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_WP (1 << 1) 22*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_SP (1 << 2) 23*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_BW (1 << 3) 24*9ceb1cf5SLaurentiu Mihalcea 25*9ceb1cf5SLaurentiu Mihalcea /* master ID definitions */ 26*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_EDMA 0 /* AUDIOMIX EDMA */ 27*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_CA53 1 /* Cortex-A53 cluster */ 28*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_SDMA2 3 /* AUDIOMIX SDMA2 */ 29*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_SDMA3 3 /* AUDIOMIX SDMA3 */ 30*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_HIFI4 5 /* HIFI4 DSP */ 31*9ceb1cf5SLaurentiu Mihalcea #define IMX8MP_AIPSTZ_CM7 6 /* Cortex-M7 */ 32*9ceb1cf5SLaurentiu Mihalcea 33*9ceb1cf5SLaurentiu Mihalcea #endif /* __IMX8MP_AIPSTZ_H */ 34