xref: /linux/scripts/dtc/include-prefixes/arm64/freescale/imx8mm-var-dart-sonata.dts (revision 67f8bc848ee31831336bd478e57d2f993551902e)
1*770aba46SStefano Radaelli// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*770aba46SStefano Radaelli/*
3*770aba46SStefano Radaelli * Variscite Sonata carrier board for DART-MX8M-MINI
4*770aba46SStefano Radaelli *
5*770aba46SStefano Radaelli * Link: https://variscite.com/carrier-boards/sonata-board/
6*770aba46SStefano Radaelli *
7*770aba46SStefano Radaelli * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
8*770aba46SStefano Radaelli *
9*770aba46SStefano Radaelli */
10*770aba46SStefano Radaelli
11*770aba46SStefano Radaelli/dts-v1/;
12*770aba46SStefano Radaelli
13*770aba46SStefano Radaelli#include <dt-bindings/leds/common.h>
14*770aba46SStefano Radaelli#include <dt-bindings/phy/phy-imx8-pcie.h>
15*770aba46SStefano Radaelli#include "imx8mm-var-dart.dtsi"
16*770aba46SStefano Radaelli
17*770aba46SStefano Radaelli/ {
18*770aba46SStefano Radaelli	model = "Variscite DART-MX8M-MINI on Sonata-Board";
19*770aba46SStefano Radaelli	compatible = "variscite,var-dart-mx8mm-sonata",
20*770aba46SStefano Radaelli		     "variscite,var-dart-mx8mm",
21*770aba46SStefano Radaelli		     "fsl,imx8mm";
22*770aba46SStefano Radaelli
23*770aba46SStefano Radaelli	chosen {
24*770aba46SStefano Radaelli		stdout-path = &uart1;
25*770aba46SStefano Radaelli	};
26*770aba46SStefano Radaelli
27*770aba46SStefano Radaelli	gpio-keys {
28*770aba46SStefano Radaelli		compatible = "gpio-keys";
29*770aba46SStefano Radaelli
30*770aba46SStefano Radaelli		button-home {
31*770aba46SStefano Radaelli			label = "Home";
32*770aba46SStefano Radaelli			linux,code = <KEY_HOME>;
33*770aba46SStefano Radaelli			gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
34*770aba46SStefano Radaelli			wakeup-source;
35*770aba46SStefano Radaelli		};
36*770aba46SStefano Radaelli
37*770aba46SStefano Radaelli		button-up {
38*770aba46SStefano Radaelli			label = "Up";
39*770aba46SStefano Radaelli			linux,code = <KEY_UP>;
40*770aba46SStefano Radaelli			gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
41*770aba46SStefano Radaelli			wakeup-source;
42*770aba46SStefano Radaelli		};
43*770aba46SStefano Radaelli
44*770aba46SStefano Radaelli		button-down {
45*770aba46SStefano Radaelli			label = "Down";
46*770aba46SStefano Radaelli			linux,code = <KEY_DOWN>;
47*770aba46SStefano Radaelli			gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
48*770aba46SStefano Radaelli			wakeup-source;
49*770aba46SStefano Radaelli		};
50*770aba46SStefano Radaelli
51*770aba46SStefano Radaelli		button-back {
52*770aba46SStefano Radaelli			label = "Back";
53*770aba46SStefano Radaelli			linux,code = <KEY_BACK>;
54*770aba46SStefano Radaelli			gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
55*770aba46SStefano Radaelli			wakeup-source;
56*770aba46SStefano Radaelli		};
57*770aba46SStefano Radaelli	};
58*770aba46SStefano Radaelli
59*770aba46SStefano Radaelli	gpio-leds {
60*770aba46SStefano Radaelli		compatible = "gpio-leds";
61*770aba46SStefano Radaelli		pinctrl-names = "default";
62*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_gpio_leds>;
63*770aba46SStefano Radaelli
64*770aba46SStefano Radaelli		led-emmc {
65*770aba46SStefano Radaelli			gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
66*770aba46SStefano Radaelli			label = "eMMC";
67*770aba46SStefano Radaelli			linux,default-trigger = "mmc2";
68*770aba46SStefano Radaelli		};
69*770aba46SStefano Radaelli	};
70*770aba46SStefano Radaelli
71*770aba46SStefano Radaelli	clk40m: oscillator {
72*770aba46SStefano Radaelli		compatible = "fixed-clock";
73*770aba46SStefano Radaelli		#clock-cells = <0>;
74*770aba46SStefano Radaelli		clock-frequency = <40000000>;
75*770aba46SStefano Radaelli		clock-output-names = "can_osc";
76*770aba46SStefano Radaelli	};
77*770aba46SStefano Radaelli
78*770aba46SStefano Radaelli	pcie0_refclk: pcie0-refclk {
79*770aba46SStefano Radaelli		compatible = "fixed-clock";
80*770aba46SStefano Radaelli		#clock-cells = <0>;
81*770aba46SStefano Radaelli		clock-frequency = <100000000>;
82*770aba46SStefano Radaelli	};
83*770aba46SStefano Radaelli
84*770aba46SStefano Radaelli	reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
85*770aba46SStefano Radaelli		compatible = "regulator-fixed";
86*770aba46SStefano Radaelli		pinctrl-names = "default";
87*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_vmmc_usdhc2>;
88*770aba46SStefano Radaelli		regulator-name = "VSD_3V3";
89*770aba46SStefano Radaelli		regulator-min-microvolt = <3300000>;
90*770aba46SStefano Radaelli		regulator-max-microvolt = <3300000>;
91*770aba46SStefano Radaelli		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
92*770aba46SStefano Radaelli		enable-active-high;
93*770aba46SStefano Radaelli		startup-delay-us = <100>;
94*770aba46SStefano Radaelli		off-on-delay-us = <12000>;
95*770aba46SStefano Radaelli	};
96*770aba46SStefano Radaelli};
97*770aba46SStefano Radaelli
98*770aba46SStefano Radaelli&ecspi1 {
99*770aba46SStefano Radaelli	pinctrl-names = "default";
100*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_ecspi1>;
101*770aba46SStefano Radaelli	cs-gpios = <&gpio5  9 GPIO_ACTIVE_LOW>,
102*770aba46SStefano Radaelli		   <&gpio1 12 GPIO_ACTIVE_LOW>;
103*770aba46SStefano Radaelli	status = "okay";
104*770aba46SStefano Radaelli
105*770aba46SStefano Radaelli	/* Resistive touch controller */
106*770aba46SStefano Radaelli	ads7846: touchscreen@0 {
107*770aba46SStefano Radaelli		compatible = "ti,ads7846";
108*770aba46SStefano Radaelli		reg = <0>;
109*770aba46SStefano Radaelli		pinctrl-names = "default";
110*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_restouch>;
111*770aba46SStefano Radaelli		interrupt-parent = <&gpio1>;
112*770aba46SStefano Radaelli		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
113*770aba46SStefano Radaelli		spi-max-frequency = <1500000>;
114*770aba46SStefano Radaelli		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
115*770aba46SStefano Radaelli		ti,x-min = /bits/ 16 <125>;
116*770aba46SStefano Radaelli		ti,x-max = /bits/ 16 <4008>;
117*770aba46SStefano Radaelli		ti,y-min = /bits/ 16 <282>;
118*770aba46SStefano Radaelli		ti,y-max = /bits/ 16 <3864>;
119*770aba46SStefano Radaelli		ti,x-plate-ohms = /bits/ 16 <180>;
120*770aba46SStefano Radaelli		ti,pressure-max = /bits/ 16 <255>;
121*770aba46SStefano Radaelli		ti,debounce-max = /bits/ 16 <10>;
122*770aba46SStefano Radaelli		ti,debounce-tol = /bits/ 16 <3>;
123*770aba46SStefano Radaelli		ti,debounce-rep = /bits/ 16 <1>;
124*770aba46SStefano Radaelli		ti,settle-delay-usec = /bits/ 16 <150>;
125*770aba46SStefano Radaelli		ti,keep-vref-on;
126*770aba46SStefano Radaelli		wakeup-source;
127*770aba46SStefano Radaelli	};
128*770aba46SStefano Radaelli
129*770aba46SStefano Radaelli	can0: can@1 {
130*770aba46SStefano Radaelli		compatible = "microchip,mcp251xfd";
131*770aba46SStefano Radaelli		reg = <1>;
132*770aba46SStefano Radaelli		pinctrl-names = "default";
133*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_can>;
134*770aba46SStefano Radaelli		clocks = <&clk40m>;
135*770aba46SStefano Radaelli		interrupt-parent = <&gpio1>;
136*770aba46SStefano Radaelli		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
137*770aba46SStefano Radaelli		microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
138*770aba46SStefano Radaelli		spi-max-frequency = <20000000>;
139*770aba46SStefano Radaelli	};
140*770aba46SStefano Radaelli};
141*770aba46SStefano Radaelli
142*770aba46SStefano Radaelli&ethphy0 {
143*770aba46SStefano Radaelli	leds {
144*770aba46SStefano Radaelli		#address-cells = <1>;
145*770aba46SStefano Radaelli		#size-cells = <0>;
146*770aba46SStefano Radaelli
147*770aba46SStefano Radaelli		led@0 {
148*770aba46SStefano Radaelli			reg = <0>;
149*770aba46SStefano Radaelli			color = <LED_COLOR_ID_YELLOW>;
150*770aba46SStefano Radaelli			function = LED_FUNCTION_LAN;
151*770aba46SStefano Radaelli			linux,default-trigger = "netdev";
152*770aba46SStefano Radaelli		};
153*770aba46SStefano Radaelli
154*770aba46SStefano Radaelli		led@1 {
155*770aba46SStefano Radaelli			reg = <1>;
156*770aba46SStefano Radaelli			color = <LED_COLOR_ID_GREEN>;
157*770aba46SStefano Radaelli			function = LED_FUNCTION_LAN;
158*770aba46SStefano Radaelli			linux,default-trigger = "netdev";
159*770aba46SStefano Radaelli		};
160*770aba46SStefano Radaelli	};
161*770aba46SStefano Radaelli};
162*770aba46SStefano Radaelli
163*770aba46SStefano Radaelli&i2c2 {
164*770aba46SStefano Radaelli	clock-frequency = <100000>;
165*770aba46SStefano Radaelli	pinctrl-names = "default", "gpio";
166*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_i2c2>;
167*770aba46SStefano Radaelli	pinctrl-1 = <&pinctrl_i2c2_gpio>;
168*770aba46SStefano Radaelli	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
169*770aba46SStefano Radaelli	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
170*770aba46SStefano Radaelli	status = "okay";
171*770aba46SStefano Radaelli
172*770aba46SStefano Radaelli	pca9534: gpio@22 {
173*770aba46SStefano Radaelli		compatible = "nxp,pca9534";
174*770aba46SStefano Radaelli		reg = <0x22>;
175*770aba46SStefano Radaelli		gpio-controller;
176*770aba46SStefano Radaelli		#gpio-cells = <2>;
177*770aba46SStefano Radaelli
178*770aba46SStefano Radaelli		/* RGB_SEL */
179*770aba46SStefano Radaelli		lvds-brg-enable-hog {
180*770aba46SStefano Radaelli			gpio-hog;
181*770aba46SStefano Radaelli			gpios = <7 GPIO_ACTIVE_HIGH>;
182*770aba46SStefano Radaelli			output-low;
183*770aba46SStefano Radaelli			line-name = "rgb_sel";
184*770aba46SStefano Radaelli		};
185*770aba46SStefano Radaelli	};
186*770aba46SStefano Radaelli
187*770aba46SStefano Radaelli	/* Capacitive touch controller */
188*770aba46SStefano Radaelli	ft5x06_ts: touchscreen@38 {
189*770aba46SStefano Radaelli		compatible = "edt,edt-ft5206";
190*770aba46SStefano Radaelli		reg = <0x38>;
191*770aba46SStefano Radaelli		pinctrl-names = "default";
192*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_captouch>;
193*770aba46SStefano Radaelli		reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
194*770aba46SStefano Radaelli		interrupt-parent = <&gpio1>;
195*770aba46SStefano Radaelli		interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
196*770aba46SStefano Radaelli		touchscreen-size-x = <800>;
197*770aba46SStefano Radaelli		touchscreen-size-y = <480>;
198*770aba46SStefano Radaelli		touchscreen-inverted-x;
199*770aba46SStefano Radaelli		touchscreen-inverted-y;
200*770aba46SStefano Radaelli		wakeup-source;
201*770aba46SStefano Radaelli	};
202*770aba46SStefano Radaelli
203*770aba46SStefano Radaelli	extcon_ptn5150: typec@3d {
204*770aba46SStefano Radaelli		compatible = "nxp,ptn5150";
205*770aba46SStefano Radaelli		reg = <0x3d>;
206*770aba46SStefano Radaelli		pinctrl-names = "default";
207*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_extcon>;
208*770aba46SStefano Radaelli		interrupt-parent = <&gpio1>;
209*770aba46SStefano Radaelli		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
210*770aba46SStefano Radaelli
211*770aba46SStefano Radaelli		port {
212*770aba46SStefano Radaelli			typec1_dr_sw: endpoint {
213*770aba46SStefano Radaelli				remote-endpoint = <&usb1_drd_sw>;
214*770aba46SStefano Radaelli			};
215*770aba46SStefano Radaelli		};
216*770aba46SStefano Radaelli	};
217*770aba46SStefano Radaelli
218*770aba46SStefano Radaelli	rtc@68 {
219*770aba46SStefano Radaelli		compatible = "dallas,ds1337";
220*770aba46SStefano Radaelli		reg = <0x68>;
221*770aba46SStefano Radaelli		pinctrl-names = "default";
222*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_rtc>;
223*770aba46SStefano Radaelli		interrupt-parent = <&gpio1>;
224*770aba46SStefano Radaelli		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
225*770aba46SStefano Radaelli		wakeup-source;
226*770aba46SStefano Radaelli	};
227*770aba46SStefano Radaelli};
228*770aba46SStefano Radaelli
229*770aba46SStefano Radaelli&i2c4 {
230*770aba46SStefano Radaelli	clock-frequency = <100000>;
231*770aba46SStefano Radaelli	pinctrl-names = "default", "gpio";
232*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_i2c4>;
233*770aba46SStefano Radaelli	pinctrl-1 = <&pinctrl_i2c4_gpio>;
234*770aba46SStefano Radaelli	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
235*770aba46SStefano Radaelli	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
236*770aba46SStefano Radaelli	status = "okay";
237*770aba46SStefano Radaelli
238*770aba46SStefano Radaelli	pca6408_1: gpio@20 {
239*770aba46SStefano Radaelli		compatible = "nxp,pcal6408";
240*770aba46SStefano Radaelli		reg = <0x20>;
241*770aba46SStefano Radaelli		gpio-controller;
242*770aba46SStefano Radaelli		#gpio-cells = <2>;
243*770aba46SStefano Radaelli		pinctrl-names = "default";
244*770aba46SStefano Radaelli		pinctrl-0 = <&pinctrl_pca6408>;
245*770aba46SStefano Radaelli		interrupt-parent = <&gpio1>;
246*770aba46SStefano Radaelli		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
247*770aba46SStefano Radaelli	};
248*770aba46SStefano Radaelli
249*770aba46SStefano Radaelli	pca6408_2: gpio@21 {
250*770aba46SStefano Radaelli		compatible = "nxp,pcal6408";
251*770aba46SStefano Radaelli		reg = <0x21>;
252*770aba46SStefano Radaelli		gpio-controller;
253*770aba46SStefano Radaelli		#gpio-cells = <2>;
254*770aba46SStefano Radaelli		interrupt-parent = <&gpio1>;
255*770aba46SStefano Radaelli		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
256*770aba46SStefano Radaelli	};
257*770aba46SStefano Radaelli
258*770aba46SStefano Radaelli	st33ktpm2xi2c: tpm@2e {
259*770aba46SStefano Radaelli		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
260*770aba46SStefano Radaelli		reg = <0x2e>;
261*770aba46SStefano Radaelli		label = "tpm";
262*770aba46SStefano Radaelli		reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
263*770aba46SStefano Radaelli	};
264*770aba46SStefano Radaelli};
265*770aba46SStefano Radaelli
266*770aba46SStefano Radaelli&pcie_phy {
267*770aba46SStefano Radaelli	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
268*770aba46SStefano Radaelli	fsl,tx-deemph-gen1 = <0x2d>;
269*770aba46SStefano Radaelli	fsl,tx-deemph-gen2 = <0xf>;
270*770aba46SStefano Radaelli	clocks = <&pcie0_refclk>;
271*770aba46SStefano Radaelli	status = "okay";
272*770aba46SStefano Radaelli};
273*770aba46SStefano Radaelli
274*770aba46SStefano Radaelli&pcie0 {
275*770aba46SStefano Radaelli	reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
276*770aba46SStefano Radaelli	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
277*770aba46SStefano Radaelli		 <&clk IMX8MM_CLK_PCIE1_AUX>;
278*770aba46SStefano Radaelli	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
279*770aba46SStefano Radaelli			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
280*770aba46SStefano Radaelli	assigned-clock-rates = <10000000>, <250000000>;
281*770aba46SStefano Radaelli	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
282*770aba46SStefano Radaelli				 <&clk IMX8MM_SYS_PLL2_250M>;
283*770aba46SStefano Radaelli	status = "okay";
284*770aba46SStefano Radaelli};
285*770aba46SStefano Radaelli
286*770aba46SStefano Radaelli&pwm1 {
287*770aba46SStefano Radaelli	pinctrl-names = "default";
288*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_pwm>;
289*770aba46SStefano Radaelli	status = "okay";
290*770aba46SStefano Radaelli};
291*770aba46SStefano Radaelli
292*770aba46SStefano Radaelli&snvs_pwrkey {
293*770aba46SStefano Radaelli	status = "okay";
294*770aba46SStefano Radaelli};
295*770aba46SStefano Radaelli
296*770aba46SStefano Radaelli&snvs_rtc {
297*770aba46SStefano Radaelli	status = "disabled";
298*770aba46SStefano Radaelli};
299*770aba46SStefano Radaelli
300*770aba46SStefano Radaelli/* Console */
301*770aba46SStefano Radaelli&uart1 {
302*770aba46SStefano Radaelli	pinctrl-names = "default";
303*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_uart1>;
304*770aba46SStefano Radaelli	wakeup-source;
305*770aba46SStefano Radaelli	status = "okay";
306*770aba46SStefano Radaelli};
307*770aba46SStefano Radaelli
308*770aba46SStefano Radaelli/* Header */
309*770aba46SStefano Radaelli&uart2 {
310*770aba46SStefano Radaelli	pinctrl-names = "default";
311*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_uart2>;
312*770aba46SStefano Radaelli	status = "okay";
313*770aba46SStefano Radaelli};
314*770aba46SStefano Radaelli
315*770aba46SStefano Radaelli/* Header */
316*770aba46SStefano Radaelli&uart3 {
317*770aba46SStefano Radaelli	pinctrl-names = "default";
318*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_uart3>;
319*770aba46SStefano Radaelli	status = "okay";
320*770aba46SStefano Radaelli};
321*770aba46SStefano Radaelli
322*770aba46SStefano Radaelli&usbotg1 {
323*770aba46SStefano Radaelli	dr_mode = "otg";
324*770aba46SStefano Radaelli	hnp-disable;
325*770aba46SStefano Radaelli	srp-disable;
326*770aba46SStefano Radaelli	adp-disable;
327*770aba46SStefano Radaelli	usb-role-switch;
328*770aba46SStefano Radaelli	disable-over-current;
329*770aba46SStefano Radaelli	samsung,picophy-pre-emp-curr-control = <3>;
330*770aba46SStefano Radaelli	samsung,picophy-dc-vol-level-adjust = <7>;
331*770aba46SStefano Radaelli	status = "okay";
332*770aba46SStefano Radaelli
333*770aba46SStefano Radaelli	port {
334*770aba46SStefano Radaelli		usb1_drd_sw: endpoint {
335*770aba46SStefano Radaelli			remote-endpoint = <&typec1_dr_sw>;
336*770aba46SStefano Radaelli		};
337*770aba46SStefano Radaelli	};
338*770aba46SStefano Radaelli};
339*770aba46SStefano Radaelli
340*770aba46SStefano Radaelli&usbotg2 {
341*770aba46SStefano Radaelli	dr_mode = "host";
342*770aba46SStefano Radaelli	samsung,picophy-pre-emp-curr-control = <3>;
343*770aba46SStefano Radaelli	samsung,picophy-dc-vol-level-adjust = <7>;
344*770aba46SStefano Radaelli	disable-over-current;
345*770aba46SStefano Radaelli	status = "okay";
346*770aba46SStefano Radaelli};
347*770aba46SStefano Radaelli
348*770aba46SStefano Radaelli/* SD */
349*770aba46SStefano Radaelli&usdhc2 {
350*770aba46SStefano Radaelli	pinctrl-names = "default", "state_100mhz", "state_200mhz";
351*770aba46SStefano Radaelli	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
352*770aba46SStefano Radaelli	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
353*770aba46SStefano Radaelli	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
354*770aba46SStefano Radaelli	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
355*770aba46SStefano Radaelli	bus-width = <4>;
356*770aba46SStefano Radaelli	vmmc-supply = <&reg_usdhc2_vmmc>;
357*770aba46SStefano Radaelli	status = "okay";
358*770aba46SStefano Radaelli};
359*770aba46SStefano Radaelli
360*770aba46SStefano Radaelli&iomuxc {
361*770aba46SStefano Radaelli	pinctrl_can: cangrp {
362*770aba46SStefano Radaelli		fsl,pins = <
363*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x16
364*770aba46SStefano Radaelli			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4			0x16
365*770aba46SStefano Radaelli		>;
366*770aba46SStefano Radaelli	};
367*770aba46SStefano Radaelli
368*770aba46SStefano Radaelli	pinctrl_captouch: captouchgrp {
369*770aba46SStefano Radaelli		fsl,pins = <
370*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16
371*770aba46SStefano Radaelli		>;
372*770aba46SStefano Radaelli	};
373*770aba46SStefano Radaelli
374*770aba46SStefano Radaelli	pinctrl_ecspi1: ecspi1grp {
375*770aba46SStefano Radaelli		fsl,pins = <
376*770aba46SStefano Radaelli			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
377*770aba46SStefano Radaelli			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
378*770aba46SStefano Radaelli			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
379*770aba46SStefano Radaelli			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x13
380*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x13
381*770aba46SStefano Radaelli		>;
382*770aba46SStefano Radaelli	};
383*770aba46SStefano Radaelli
384*770aba46SStefano Radaelli	pinctrl_extcon: extcongrp {
385*770aba46SStefano Radaelli		fsl,pins = <
386*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19
387*770aba46SStefano Radaelli		>;
388*770aba46SStefano Radaelli	};
389*770aba46SStefano Radaelli
390*770aba46SStefano Radaelli	pinctrl_gpio_leds: ledgrp {
391*770aba46SStefano Radaelli		fsl,pins = <
392*770aba46SStefano Radaelli			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x1c6
393*770aba46SStefano Radaelli		>;
394*770aba46SStefano Radaelli	};
395*770aba46SStefano Radaelli
396*770aba46SStefano Radaelli	pinctrl_i2c2: i2c2grp {
397*770aba46SStefano Radaelli		fsl,pins = <
398*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
399*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
400*770aba46SStefano Radaelli		>;
401*770aba46SStefano Radaelli	};
402*770aba46SStefano Radaelli
403*770aba46SStefano Radaelli	pinctrl_i2c2_gpio: i2c2-gpiogrp {
404*770aba46SStefano Radaelli		fsl,pins = <
405*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x400001c3
406*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x400001c3
407*770aba46SStefano Radaelli		>;
408*770aba46SStefano Radaelli	};
409*770aba46SStefano Radaelli
410*770aba46SStefano Radaelli	pinctrl_i2c4: i2c4grp {
411*770aba46SStefano Radaelli		fsl,pins = <
412*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x400001c3
413*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x400001c3
414*770aba46SStefano Radaelli		>;
415*770aba46SStefano Radaelli	};
416*770aba46SStefano Radaelli
417*770aba46SStefano Radaelli	pinctrl_i2c4_gpio: i2c4-gpiogrp {
418*770aba46SStefano Radaelli		fsl,pins = <
419*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x400001c3
420*770aba46SStefano Radaelli			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x400001c3
421*770aba46SStefano Radaelli		>;
422*770aba46SStefano Radaelli	};
423*770aba46SStefano Radaelli
424*770aba46SStefano Radaelli	pinctrl_pca6408: pca6408grp {
425*770aba46SStefano Radaelli		fsl,pins = <
426*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x1c6
427*770aba46SStefano Radaelli		>;
428*770aba46SStefano Radaelli	};
429*770aba46SStefano Radaelli
430*770aba46SStefano Radaelli	pinctrl_pwm: pwmgrp {
431*770aba46SStefano Radaelli		fsl,pins = <
432*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x06
433*770aba46SStefano Radaelli		>;
434*770aba46SStefano Radaelli	};
435*770aba46SStefano Radaelli
436*770aba46SStefano Radaelli	pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp {
437*770aba46SStefano Radaelli		fsl,pins = <
438*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0xc1
439*770aba46SStefano Radaelli		>;
440*770aba46SStefano Radaelli	};
441*770aba46SStefano Radaelli
442*770aba46SStefano Radaelli	pinctrl_restouch: restouchgrp {
443*770aba46SStefano Radaelli		fsl,pins = <
444*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x1c0
445*770aba46SStefano Radaelli		>;
446*770aba46SStefano Radaelli	};
447*770aba46SStefano Radaelli
448*770aba46SStefano Radaelli	pinctrl_rtc: rtcgrp {
449*770aba46SStefano Radaelli		fsl,pins = <
450*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x1c1
451*770aba46SStefano Radaelli		>;
452*770aba46SStefano Radaelli	};
453*770aba46SStefano Radaelli
454*770aba46SStefano Radaelli	pinctrl_uart1: uart1grp {
455*770aba46SStefano Radaelli		fsl,pins = <
456*770aba46SStefano Radaelli			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x140
457*770aba46SStefano Radaelli			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x140
458*770aba46SStefano Radaelli		>;
459*770aba46SStefano Radaelli	};
460*770aba46SStefano Radaelli
461*770aba46SStefano Radaelli	pinctrl_uart2: uart2grp {
462*770aba46SStefano Radaelli		fsl,pins = <
463*770aba46SStefano Radaelli			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140
464*770aba46SStefano Radaelli			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140
465*770aba46SStefano Radaelli		>;
466*770aba46SStefano Radaelli	};
467*770aba46SStefano Radaelli
468*770aba46SStefano Radaelli	pinctrl_uart3: uart3grp {
469*770aba46SStefano Radaelli		fsl,pins = <
470*770aba46SStefano Radaelli			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140
471*770aba46SStefano Radaelli			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140
472*770aba46SStefano Radaelli		>;
473*770aba46SStefano Radaelli	};
474*770aba46SStefano Radaelli
475*770aba46SStefano Radaelli	pinctrl_usdhc2: usdhc2grp {
476*770aba46SStefano Radaelli		fsl,pins = <
477*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190
478*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
479*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
480*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
481*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
482*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
483*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
484*770aba46SStefano Radaelli		>;
485*770aba46SStefano Radaelli	};
486*770aba46SStefano Radaelli
487*770aba46SStefano Radaelli	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
488*770aba46SStefano Radaelli		fsl,pins = <
489*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
490*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
491*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
492*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
493*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
494*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
495*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
496*770aba46SStefano Radaelli		>;
497*770aba46SStefano Radaelli	};
498*770aba46SStefano Radaelli
499*770aba46SStefano Radaelli	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
500*770aba46SStefano Radaelli		fsl,pins = <
501*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
502*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
503*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
504*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
505*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
506*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
507*770aba46SStefano Radaelli			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
508*770aba46SStefano Radaelli		>;
509*770aba46SStefano Radaelli	};
510*770aba46SStefano Radaelli
511*770aba46SStefano Radaelli	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
512*770aba46SStefano Radaelli		fsl,pins = <
513*770aba46SStefano Radaelli			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0xc1
514*770aba46SStefano Radaelli		>;
515*770aba46SStefano Radaelli	};
516*770aba46SStefano Radaelli};
517