xref: /linux/scripts/dtc/include-prefixes/arm64/freescale/imx8dxl-sr-som.dtsi (revision b2128290c29902315e632ea59e0504d6bc9e9b42)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
 */

#include "imx8dxl.dtsi"
/ {
	compatible = "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
	model = "SolidRun i.MX8DXL SoM";

	aliases {
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &lpuart0;
		serial2 = &lpuart2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	imx8dxl-cm4 {
		compatible = "fsl,imx8qxp-cm4";
		clocks = <&clk_dummy>;
		mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
		mbox-names = "tx", "rx", "rxdb";
		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
				<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
		power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
		fsl,entry-address = <0x34fe0000>;
		fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
	};

	pps {
		compatible = "pps-gpio";
		gpios = <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>;
		pinctrl-0 = <&gnss_pps_pins>;
		pinctrl-names = "default";
	};

	v_1_2: regulator-1-2 {
		compatible = "regulator-fixed";
		regulator-name = "1v2";
		pinctrl-0 = <&regulator_1_2_pins>;
		pinctrl-names = "default";
		regulator-max-microvolt = <1200000>;
		regulator-min-microvolt = <1200000>;
		gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	v_1_6: regulator-1-6 {
		compatible = "regulator-fixed";
		regulator-name = "1v6";
		pinctrl-0 = <&regulator_1_6_pins>;
		pinctrl-names = "default";
		regulator-max-microvolt = <1600000>;
		regulator-min-microvolt = <1600000>;
		vin-supply = <&v_1_8>;
		gpio = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	v_1_8: regulator-1-8 {
		compatible = "regulator-fixed";
		regulator-name = "1v8";
		regulator-max-microvolt = <1800000>;
		regulator-min-microvolt = <1800000>;
	};

	v_1_8_se: regulator-1-8-secure-element {
		compatible = "regulator-fixed";
		regulator-name = "1v8-se";
		pinctrl-0 = <&regulator_1_8_se_pins>;
		pinctrl-names = "default";
		regulator-max-microvolt = <1800000>;
		regulator-min-microvolt = <1800000>;
		vin-supply = <&v_1_8>;
		gpio = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	v_3_3: regulator-3-3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3";
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
	};

	reserved-memory {
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x98000000 0 0x14000000>;
			reusable;
			size = <0 0x14000000>;
			linux,cma-default;
		};

		vdev0vring0: memory0@90000000 {
			reg = <0 0x90000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: memory@90008000 {
			reg = <0 0x90008000 0 0x8000>;
			no-map;
		};

		vdev1vring0: memory@90010000 {
			reg = <0 0x90010000 0 0x8000>;
			no-map;
		};

		vdev1vring1: memory@90018000 {
			reg = <0 0x90018000 0 0x8000>;
			no-map;
		};

		rsc_table: memory-rsc-table@900ff000 {
			reg = <0 0x900ff000 0 0x1000>;
			no-map;
		};

		vdevbuffer: memory-vdevbuffer@90400000 {
			compatible = "shared-dma-pool";
			reg = <0 0x90400000 0 0x100000>;
			no-map;
		};

		/*
		 * Memory reserved for optee usage. Please do not use.
		 * This will be automatically added to dtb if OP-TEE is installed.
		 * optee@96000000 {
		 *     reg = <0 0x96000000 0 0x2000000>;
		 *     no-map;
		 * };
		 */
	};

	memory@80000000 {
		reg = <0x00000000 0x80000000 0 0x40000000>;
		device_type = "memory";
	};
};

&i2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-1 = <&i2c2_gpio_pins>;
	pinctrl-names = "default", "gpio";
	scl-gpios = <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-1 = <&i2c3_gpio_pins>;
	pinctrl-names = "default", "gpio";
	scl-gpios = <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	magnetometer@1e {
		compatible = "st,iis2mdc";
		reg = <0x1e>;
		interrupt-parent = <&lsio_gpio2>;
		interrupts = <10 IRQ_TYPE_EDGE_RISING>;
		pinctrl-0 = <&magnetometer_pins>;
		pinctrl-names = "default";
		st,drdy-int-pin = <1>;
	};

	/* pressure-sensor@5c */

	inertial-sensor@6b {
		compatible = "st,ism330dhcx";
		reg = <0x6b>;
		interrupt-parent = <&lsio_gpio2>;
		interrupts = <11 IRQ_TYPE_EDGE_RISING>;
		pinctrl-0 = <&imu_pins>;
		pinctrl-names = "default";
		st,drdy-int-pin = <1>;
	};
};

&iomuxc {
	pinctrl-0 = <&pinctrl_hog>;
	pinctrl-names = "default";

	pinctrl_hog: hoggrp {
		fsl,pins = <
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
		>;
	};

	dsrc_pins: pinctrl-dsrc-grp {
		fsl,pins = <
			/* reset: io without pull */
			IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10			0x0000060

			/*
			 * boot0: io without pull
			 * After reset, this pin selects radio boot media:
			 * - 0: flash spi
			 * - 1: slave sdio
			 * Once the firmware boots however, the radio controls
			 * this pin for flow-control to signal readiness.
			 */
			IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09			0x0000060
		>;
	};

	gnss_pins: pinctrl-gnss-grp {
		fsl,pins = <
			/* gps reset: input with pull-up */
			IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN	0x0000021
			/* gps interrupt: io without pull-up */
			IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN	0x0000061
		>;
	};

	gnss_pps_pins: pinctrl-gnss-pps-grp {
		fsl,pins = <
			/* gps timepulse: input without pull-up */
			IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN	0x0000061
		>;
	};

	i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
		fsl,pins = <
			/* io with pull-up and weak drive */
			IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00		0x00000021
			/* io with pull-up, weak drive, open-drain */
			IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01		0x02000021
		>;
	};

	i2c2_pins: pinctrl-i2c2-grp {
		fsl,pins = <
			/* io with pull-up and weak drive */
			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA			0x06000021
			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL			0x06000021
		>;
	};

	i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
		fsl,pins = <
			/* io with pull-up and weak drive */
			IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03		0x00000021
			/* io with pull-up, weak drive, open-drain */
			IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02		0x02000021
		>;
	};

	i2c3_pins: pinctrl-i2c3-grp {
		fsl,pins = <
			/* io with pull-up and weak drive */
			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA			0x06000021
			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL			0x06000021
		>;
	};

	imu_pins: pinctrl-imu-grp {
		fsl,pins = <
			/* interrupt: io with pull-down */
			IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN	0x0000041
		>;
	};

	lpspi2_pins: pinctrl-lpspi2-grp {
		fsl,pins = <
			IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK		0x600004c
			IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO		0x600004c
			IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI			0x600004c
			IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22		0x6000021
		>;
	};

	lpuart0_pins: pinctrl-lpuart0-grp {
		fsl,pins = <
			IMX8DXL_UART0_RX_ADMA_UART0_RX			0x06000020
			IMX8DXL_UART0_TX_ADMA_UART0_TX			0x06000020
		>;
	};

	lpuart2_pins: pinctrl-lpuart2-grp {
		fsl,pins = <
			IMX8DXL_UART2_TX_ADMA_UART2_TX			0x06000020
			IMX8DXL_UART2_RX_ADMA_UART2_RX			0x06000020
		>;
	};

	magnetometer_pins: pinctrl-magnetometer-grp {
		fsl,pins = <
			/* interrupt: io with pull-down */
			IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN	0x0000041
		>;
	};

	regulator_1_2_pins: pinctrl-regulator-1-2-grp {
		fsl,pins = <
			/* io without pull-up */
			/* has etxernal pull-down */
			IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13			0x0000061
		>;
	};

	regulator_1_6_pins: pinctrl-regulator-1-6-grp {
		fsl,pins = <
			/* io without pull-up */
			/* has etxernal pull-down */
			IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14			0x0000061
		>;
	};

	regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp {
		fsl,pins = <
			/* v2x-secure-element power switch: io with pull-down */
			IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x0000041
		>;
	};

	se_pins: pinctrl-secure-element-grp {
		fsl,pins = <
			/* v2x-secure-element reset: io with pull-up */
			IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x0000021

			/*
			 * v2x-secure-element gpio0: io with pull-up
			 * pulled low by sxf after boot indicating ready for commands
			 */
			IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x0000021

			/* v2x-secure-element gpio1: io with pull-up */
			IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x0000021
		>;
	};

	usdhc1_pins: pinctrl-usdhc1-grp {
		fsl,pins = <
			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0		0x00000021
			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1		0x00000021
			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2		0x00000021
			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3		0x00000021
			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4		0x00000021
			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5		0x00000021
			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6		0x00000021
			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7		0x00000021
			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE		0x00000041
			IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000061
		>;
	};

	usdhc2_pins: pinctrl-usdhc2-grp {
		fsl,pins = <
			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000040
			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
		>;
	};
};

&lpspi2 {
	cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
	num-cs = <1>;
	pinctrl-0 = <&lpspi2_pins>, <&se_pins>;
	pinctrl-names = "default";
	status = "okay";
};

/* console */
&lpuart0 {
	pinctrl-0 = <&lpuart0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

/* gnss */
&lpuart2 {
	pinctrl-0 = <&lpuart2_pins>, <&gnss_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&lsio_gpio3 {
	gpio-line-names = "", "", "", "", "", "", "", "",
			  "", "", "", "", "", "", "", "",
			  "", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "",
			  "", "", "", "", "", "", "", "";
};

&lsio_mu5 {
	status = "okay";
};

/* OTG port for boot */
&usbotg1 {
	adp-disable;
	disable-over-current;
	dr_mode = "peripheral";
	hnp-disable;
	power-active-high;
	srp-disable;
	status = "okay";
};

&usbphy1 {
	status = "okay";
};

/* eMMC */
&usdhc1 {
	bus-width = <8>;
	cap-mmc-hw-reset;
	non-removable;
	no-sd;
	no-sdio;
	pinctrl-0 = <&usdhc1_pins>;
	pinctrl-1 = <&usdhc1_pins>;
	pinctrl-2 = <&usdhc1_pins>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	vmmc-supply = <&v_3_3>;
	vqmmc-supply = <&v_1_8>;
	status = "okay";
};

/* DSRC Radio */
&usdhc2 {
	bus-width = <4>;
	keep-power-in-suspend;
	max-frequency = <40000000>;
	non-removable;
	no-sd;
	pinctrl-0 = <&usdhc2_pins>, <&dsrc_pins>;
	pinctrl-names = "default";
	vmmc-supply = <&v_3_3>;
	vqmmc-supply = <&v_1_8>;
	status = "okay";
};