xref: /linux/scripts/dtc/include-prefixes/arm64/freescale/fsl-lx2162a-serdes.dtsi (revision 67f8bc848ee31831336bd478e57d2f993551902e)

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2162A
// SoC
//
// Copyright 2026 NXP

&soc {
	serdes_1: phy@1ea0000 {
		compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
		reg = <0x0 0x1ea0000 0x0 0x1e30>;
		#address-cells = <1>;
		#size-cells = <0>;
		#phy-cells = <1>;
		status = "disabled";

		serdes_1_lane_e: phy@4 {
			reg = <4>;
			#phy-cells = <0>;
		};

		serdes_1_lane_f: phy@5 {
			reg = <5>;
			#phy-cells = <0>;
		};

		serdes_1_lane_g: phy@6 {
			reg = <6>;
			#phy-cells = <0>;
		};

		serdes_1_lane_h: phy@7 {
			reg = <7>;
			#phy-cells = <0>;
		};
	};

	serdes_2: phy@1eb0000 {
		compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
		reg = <0x0 0x1eb0000 0x0 0x1e30>;
		#address-cells = <1>;
		#size-cells = <0>;
		#phy-cells = <1>;
		status = "disabled";

		serdes_2_lane_a: phy@0 {
			reg = <0>;
			#phy-cells = <0>;
		};

		serdes_2_lane_b: phy@1 {
			reg = <1>;
			#phy-cells = <0>;
		};

		serdes_2_lane_c: phy@2 {
			reg = <2>;
			#phy-cells = <0>;
		};

		serdes_2_lane_d: phy@3 {
			reg = <3>;
			#phy-cells = <0>;
		};

		serdes_2_lane_e: phy@4 {
			reg = <4>;
			#phy-cells = <0>;
		};

		serdes_2_lane_f: phy@5 {
			reg = <5>;
			#phy-cells = <0>;
		};

		serdes_2_lane_g: phy@6 {
			reg = <6>;
			#phy-cells = <0>;
		};

		serdes_2_lane_h: phy@7 {
			reg = <7>;
			#phy-cells = <0>;
		};
	};
};