xref: /linux/scripts/dtc/include-prefixes/arm64/exynos/exynosautov920.dtsi (revision 115e74a29b530d121891238e9551c4bcdf7b04b5)
1c96dab19SJaewon Kim// SPDX-License-Identifier: GPL-2.0
2c96dab19SJaewon Kim/*
3c96dab19SJaewon Kim * Samsung's ExynosAutov920 SoC device tree source
4c96dab19SJaewon Kim *
5c96dab19SJaewon Kim * Copyright (c) 2023 Samsung Electronics Co., Ltd.
6c96dab19SJaewon Kim *
7c96dab19SJaewon Kim */
8c96dab19SJaewon Kim
94d060009SSunyeal Hong#include <dt-bindings/clock/samsung,exynosautov920.h>
10c96dab19SJaewon Kim#include <dt-bindings/interrupt-controller/arm-gic.h>
11c96dab19SJaewon Kim#include <dt-bindings/soc/samsung,exynos-usi.h>
12c96dab19SJaewon Kim
13c96dab19SJaewon Kim/ {
14c96dab19SJaewon Kim	compatible = "samsung,exynosautov920";
15c96dab19SJaewon Kim	#address-cells = <2>;
16c96dab19SJaewon Kim	#size-cells = <1>;
17c96dab19SJaewon Kim
18c96dab19SJaewon Kim	interrupt-parent = <&gic>;
19c96dab19SJaewon Kim
20c96dab19SJaewon Kim	aliases {
21c96dab19SJaewon Kim		pinctrl0 = &pinctrl_alive;
22c96dab19SJaewon Kim		pinctrl1 = &pinctrl_aud;
23c96dab19SJaewon Kim		pinctrl2 = &pinctrl_hsi0;
24c96dab19SJaewon Kim		pinctrl3 = &pinctrl_hsi1;
25c96dab19SJaewon Kim		pinctrl4 = &pinctrl_hsi2;
26c96dab19SJaewon Kim		pinctrl5 = &pinctrl_hsi2ufs;
27c96dab19SJaewon Kim		pinctrl6 = &pinctrl_peric0;
28c96dab19SJaewon Kim		pinctrl7 = &pinctrl_peric1;
29c96dab19SJaewon Kim	};
30c96dab19SJaewon Kim
31c96dab19SJaewon Kim	arm-pmu {
32c96dab19SJaewon Kim		compatible = "arm,cortex-a78-pmu";
33c96dab19SJaewon Kim		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
34c96dab19SJaewon Kim	};
35c96dab19SJaewon Kim
36c96dab19SJaewon Kim	xtcxo: clock {
37c96dab19SJaewon Kim		compatible = "fixed-clock";
38c96dab19SJaewon Kim		#clock-cells = <0>;
39c96dab19SJaewon Kim		clock-output-names = "oscclk";
40c96dab19SJaewon Kim	};
41c96dab19SJaewon Kim
42c96dab19SJaewon Kim	cpus: cpus {
43c96dab19SJaewon Kim		#address-cells = <2>;
44c96dab19SJaewon Kim		#size-cells = <0>;
45c96dab19SJaewon Kim
46c96dab19SJaewon Kim		cpu-map {
47c96dab19SJaewon Kim			cluster0 {
48c96dab19SJaewon Kim				core0 {
49c96dab19SJaewon Kim					cpu = <&cpu0>;
50c96dab19SJaewon Kim				};
51c96dab19SJaewon Kim				core1 {
52c96dab19SJaewon Kim					cpu = <&cpu1>;
53c96dab19SJaewon Kim				};
54c96dab19SJaewon Kim				core2 {
55c96dab19SJaewon Kim					cpu = <&cpu2>;
56c96dab19SJaewon Kim				};
57c96dab19SJaewon Kim				core3 {
58c96dab19SJaewon Kim					cpu = <&cpu3>;
59c96dab19SJaewon Kim				};
60c96dab19SJaewon Kim			};
61c96dab19SJaewon Kim
62c96dab19SJaewon Kim			cluster1 {
63c96dab19SJaewon Kim				core0 {
64c96dab19SJaewon Kim					cpu = <&cpu4>;
65c96dab19SJaewon Kim				};
66c96dab19SJaewon Kim				core1 {
67c96dab19SJaewon Kim					cpu = <&cpu5>;
68c96dab19SJaewon Kim				};
69c96dab19SJaewon Kim				core2 {
70c96dab19SJaewon Kim					cpu = <&cpu6>;
71c96dab19SJaewon Kim				};
72c96dab19SJaewon Kim				core3 {
73c96dab19SJaewon Kim					cpu = <&cpu7>;
74c96dab19SJaewon Kim				};
75c96dab19SJaewon Kim			};
76c96dab19SJaewon Kim
77c96dab19SJaewon Kim			cluster2 {
78c96dab19SJaewon Kim				core0 {
79c96dab19SJaewon Kim					cpu = <&cpu8>;
80c96dab19SJaewon Kim				};
81c96dab19SJaewon Kim				core1 {
82c96dab19SJaewon Kim					cpu = <&cpu9>;
83c96dab19SJaewon Kim				};
84c96dab19SJaewon Kim			};
85c96dab19SJaewon Kim		};
86c96dab19SJaewon Kim
87c96dab19SJaewon Kim		cpu0: cpu@0 {
88c96dab19SJaewon Kim			device_type = "cpu";
89c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
90c96dab19SJaewon Kim			reg = <0x0 0x0>;
91c96dab19SJaewon Kim			enable-method = "psci";
92bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
93bbfc70caSDevang Tailor			i-cache-line-size = <64>;
94bbfc70caSDevang Tailor			i-cache-sets = <256>;
95bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
96bbfc70caSDevang Tailor			d-cache-line-size = <64>;
97bbfc70caSDevang Tailor			d-cache-sets = <256>;
98bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl0>;
99c96dab19SJaewon Kim		};
100c96dab19SJaewon Kim
101c96dab19SJaewon Kim		cpu1: cpu@100 {
102c96dab19SJaewon Kim			device_type = "cpu";
103c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
104c96dab19SJaewon Kim			reg = <0x0 0x100>;
105c96dab19SJaewon Kim			enable-method = "psci";
106bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
107bbfc70caSDevang Tailor			i-cache-line-size = <64>;
108bbfc70caSDevang Tailor			i-cache-sets = <256>;
109bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
110bbfc70caSDevang Tailor			d-cache-line-size = <64>;
111bbfc70caSDevang Tailor			d-cache-sets = <256>;
112bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl0>;
113c96dab19SJaewon Kim		};
114c96dab19SJaewon Kim
115c96dab19SJaewon Kim		cpu2: cpu@200 {
116c96dab19SJaewon Kim			device_type = "cpu";
117c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
118c96dab19SJaewon Kim			reg = <0x0 0x200>;
119c96dab19SJaewon Kim			enable-method = "psci";
120bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
121bbfc70caSDevang Tailor			i-cache-line-size = <64>;
122bbfc70caSDevang Tailor			i-cache-sets = <256>;
123bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
124bbfc70caSDevang Tailor			d-cache-line-size = <64>;
125bbfc70caSDevang Tailor			d-cache-sets = <256>;
126bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl0>;
127c96dab19SJaewon Kim		};
128c96dab19SJaewon Kim
129c96dab19SJaewon Kim		cpu3: cpu@300 {
130c96dab19SJaewon Kim			device_type = "cpu";
131c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
132c96dab19SJaewon Kim			reg = <0x0 0x300>;
133c96dab19SJaewon Kim			enable-method = "psci";
134bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
135bbfc70caSDevang Tailor			i-cache-line-size = <64>;
136bbfc70caSDevang Tailor			i-cache-sets = <256>;
137bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
138bbfc70caSDevang Tailor			d-cache-line-size = <64>;
139bbfc70caSDevang Tailor			d-cache-sets = <256>;
140bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl0>;
141c96dab19SJaewon Kim		};
142c96dab19SJaewon Kim
143c96dab19SJaewon Kim		cpu4: cpu@10000 {
144c96dab19SJaewon Kim			device_type = "cpu";
145c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
146c96dab19SJaewon Kim			reg = <0x0 0x10000>;
147c96dab19SJaewon Kim			enable-method = "psci";
148bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
149bbfc70caSDevang Tailor			i-cache-line-size = <64>;
150bbfc70caSDevang Tailor			i-cache-sets = <256>;
151bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
152bbfc70caSDevang Tailor			d-cache-line-size = <64>;
153bbfc70caSDevang Tailor			d-cache-sets = <256>;
154bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl1>;
155c96dab19SJaewon Kim		};
156c96dab19SJaewon Kim
157c96dab19SJaewon Kim		cpu5: cpu@10100 {
158c96dab19SJaewon Kim			device_type = "cpu";
159c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
160c96dab19SJaewon Kim			reg = <0x0 0x10100>;
161c96dab19SJaewon Kim			enable-method = "psci";
162bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
163bbfc70caSDevang Tailor			i-cache-line-size = <64>;
164bbfc70caSDevang Tailor			i-cache-sets = <256>;
165bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
166bbfc70caSDevang Tailor			d-cache-line-size = <64>;
167bbfc70caSDevang Tailor			d-cache-sets = <256>;
168bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl1>;
169c96dab19SJaewon Kim		};
170c96dab19SJaewon Kim
171c96dab19SJaewon Kim		cpu6: cpu@10200 {
172c96dab19SJaewon Kim			device_type = "cpu";
173c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
174c96dab19SJaewon Kim			reg = <0x0 0x10200>;
175c96dab19SJaewon Kim			enable-method = "psci";
176bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
177bbfc70caSDevang Tailor			i-cache-line-size = <64>;
178bbfc70caSDevang Tailor			i-cache-sets = <256>;
179bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
180bbfc70caSDevang Tailor			d-cache-line-size = <64>;
181bbfc70caSDevang Tailor			d-cache-sets = <256>;
182bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl1>;
183c96dab19SJaewon Kim		};
184c96dab19SJaewon Kim
185c96dab19SJaewon Kim		cpu7: cpu@10300 {
186c96dab19SJaewon Kim			device_type = "cpu";
187c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
188c96dab19SJaewon Kim			reg = <0x0 0x10300>;
189c96dab19SJaewon Kim			enable-method = "psci";
190bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
191bbfc70caSDevang Tailor			i-cache-line-size = <64>;
192bbfc70caSDevang Tailor			i-cache-sets = <256>;
193bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
194bbfc70caSDevang Tailor			d-cache-line-size = <64>;
195bbfc70caSDevang Tailor			d-cache-sets = <256>;
196bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl1>;
197c96dab19SJaewon Kim		};
198c96dab19SJaewon Kim
199c96dab19SJaewon Kim		cpu8: cpu@20000 {
200c96dab19SJaewon Kim			device_type = "cpu";
201c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
202c96dab19SJaewon Kim			reg = <0x0 0x20000>;
203c96dab19SJaewon Kim			enable-method = "psci";
204bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
205bbfc70caSDevang Tailor			i-cache-line-size = <64>;
206bbfc70caSDevang Tailor			i-cache-sets = <256>;
207bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
208bbfc70caSDevang Tailor			d-cache-line-size = <64>;
209bbfc70caSDevang Tailor			d-cache-sets = <256>;
210bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl2>;
211c96dab19SJaewon Kim		};
212c96dab19SJaewon Kim
213c96dab19SJaewon Kim		cpu9: cpu@20100 {
214c96dab19SJaewon Kim			device_type = "cpu";
215c96dab19SJaewon Kim			compatible = "arm,cortex-a78ae";
216c96dab19SJaewon Kim			reg = <0x0 0x20100>;
217c96dab19SJaewon Kim			enable-method = "psci";
218bbfc70caSDevang Tailor			i-cache-size = <0x10000>;
219bbfc70caSDevang Tailor			i-cache-line-size = <64>;
220bbfc70caSDevang Tailor			i-cache-sets = <256>;
221bbfc70caSDevang Tailor			d-cache-size = <0x10000>;
222bbfc70caSDevang Tailor			d-cache-line-size = <64>;
223bbfc70caSDevang Tailor			d-cache-sets = <256>;
224bbfc70caSDevang Tailor			next-level-cache = <&l2_cache_cl2>;
225bbfc70caSDevang Tailor		};
226bbfc70caSDevang Tailor
227bbfc70caSDevang Tailor		l2_cache_cl0: l2-cache0 {
228bbfc70caSDevang Tailor			compatible = "cache";
229bbfc70caSDevang Tailor			cache-level = <2>;
230bbfc70caSDevang Tailor			cache-unified;
231bbfc70caSDevang Tailor			cache-size = <0x40000>;
232bbfc70caSDevang Tailor			cache-line-size = <64>;
233bbfc70caSDevang Tailor			cache-sets = <512>;
234bbfc70caSDevang Tailor			next-level-cache = <&l3_cache_cl0>;
235bbfc70caSDevang Tailor		};
236bbfc70caSDevang Tailor
237bbfc70caSDevang Tailor		l2_cache_cl1: l2-cache1 {
238bbfc70caSDevang Tailor			compatible = "cache";
239bbfc70caSDevang Tailor			cache-level = <2>;
240bbfc70caSDevang Tailor			cache-unified;
241bbfc70caSDevang Tailor			cache-size = <0x40000>;
242bbfc70caSDevang Tailor			cache-line-size = <64>;
243bbfc70caSDevang Tailor			cache-sets = <512>;
244bbfc70caSDevang Tailor			next-level-cache = <&l3_cache_cl1>;
245bbfc70caSDevang Tailor		};
246bbfc70caSDevang Tailor
247bbfc70caSDevang Tailor		l2_cache_cl2: l2-cache2 {
248bbfc70caSDevang Tailor			compatible = "cache";
249bbfc70caSDevang Tailor			cache-level = <2>;
250bbfc70caSDevang Tailor			cache-unified;
251bbfc70caSDevang Tailor			cache-size = <0x40000>;
252bbfc70caSDevang Tailor			cache-line-size = <64>;
253bbfc70caSDevang Tailor			cache-sets = <512>;
254bbfc70caSDevang Tailor			next-level-cache = <&l3_cache_cl2>;
255bbfc70caSDevang Tailor		};
256bbfc70caSDevang Tailor
257bbfc70caSDevang Tailor		l3_cache_cl0: l3-cache0 {
258bbfc70caSDevang Tailor			compatible = "cache";
259bbfc70caSDevang Tailor			cache-level = <3>;
260bbfc70caSDevang Tailor			cache-unified;
261bbfc70caSDevang Tailor			cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */
262bbfc70caSDevang Tailor			cache-line-size = <64>;
263bbfc70caSDevang Tailor			cache-sets = <2048>;
264bbfc70caSDevang Tailor		};
265bbfc70caSDevang Tailor
266bbfc70caSDevang Tailor		l3_cache_cl1: l3-cache1 {
267bbfc70caSDevang Tailor			compatible = "cache";
268bbfc70caSDevang Tailor			cache-level = <3>;
269bbfc70caSDevang Tailor			cache-unified;
270bbfc70caSDevang Tailor			cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */
271bbfc70caSDevang Tailor			cache-line-size = <64>;
272bbfc70caSDevang Tailor			cache-sets = <2048>;
273bbfc70caSDevang Tailor		};
274bbfc70caSDevang Tailor
275bbfc70caSDevang Tailor		l3_cache_cl2: l3-cache2 {
276bbfc70caSDevang Tailor			compatible = "cache";
277bbfc70caSDevang Tailor			cache-level = <3>;
278bbfc70caSDevang Tailor			cache-unified;
279bbfc70caSDevang Tailor			cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */
280bbfc70caSDevang Tailor			cache-line-size = <64>;
281bbfc70caSDevang Tailor			cache-sets = <1365>;
282c96dab19SJaewon Kim		};
283c96dab19SJaewon Kim	};
284c96dab19SJaewon Kim
285c96dab19SJaewon Kim	psci {
286c96dab19SJaewon Kim		compatible = "arm,psci-1.0";
287c96dab19SJaewon Kim		method = "smc";
288c96dab19SJaewon Kim	};
289c96dab19SJaewon Kim
290c96dab19SJaewon Kim	soc: soc@0 {
291c96dab19SJaewon Kim		compatible = "simple-bus";
292c96dab19SJaewon Kim		#address-cells = <1>;
293c96dab19SJaewon Kim		#size-cells = <1>;
294c96dab19SJaewon Kim		ranges = <0x0 0x0 0x0 0x20000000>;
295c96dab19SJaewon Kim
296c96dab19SJaewon Kim		chipid@10000000 {
297c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-chipid",
298c96dab19SJaewon Kim				     "samsung,exynos850-chipid";
299c96dab19SJaewon Kim			reg = <0x10000000 0x24>;
300c96dab19SJaewon Kim		};
301c96dab19SJaewon Kim
302ef1c2a54SSunyeal Hong		cmu_misc: clock-controller@10020000 {
303ef1c2a54SSunyeal Hong			compatible = "samsung,exynosautov920-cmu-misc";
304ef1c2a54SSunyeal Hong			reg = <0x10020000 0x8000>;
305ef1c2a54SSunyeal Hong			#clock-cells = <1>;
306ef1c2a54SSunyeal Hong
307ef1c2a54SSunyeal Hong			clocks = <&xtcxo>,
308ef1c2a54SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_MISC_NOC>;
309ef1c2a54SSunyeal Hong			clock-names = "oscclk",
310ef1c2a54SSunyeal Hong				      "noc";
311ef1c2a54SSunyeal Hong		};
312ef1c2a54SSunyeal Hong
31341979b81SByoungtae Cho		watchdog_cl0: watchdog@10060000 {
31441979b81SByoungtae Cho			compatible = "samsung,exynosautov920-wdt";
31541979b81SByoungtae Cho			reg = <0x10060000 0x100>;
31641979b81SByoungtae Cho			interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>;
31741979b81SByoungtae Cho			clocks = <&xtcxo>, <&xtcxo>;
31841979b81SByoungtae Cho			clock-names = "watchdog", "watchdog_src";
31941979b81SByoungtae Cho			samsung,syscon-phandle = <&pmu_system_controller>;
32041979b81SByoungtae Cho			samsung,cluster-index = <0>;
32141979b81SByoungtae Cho		};
32241979b81SByoungtae Cho
32341979b81SByoungtae Cho		watchdog_cl1: watchdog@10070000 {
32441979b81SByoungtae Cho			compatible = "samsung,exynosautov920-wdt";
32541979b81SByoungtae Cho			reg = <0x10070000 0x100>;
32641979b81SByoungtae Cho			interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>;
32741979b81SByoungtae Cho			clocks = <&xtcxo>, <&xtcxo>;
32841979b81SByoungtae Cho			clock-names = "watchdog", "watchdog_src";
32941979b81SByoungtae Cho			samsung,syscon-phandle = <&pmu_system_controller>;
33041979b81SByoungtae Cho			samsung,cluster-index = <1>;
33141979b81SByoungtae Cho		};
33241979b81SByoungtae Cho
333c96dab19SJaewon Kim		gic: interrupt-controller@10400000 {
334c96dab19SJaewon Kim			compatible = "arm,gic-v3";
335c96dab19SJaewon Kim			#interrupt-cells = <3>;
336c96dab19SJaewon Kim			#address-cells = <0>;
337c96dab19SJaewon Kim			interrupt-controller;
338c96dab19SJaewon Kim			reg = <0x10400000 0x10000>,
339c96dab19SJaewon Kim			      <0x10460000 0x140000>;
340c96dab19SJaewon Kim			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
341c96dab19SJaewon Kim		};
342c96dab19SJaewon Kim
343de7a4e01SFaraz Ata		spdma0: dma-controller@10180000 {
344de7a4e01SFaraz Ata			compatible = "arm,pl330", "arm,primecell";
345de7a4e01SFaraz Ata			reg = <0x10180000 0x1000>;
346de7a4e01SFaraz Ata			interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>;
347de7a4e01SFaraz Ata			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
348de7a4e01SFaraz Ata			clock-names = "apb_pclk";
349de7a4e01SFaraz Ata			#dma-cells = <1>;
350de7a4e01SFaraz Ata		};
351de7a4e01SFaraz Ata
352de7a4e01SFaraz Ata		spdma1: dma-controller@10190000 {
353de7a4e01SFaraz Ata			compatible = "arm,pl330", "arm,primecell";
354de7a4e01SFaraz Ata			reg = <0x10190000 0x1000>;
355de7a4e01SFaraz Ata			interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>;
356de7a4e01SFaraz Ata			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
357de7a4e01SFaraz Ata			clock-names = "apb_pclk";
358de7a4e01SFaraz Ata			#dma-cells = <1>;
359de7a4e01SFaraz Ata		};
360de7a4e01SFaraz Ata
361de7a4e01SFaraz Ata		pdma0: dma-controller@101a0000 {
362de7a4e01SFaraz Ata			compatible = "arm,pl330", "arm,primecell";
363de7a4e01SFaraz Ata			reg = <0x101a0000 0x1000>;
364de7a4e01SFaraz Ata			interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>;
365de7a4e01SFaraz Ata			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
366de7a4e01SFaraz Ata			clock-names = "apb_pclk";
367de7a4e01SFaraz Ata			#dma-cells = <1>;
368de7a4e01SFaraz Ata		};
369de7a4e01SFaraz Ata
370de7a4e01SFaraz Ata		pdma1: dma-controller@101b0000 {
371de7a4e01SFaraz Ata			compatible = "arm,pl330", "arm,primecell";
372de7a4e01SFaraz Ata			reg = <0x101b0000 0x1000>;
373de7a4e01SFaraz Ata			interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>;
374de7a4e01SFaraz Ata			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
375de7a4e01SFaraz Ata			clock-names = "apb_pclk";
376de7a4e01SFaraz Ata			#dma-cells = <1>;
377de7a4e01SFaraz Ata		};
378de7a4e01SFaraz Ata
379de7a4e01SFaraz Ata		pdma2: dma-controller@101c0000 {
380de7a4e01SFaraz Ata			compatible = "arm,pl330", "arm,primecell";
381de7a4e01SFaraz Ata			reg = <0x101c0000 0x1000>;
382de7a4e01SFaraz Ata			interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>;
383de7a4e01SFaraz Ata			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
384de7a4e01SFaraz Ata			clock-names = "apb_pclk";
385de7a4e01SFaraz Ata			#dma-cells = <1>;
386de7a4e01SFaraz Ata		};
387de7a4e01SFaraz Ata
388de7a4e01SFaraz Ata		pdma3: dma-controller@101d0000 {
389de7a4e01SFaraz Ata			compatible = "arm,pl330", "arm,primecell";
390de7a4e01SFaraz Ata			reg = <0x101d0000 0x1000>;
391de7a4e01SFaraz Ata			interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>;
392de7a4e01SFaraz Ata			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
393de7a4e01SFaraz Ata			clock-names = "apb_pclk";
394de7a4e01SFaraz Ata			#dma-cells = <1>;
395de7a4e01SFaraz Ata		};
396de7a4e01SFaraz Ata
397de7a4e01SFaraz Ata		pdma4: dma-controller@101e0000 {
398de7a4e01SFaraz Ata			compatible = "arm,pl330", "arm,primecell";
399de7a4e01SFaraz Ata			reg = <0x101e0000 0x1000>;
400de7a4e01SFaraz Ata			interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>;
401de7a4e01SFaraz Ata			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
402de7a4e01SFaraz Ata			clock-names = "apb_pclk";
403de7a4e01SFaraz Ata			#dma-cells = <1>;
404de7a4e01SFaraz Ata		};
405de7a4e01SFaraz Ata
4064d060009SSunyeal Hong		cmu_peric0: clock-controller@10800000 {
4074d060009SSunyeal Hong			compatible = "samsung,exynosautov920-cmu-peric0";
4084d060009SSunyeal Hong			reg = <0x10800000 0x8000>;
4094d060009SSunyeal Hong			#clock-cells = <1>;
4104d060009SSunyeal Hong
4114d060009SSunyeal Hong			clocks = <&xtcxo>,
4124d060009SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
4134d060009SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
4144d060009SSunyeal Hong			clock-names = "oscclk",
4154d060009SSunyeal Hong				      "noc",
4164d060009SSunyeal Hong				      "ip";
4174d060009SSunyeal Hong		};
4184d060009SSunyeal Hong
419c96dab19SJaewon Kim		syscon_peric0: syscon@10820000 {
420c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-peric0-sysreg",
421c96dab19SJaewon Kim				     "syscon";
422c96dab19SJaewon Kim			reg = <0x10820000 0x2000>;
423c96dab19SJaewon Kim		};
424c96dab19SJaewon Kim
425c96dab19SJaewon Kim		pinctrl_peric0: pinctrl@10830000 {
426c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
427c96dab19SJaewon Kim			reg = <0x10830000 0x10000>;
428c96dab19SJaewon Kim			interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
429c96dab19SJaewon Kim		};
430c96dab19SJaewon Kim
431c96dab19SJaewon Kim		usi_0: usi@108800c0 {
432c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-usi",
433c96dab19SJaewon Kim				     "samsung,exynos850-usi";
434c96dab19SJaewon Kim			reg = <0x108800c0 0x20>;
435c96dab19SJaewon Kim			samsung,sysreg = <&syscon_peric0 0x1000>;
43648552449SIvaylo Ivanov			samsung,mode = <USI_MODE_UART>;
437c96dab19SJaewon Kim			#address-cells = <1>;
438c96dab19SJaewon Kim			#size-cells = <1>;
439c96dab19SJaewon Kim			ranges;
4404d060009SSunyeal Hong			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
4414d060009SSunyeal Hong				 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
442c96dab19SJaewon Kim			clock-names = "pclk", "ipclk";
443c96dab19SJaewon Kim			status = "disabled";
444c96dab19SJaewon Kim
445c96dab19SJaewon Kim			serial_0: serial@10880000 {
446c96dab19SJaewon Kim				compatible = "samsung,exynosautov920-uart",
447c96dab19SJaewon Kim					     "samsung,exynos850-uart";
448c96dab19SJaewon Kim				reg = <0x10880000 0xc0>;
449c96dab19SJaewon Kim				interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
450c96dab19SJaewon Kim				pinctrl-names = "default";
451c96dab19SJaewon Kim				pinctrl-0 = <&uart0_bus>;
4524d060009SSunyeal Hong				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
4534d060009SSunyeal Hong					 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
454c96dab19SJaewon Kim				clock-names = "uart", "clk_uart_baud0";
455c96dab19SJaewon Kim				samsung,uart-fifosize = <256>;
456c96dab19SJaewon Kim				status = "disabled";
457c96dab19SJaewon Kim			};
458*134442a0SFaraz Ata
459*134442a0SFaraz Ata			spi_0: spi@10880000 {
460*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
461*134442a0SFaraz Ata					     "samsung,exynos850-spi";
462*134442a0SFaraz Ata				reg = <0x10880000 0x30>;
463*134442a0SFaraz Ata				interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
464*134442a0SFaraz Ata				pinctrl-names = "default";
465*134442a0SFaraz Ata				pinctrl-0 = <&spi0_bus &spi0_cs_func>;
466*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
467*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
468*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
469*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
470*134442a0SFaraz Ata				dmas = <&pdma0 1>, <&pdma0 0>;
471*134442a0SFaraz Ata				dma-names = "tx", "rx";
472*134442a0SFaraz Ata				num-cs = <1>;
473*134442a0SFaraz Ata				#address-cells = <1>;
474*134442a0SFaraz Ata				#size-cells = <0>;
475*134442a0SFaraz Ata				fifo-depth = <256>;
476*134442a0SFaraz Ata				status = "disabled";
477*134442a0SFaraz Ata			};
478c96dab19SJaewon Kim		};
479c96dab19SJaewon Kim
4801a6ee48dSFaraz Ata		usi_1: usi@108a00c0 {
4811a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
4821a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
4831a6ee48dSFaraz Ata			reg = <0x108a00c0 0x20>;
4841a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1008>;
4851a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
4861a6ee48dSFaraz Ata			#address-cells = <1>;
4871a6ee48dSFaraz Ata			#size-cells = <1>;
4881a6ee48dSFaraz Ata			ranges;
4891a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
4901a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>;
4911a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
4921a6ee48dSFaraz Ata			status = "disabled";
4931a6ee48dSFaraz Ata
4941a6ee48dSFaraz Ata			serial_1: serial@108a0000 {
4951a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
4961a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
4971a6ee48dSFaraz Ata				reg = <0x108a0000 0xc0>;
4981a6ee48dSFaraz Ata				interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
4991a6ee48dSFaraz Ata				pinctrl-names = "default";
5001a6ee48dSFaraz Ata				pinctrl-0 = <&uart1_bus>;
5011a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
5021a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>;
5031a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
5041a6ee48dSFaraz Ata				samsung,uart-fifosize = <256>;
5051a6ee48dSFaraz Ata				status = "disabled";
5061a6ee48dSFaraz Ata			};
507*134442a0SFaraz Ata
508*134442a0SFaraz Ata			spi_1: spi@108a0000 {
509*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
510*134442a0SFaraz Ata					     "samsung,exynos850-spi";
511*134442a0SFaraz Ata				reg = <0x108a0000 0x30>;
512*134442a0SFaraz Ata				interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
513*134442a0SFaraz Ata				pinctrl-names = "default";
514*134442a0SFaraz Ata				pinctrl-0 = <&spi1_bus &spi1_cs_func>;
515*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
516*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>;
517*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
518*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
519*134442a0SFaraz Ata				dmas = <&pdma0 3>, <&pdma0 2>;
520*134442a0SFaraz Ata				dma-names = "tx", "rx";
521*134442a0SFaraz Ata				num-cs = <1>;
522*134442a0SFaraz Ata				#address-cells = <1>;
523*134442a0SFaraz Ata				#size-cells = <0>;
524*134442a0SFaraz Ata				fifo-depth = <256>;
525*134442a0SFaraz Ata				status = "disabled";
526*134442a0SFaraz Ata			};
5271a6ee48dSFaraz Ata		};
5281a6ee48dSFaraz Ata
5291a6ee48dSFaraz Ata		usi_2: usi@108c00c0 {
5301a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
5311a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
5321a6ee48dSFaraz Ata			reg = <0x108c00c0 0x20>;
5331a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1010>;
5341a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
5351a6ee48dSFaraz Ata			#address-cells = <1>;
5361a6ee48dSFaraz Ata			#size-cells = <1>;
5371a6ee48dSFaraz Ata			ranges;
5381a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
5391a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>;
5401a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
5411a6ee48dSFaraz Ata			status = "disabled";
5421a6ee48dSFaraz Ata
5431a6ee48dSFaraz Ata			serial_2: serial@108c0000 {
5441a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
5451a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
5461a6ee48dSFaraz Ata				reg = <0x108c0000 0xc0>;
5471a6ee48dSFaraz Ata				interrupts = <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>;
5481a6ee48dSFaraz Ata				pinctrl-names = "default";
5491a6ee48dSFaraz Ata				pinctrl-0 = <&uart2_bus>;
5501a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
5511a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>;
5521a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
5531a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
5541a6ee48dSFaraz Ata				status = "disabled";
5551a6ee48dSFaraz Ata			};
556*134442a0SFaraz Ata
557*134442a0SFaraz Ata			spi_2: spi@108c0000 {
558*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
559*134442a0SFaraz Ata					     "samsung,exynos850-spi";
560*134442a0SFaraz Ata				reg = <0x108c0000 0x30>;
561*134442a0SFaraz Ata				interrupts = <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>;
562*134442a0SFaraz Ata				pinctrl-names = "default";
563*134442a0SFaraz Ata				pinctrl-0 = <&spi2_bus &spi2_cs_func>;
564*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
565*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>;
566*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
567*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
568*134442a0SFaraz Ata				dmas = <&pdma0 5>, <&pdma0 4>;
569*134442a0SFaraz Ata				dma-names = "tx", "rx";
570*134442a0SFaraz Ata				num-cs = <1>;
571*134442a0SFaraz Ata				#address-cells = <1>;
572*134442a0SFaraz Ata				#size-cells = <0>;
573*134442a0SFaraz Ata				fifo-depth = <64>;
574*134442a0SFaraz Ata				status = "disabled";
575*134442a0SFaraz Ata			};
5761a6ee48dSFaraz Ata		};
5771a6ee48dSFaraz Ata
5781a6ee48dSFaraz Ata		usi_3: usi@108e00c0 {
5791a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
5801a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
5811a6ee48dSFaraz Ata			reg = <0x108e00c0 0x20>;
5821a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1018>;
5831a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
5841a6ee48dSFaraz Ata			#address-cells = <1>;
5851a6ee48dSFaraz Ata			#size-cells = <1>;
5861a6ee48dSFaraz Ata			ranges;
5871a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
5881a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>;
5891a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
5901a6ee48dSFaraz Ata			status = "disabled";
5911a6ee48dSFaraz Ata
5921a6ee48dSFaraz Ata			serial_3: serial@108e0000 {
5931a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
5941a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
5951a6ee48dSFaraz Ata				reg = <0x108e0000 0xc0>;
5961a6ee48dSFaraz Ata				interrupts = <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
5971a6ee48dSFaraz Ata				pinctrl-names = "default";
5981a6ee48dSFaraz Ata				pinctrl-0 = <&uart3_bus>;
5991a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
6001a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>;
6011a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
6021a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
6031a6ee48dSFaraz Ata				status = "disabled";
6041a6ee48dSFaraz Ata			};
605*134442a0SFaraz Ata
606*134442a0SFaraz Ata			spi_3: spi@108e0000 {
607*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
608*134442a0SFaraz Ata					     "samsung,exynos850-spi";
609*134442a0SFaraz Ata				reg = <0x108e0000 0x30>;
610*134442a0SFaraz Ata				interrupts = <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
611*134442a0SFaraz Ata				pinctrl-names = "default";
612*134442a0SFaraz Ata				pinctrl-0 = <&spi3_bus &spi3_cs_func>;
613*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
614*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>;
615*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
616*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
617*134442a0SFaraz Ata				dmas = <&pdma0 7>, <&pdma0 6>;
618*134442a0SFaraz Ata				dma-names = "tx", "rx";
619*134442a0SFaraz Ata				num-cs = <1>;
620*134442a0SFaraz Ata				#address-cells = <1>;
621*134442a0SFaraz Ata				#size-cells = <0>;
622*134442a0SFaraz Ata				fifo-depth = <64>;
623*134442a0SFaraz Ata				status = "disabled";
624*134442a0SFaraz Ata			};
6251a6ee48dSFaraz Ata		};
6261a6ee48dSFaraz Ata
6271a6ee48dSFaraz Ata		usi_4: usi@109000c0 {
6281a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
6291a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
6301a6ee48dSFaraz Ata			reg = <0x109000c0 0x20>;
6311a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1020>;
6321a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
6331a6ee48dSFaraz Ata			#address-cells = <1>;
6341a6ee48dSFaraz Ata			#size-cells = <1>;
6351a6ee48dSFaraz Ata			ranges;
6361a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
6371a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>;
6381a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
6391a6ee48dSFaraz Ata			status = "disabled";
6401a6ee48dSFaraz Ata
6411a6ee48dSFaraz Ata			serial_4: serial@10900000 {
6421a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
6431a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
6441a6ee48dSFaraz Ata				reg = <0x10900000 0xc0>;
6451a6ee48dSFaraz Ata				interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>;
6461a6ee48dSFaraz Ata				pinctrl-names = "default";
6471a6ee48dSFaraz Ata				pinctrl-0 = <&uart4_bus>;
6481a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
6491a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>;
6501a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
6511a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
6521a6ee48dSFaraz Ata				status = "disabled";
6531a6ee48dSFaraz Ata			};
654*134442a0SFaraz Ata
655*134442a0SFaraz Ata			spi_4: spi@10900000 {
656*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
657*134442a0SFaraz Ata					     "samsung,exynos850-spi";
658*134442a0SFaraz Ata				reg = <0x10900000 0x30>;
659*134442a0SFaraz Ata				interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>;
660*134442a0SFaraz Ata				pinctrl-names = "default";
661*134442a0SFaraz Ata				pinctrl-0 = <&spi4_bus &spi4_cs_func>;
662*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
663*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>;
664*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
665*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
666*134442a0SFaraz Ata				dmas = <&pdma0 9>, <&pdma0 8>;
667*134442a0SFaraz Ata				dma-names = "tx", "rx";
668*134442a0SFaraz Ata				num-cs = <1>;
669*134442a0SFaraz Ata				#address-cells = <1>;
670*134442a0SFaraz Ata				#size-cells = <0>;
671*134442a0SFaraz Ata				fifo-depth = <64>;
672*134442a0SFaraz Ata				status = "disabled";
673*134442a0SFaraz Ata			};
6741a6ee48dSFaraz Ata		};
6751a6ee48dSFaraz Ata
6761a6ee48dSFaraz Ata		usi_5: usi@109200c0 {
6771a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
6781a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
6791a6ee48dSFaraz Ata			reg = <0x109200c0 0x20>;
6801a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1028>;
6811a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
6821a6ee48dSFaraz Ata			#address-cells = <1>;
6831a6ee48dSFaraz Ata			#size-cells = <1>;
6841a6ee48dSFaraz Ata			ranges;
6851a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
6861a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>;
6871a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
6881a6ee48dSFaraz Ata			status = "disabled";
6891a6ee48dSFaraz Ata
6901a6ee48dSFaraz Ata			serial_5: serial@10920000 {
6911a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
6921a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
6931a6ee48dSFaraz Ata				reg = <0x10920000 0xc0>;
6941a6ee48dSFaraz Ata				interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
6951a6ee48dSFaraz Ata				pinctrl-names = "default";
6961a6ee48dSFaraz Ata				pinctrl-0 = <&uart5_bus>;
6971a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
6981a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>;
6991a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
7001a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
7011a6ee48dSFaraz Ata				status = "disabled";
7021a6ee48dSFaraz Ata			};
703*134442a0SFaraz Ata
704*134442a0SFaraz Ata			spi_5: spi@10920000 {
705*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
706*134442a0SFaraz Ata					     "samsung,exynos850-spi";
707*134442a0SFaraz Ata				reg = <0x10920000 0x30>;
708*134442a0SFaraz Ata				interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
709*134442a0SFaraz Ata				pinctrl-names = "default";
710*134442a0SFaraz Ata				pinctrl-0 = <&spi5_bus &spi5_cs_func>;
711*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
712*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>;
713*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
714*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
715*134442a0SFaraz Ata				dmas = <&pdma0 11>, <&pdma0 10>;
716*134442a0SFaraz Ata				dma-names = "tx", "rx";
717*134442a0SFaraz Ata				num-cs = <1>;
718*134442a0SFaraz Ata				#address-cells = <1>;
719*134442a0SFaraz Ata				#size-cells = <0>;
720*134442a0SFaraz Ata				fifo-depth = <64>;
721*134442a0SFaraz Ata				status = "disabled";
722*134442a0SFaraz Ata			};
7231a6ee48dSFaraz Ata		};
7241a6ee48dSFaraz Ata
7251a6ee48dSFaraz Ata		usi_6: usi@109400c0 {
7261a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
7271a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
7281a6ee48dSFaraz Ata			reg = <0x109400c0 0x20>;
7291a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1030>;
7301a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
7311a6ee48dSFaraz Ata			#address-cells = <1>;
7321a6ee48dSFaraz Ata			#size-cells = <1>;
7331a6ee48dSFaraz Ata			ranges;
7341a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
7351a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>;
7361a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
7371a6ee48dSFaraz Ata			status = "disabled";
7381a6ee48dSFaraz Ata
7391a6ee48dSFaraz Ata			serial_6: serial@10940000 {
7401a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
7411a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
7421a6ee48dSFaraz Ata				reg = <0x10940000 0xc0>;
7431a6ee48dSFaraz Ata				interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>;
7441a6ee48dSFaraz Ata				pinctrl-names = "default";
7451a6ee48dSFaraz Ata				pinctrl-0 = <&uart6_bus>;
7461a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
7471a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>;
7481a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
7491a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
7501a6ee48dSFaraz Ata				status = "disabled";
7511a6ee48dSFaraz Ata			};
752*134442a0SFaraz Ata
753*134442a0SFaraz Ata			spi_6: spi@10940000 {
754*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
755*134442a0SFaraz Ata					     "samsung,exynos850-spi";
756*134442a0SFaraz Ata				reg = <0x10940000 0x30>;
757*134442a0SFaraz Ata				interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>;
758*134442a0SFaraz Ata				pinctrl-names = "default";
759*134442a0SFaraz Ata				pinctrl-0 = <&spi6_bus &spi6_cs_func>;
760*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
761*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>;
762*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
763*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
764*134442a0SFaraz Ata				dmas = <&pdma0 13>, <&pdma0 12>;
765*134442a0SFaraz Ata				dma-names = "tx", "rx";
766*134442a0SFaraz Ata				num-cs = <1>;
767*134442a0SFaraz Ata				#address-cells = <1>;
768*134442a0SFaraz Ata				#size-cells = <0>;
769*134442a0SFaraz Ata				fifo-depth = <64>;
770*134442a0SFaraz Ata				status = "disabled";
771*134442a0SFaraz Ata			};
7721a6ee48dSFaraz Ata		};
7731a6ee48dSFaraz Ata
7741a6ee48dSFaraz Ata		usi_7: usi@109600c0 {
7751a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
7761a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
7771a6ee48dSFaraz Ata			reg = <0x109600c0 0x20>;
7781a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1038>;
7791a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
7801a6ee48dSFaraz Ata			#address-cells = <1>;
7811a6ee48dSFaraz Ata			#size-cells = <1>;
7821a6ee48dSFaraz Ata			ranges;
7831a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
7841a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>;
7851a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
7861a6ee48dSFaraz Ata			status = "disabled";
7871a6ee48dSFaraz Ata
7881a6ee48dSFaraz Ata			serial_7: serial@10960000 {
7891a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
7901a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
7911a6ee48dSFaraz Ata				reg = <0x10960000 0xc0>;
7921a6ee48dSFaraz Ata				interrupts = <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>;
7931a6ee48dSFaraz Ata				pinctrl-names = "default";
7941a6ee48dSFaraz Ata				pinctrl-0 = <&uart7_bus>;
7951a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
7961a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>;
7971a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
7981a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
7991a6ee48dSFaraz Ata				status = "disabled";
8001a6ee48dSFaraz Ata			};
801*134442a0SFaraz Ata
802*134442a0SFaraz Ata			spi_7: spi@10960000 {
803*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
804*134442a0SFaraz Ata					     "samsung,exynos850-spi";
805*134442a0SFaraz Ata				reg = <0x10960000 0x30>;
806*134442a0SFaraz Ata				interrupts = <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>;
807*134442a0SFaraz Ata				pinctrl-names = "default";
808*134442a0SFaraz Ata				pinctrl-0 = <&spi7_bus &spi7_cs_func>;
809*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
810*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>;
811*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
812*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
813*134442a0SFaraz Ata				dmas = <&pdma0 15>, <&pdma0 14>;
814*134442a0SFaraz Ata				dma-names = "tx", "rx";
815*134442a0SFaraz Ata				num-cs = <1>;
816*134442a0SFaraz Ata				#address-cells = <1>;
817*134442a0SFaraz Ata				#size-cells = <0>;
818*134442a0SFaraz Ata				fifo-depth = <64>;
819*134442a0SFaraz Ata				status = "disabled";
820*134442a0SFaraz Ata			};
8211a6ee48dSFaraz Ata		};
8221a6ee48dSFaraz Ata
8231a6ee48dSFaraz Ata		usi_8: usi@109800c0 {
8241a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
8251a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
8261a6ee48dSFaraz Ata			reg = <0x109800c0 0x20>;
8271a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric0 0x1040>;
8281a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
8291a6ee48dSFaraz Ata			#address-cells = <1>;
8301a6ee48dSFaraz Ata			#size-cells = <1>;
8311a6ee48dSFaraz Ata			ranges;
8321a6ee48dSFaraz Ata			clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
8331a6ee48dSFaraz Ata				 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>;
8341a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
8351a6ee48dSFaraz Ata			status = "disabled";
8361a6ee48dSFaraz Ata
8371a6ee48dSFaraz Ata			serial_8: serial@10980000 {
8381a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
8391a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
8401a6ee48dSFaraz Ata				reg = <0x10980000 0xc0>;
8411a6ee48dSFaraz Ata				interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>;
8421a6ee48dSFaraz Ata				pinctrl-names = "default";
8431a6ee48dSFaraz Ata				pinctrl-0 = <&uart8_bus>;
8441a6ee48dSFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
8451a6ee48dSFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>;
8461a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
8471a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
8481a6ee48dSFaraz Ata				status = "disabled";
8491a6ee48dSFaraz Ata			};
850*134442a0SFaraz Ata
851*134442a0SFaraz Ata			spi_8: spi@10980000 {
852*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
853*134442a0SFaraz Ata					     "samsung,exynos850-spi";
854*134442a0SFaraz Ata				reg = <0x10980000 0x30>;
855*134442a0SFaraz Ata				interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>;
856*134442a0SFaraz Ata				pinctrl-names = "default";
857*134442a0SFaraz Ata				pinctrl-0 = <&spi8_bus &spi8_cs_func>;
858*134442a0SFaraz Ata				clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
859*134442a0SFaraz Ata					 <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>;
860*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
861*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
862*134442a0SFaraz Ata				dmas = <&pdma0 17>, <&pdma0 16>;
863*134442a0SFaraz Ata				dma-names = "tx", "rx";
864*134442a0SFaraz Ata				num-cs = <1>;
865*134442a0SFaraz Ata				#address-cells = <1>;
866*134442a0SFaraz Ata				#size-cells = <0>;
867*134442a0SFaraz Ata				fifo-depth = <64>;
868*134442a0SFaraz Ata				status = "disabled";
869*134442a0SFaraz Ata			};
870*134442a0SFaraz Ata
8711a6ee48dSFaraz Ata		};
8721a6ee48dSFaraz Ata
873c96dab19SJaewon Kim		pwm: pwm@109b0000 {
874c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pwm",
875c96dab19SJaewon Kim				     "samsung,exynos4210-pwm";
876c96dab19SJaewon Kim			reg = <0x109b0000 0x100>;
877c96dab19SJaewon Kim			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
878c96dab19SJaewon Kim			#pwm-cells = <3>;
879c96dab19SJaewon Kim			clocks = <&xtcxo>;
880c96dab19SJaewon Kim			clock-names = "timers";
881c96dab19SJaewon Kim			status = "disabled";
882c96dab19SJaewon Kim		};
883c96dab19SJaewon Kim
884ef1c2a54SSunyeal Hong		cmu_peric1: clock-controller@10c00000 {
885ef1c2a54SSunyeal Hong			compatible = "samsung,exynosautov920-cmu-peric1";
886ef1c2a54SSunyeal Hong			reg = <0x10c00000 0x8000>;
887ef1c2a54SSunyeal Hong			#clock-cells = <1>;
888ef1c2a54SSunyeal Hong
889ef1c2a54SSunyeal Hong			clocks = <&xtcxo>,
890ef1c2a54SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_PERIC1_NOC>,
891ef1c2a54SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_PERIC1_IP>;
892ef1c2a54SSunyeal Hong			clock-names = "oscclk",
893ef1c2a54SSunyeal Hong				      "noc",
894ef1c2a54SSunyeal Hong				      "ip";
895ef1c2a54SSunyeal Hong		};
896ef1c2a54SSunyeal Hong
897c96dab19SJaewon Kim		syscon_peric1: syscon@10c20000 {
898c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-peric1-sysreg",
899c96dab19SJaewon Kim				     "syscon";
900c96dab19SJaewon Kim			reg = <0x10c20000 0x2000>;
901c96dab19SJaewon Kim		};
902c96dab19SJaewon Kim
903c96dab19SJaewon Kim		pinctrl_peric1: pinctrl@10c30000 {
904c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
905c96dab19SJaewon Kim			reg = <0x10c30000 0x10000>;
906c96dab19SJaewon Kim			interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
907c96dab19SJaewon Kim		};
908c96dab19SJaewon Kim
9091a6ee48dSFaraz Ata		usi_9: usi@10c800c0 {
9101a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
9111a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
9121a6ee48dSFaraz Ata			reg = <0x10c800c0 0x20>;
9131a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1000>;
9141a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
9151a6ee48dSFaraz Ata			#address-cells = <1>;
9161a6ee48dSFaraz Ata			#size-cells = <1>;
9171a6ee48dSFaraz Ata			ranges;
9181a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
9191a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>;
9201a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
9211a6ee48dSFaraz Ata			status = "disabled";
9221a6ee48dSFaraz Ata
9231a6ee48dSFaraz Ata			serial_9: serial@10c8000 {
9241a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
9251a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
9261a6ee48dSFaraz Ata				reg = <0x10c80000 0xc0>;
9271a6ee48dSFaraz Ata				interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
9281a6ee48dSFaraz Ata				pinctrl-names = "default";
9291a6ee48dSFaraz Ata				pinctrl-0 = <&uart9_bus>;
9301a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
9311a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>;
9321a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
9331a6ee48dSFaraz Ata				samsung,uart-fifosize = <256>;
9341a6ee48dSFaraz Ata				status = "disabled";
9351a6ee48dSFaraz Ata			};
936*134442a0SFaraz Ata
937*134442a0SFaraz Ata			spi_9: spi@10c80000 {
938*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
939*134442a0SFaraz Ata					     "samsung,exynos850-spi";
940*134442a0SFaraz Ata				reg = <0x10c80000 0x30>;
941*134442a0SFaraz Ata				interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
942*134442a0SFaraz Ata				pinctrl-names = "default";
943*134442a0SFaraz Ata				pinctrl-0 = <&spi9_bus &spi9_cs_func>;
944*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
945*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>;
946*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
947*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
948*134442a0SFaraz Ata				dmas = <&pdma1 1>, <&pdma1 0>;
949*134442a0SFaraz Ata				dma-names = "tx", "rx";
950*134442a0SFaraz Ata				num-cs = <1>;
951*134442a0SFaraz Ata				#address-cells = <1>;
952*134442a0SFaraz Ata				#size-cells = <0>;
953*134442a0SFaraz Ata				fifo-depth = <256>;
954*134442a0SFaraz Ata				status = "disabled";
955*134442a0SFaraz Ata			};
9561a6ee48dSFaraz Ata		};
9571a6ee48dSFaraz Ata
9581a6ee48dSFaraz Ata		usi_10: usi@10ca00c0 {
9591a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
9601a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
9611a6ee48dSFaraz Ata			reg = <0x10ca00c0 0x20>;
9621a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1008>;
9631a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
9641a6ee48dSFaraz Ata			#address-cells = <1>;
9651a6ee48dSFaraz Ata			#size-cells = <1>;
9661a6ee48dSFaraz Ata			ranges;
9671a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
9681a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>;
9691a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
9701a6ee48dSFaraz Ata			status = "disabled";
9711a6ee48dSFaraz Ata
9721a6ee48dSFaraz Ata			serial_10: serial@10ca0000 {
9731a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
9741a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
9751a6ee48dSFaraz Ata				reg = <0x10ca0000 0xc0>;
9761a6ee48dSFaraz Ata				interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>;
9771a6ee48dSFaraz Ata				pinctrl-names = "default";
9781a6ee48dSFaraz Ata				pinctrl-0 = <&uart10_bus>;
9791a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
9801a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>;
9811a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
9821a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
9831a6ee48dSFaraz Ata				status = "disabled";
9841a6ee48dSFaraz Ata			};
985*134442a0SFaraz Ata
986*134442a0SFaraz Ata			spi_10: spi@10ca0000 {
987*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
988*134442a0SFaraz Ata					     "samsung,exynos850-spi";
989*134442a0SFaraz Ata				reg = <0x10ca0000 0x30>;
990*134442a0SFaraz Ata				interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>;
991*134442a0SFaraz Ata				pinctrl-names = "default";
992*134442a0SFaraz Ata				pinctrl-0 = <&spi10_bus &spi10_cs_func>;
993*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
994*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>;
995*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
996*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
997*134442a0SFaraz Ata				dmas = <&pdma1 3>, <&pdma1 2>;
998*134442a0SFaraz Ata				dma-names = "tx", "rx";
999*134442a0SFaraz Ata				num-cs = <1>;
1000*134442a0SFaraz Ata				#address-cells = <1>;
1001*134442a0SFaraz Ata				#size-cells = <0>;
1002*134442a0SFaraz Ata				fifo-depth = <64>;
1003*134442a0SFaraz Ata				status = "disabled";
1004*134442a0SFaraz Ata			};
10051a6ee48dSFaraz Ata		};
10061a6ee48dSFaraz Ata
10071a6ee48dSFaraz Ata		usi_11: usi@10cc00c0 {
10081a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
10091a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
10101a6ee48dSFaraz Ata			reg = <0x10cc00c0 0x20>;
10111a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1010>;
10121a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
10131a6ee48dSFaraz Ata			#address-cells = <1>;
10141a6ee48dSFaraz Ata			#size-cells = <1>;
10151a6ee48dSFaraz Ata			ranges;
10161a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
10171a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>;
10181a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
10191a6ee48dSFaraz Ata			status = "disabled";
10201a6ee48dSFaraz Ata
10211a6ee48dSFaraz Ata			serial_11: serial@10cc0000 {
10221a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
10231a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
10241a6ee48dSFaraz Ata				reg = <0x10cc0000 0xc0>;
10251a6ee48dSFaraz Ata				interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>;
10261a6ee48dSFaraz Ata				pinctrl-names = "default";
10271a6ee48dSFaraz Ata				pinctrl-0 = <&uart11_bus>;
10281a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
10291a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>;
10301a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
10311a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
10321a6ee48dSFaraz Ata				status = "disabled";
10331a6ee48dSFaraz Ata			};
1034*134442a0SFaraz Ata
1035*134442a0SFaraz Ata			spi_11: spi@10cc0000 {
1036*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
1037*134442a0SFaraz Ata					     "samsung,exynos850-spi";
1038*134442a0SFaraz Ata				reg = <0x10cc0000 0x30>;
1039*134442a0SFaraz Ata				interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>;
1040*134442a0SFaraz Ata				pinctrl-names = "default";
1041*134442a0SFaraz Ata				pinctrl-0 = <&spi11_bus &spi11_cs_func>;
1042*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
1043*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>;
1044*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
1045*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
1046*134442a0SFaraz Ata				dmas = <&pdma1 5>, <&pdma1 4>;
1047*134442a0SFaraz Ata				dma-names = "tx", "rx";
1048*134442a0SFaraz Ata				num-cs = <1>;
1049*134442a0SFaraz Ata				#address-cells = <1>;
1050*134442a0SFaraz Ata				#size-cells = <0>;
1051*134442a0SFaraz Ata				fifo-depth = <64>;
1052*134442a0SFaraz Ata				status = "disabled";
1053*134442a0SFaraz Ata			};
10541a6ee48dSFaraz Ata		};
10551a6ee48dSFaraz Ata
10561a6ee48dSFaraz Ata		usi_12: usi@10ce00c0 {
10571a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
10581a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
10591a6ee48dSFaraz Ata			reg = <0x10ce00c0 0x20>;
10601a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1018>;
10611a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
10621a6ee48dSFaraz Ata			#address-cells = <1>;
10631a6ee48dSFaraz Ata			#size-cells = <1>;
10641a6ee48dSFaraz Ata			ranges;
10651a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
10661a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>;
10671a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
10681a6ee48dSFaraz Ata			status = "disabled";
10691a6ee48dSFaraz Ata
10701a6ee48dSFaraz Ata			serial_12: serial@10ce0000 {
10711a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
10721a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
10731a6ee48dSFaraz Ata				reg = <0x10ce0000 0xc0>;
10741a6ee48dSFaraz Ata				interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>;
10751a6ee48dSFaraz Ata				pinctrl-names = "default";
10761a6ee48dSFaraz Ata				pinctrl-0 = <&uart12_bus>;
10771a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
10781a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>;
10791a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
10801a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
10811a6ee48dSFaraz Ata				status = "disabled";
10821a6ee48dSFaraz Ata			};
1083*134442a0SFaraz Ata
1084*134442a0SFaraz Ata			spi_12: spi@10ce0000 {
1085*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
1086*134442a0SFaraz Ata					     "samsung,exynos850-spi";
1087*134442a0SFaraz Ata				reg = <0x10ce0000 0x30>;
1088*134442a0SFaraz Ata				interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>;
1089*134442a0SFaraz Ata				pinctrl-names = "default";
1090*134442a0SFaraz Ata				pinctrl-0 = <&spi12_bus &spi12_cs_func>;
1091*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
1092*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>;
1093*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
1094*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
1095*134442a0SFaraz Ata				dmas = <&pdma1 7>, <&pdma1 6>;
1096*134442a0SFaraz Ata				dma-names = "tx", "rx";
1097*134442a0SFaraz Ata				num-cs = <1>;
1098*134442a0SFaraz Ata				#address-cells = <1>;
1099*134442a0SFaraz Ata				#size-cells = <0>;
1100*134442a0SFaraz Ata				fifo-depth = <64>;
1101*134442a0SFaraz Ata				status = "disabled";
1102*134442a0SFaraz Ata			};
11031a6ee48dSFaraz Ata		};
11041a6ee48dSFaraz Ata
11051a6ee48dSFaraz Ata		usi_13: usi@10d000c0 {
11061a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
11071a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
11081a6ee48dSFaraz Ata			reg = <0x10d000c0 0x20>;
11091a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1020>;
11101a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
11111a6ee48dSFaraz Ata			#address-cells = <1>;
11121a6ee48dSFaraz Ata			#size-cells = <1>;
11131a6ee48dSFaraz Ata			ranges;
11141a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
11151a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>;
11161a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
11171a6ee48dSFaraz Ata			status = "disabled";
11181a6ee48dSFaraz Ata
11191a6ee48dSFaraz Ata			serial_13: serial@10d00000 {
11201a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
11211a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
11221a6ee48dSFaraz Ata				reg = <0x10d00000 0xc0>;
11231a6ee48dSFaraz Ata				interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>;
11241a6ee48dSFaraz Ata				pinctrl-names = "default";
11251a6ee48dSFaraz Ata				pinctrl-0 = <&uart13_bus>;
11261a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
11271a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>;
11281a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
11291a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
11301a6ee48dSFaraz Ata				status = "disabled";
11311a6ee48dSFaraz Ata			};
1132*134442a0SFaraz Ata
1133*134442a0SFaraz Ata			spi_13: spi@10d00000 {
1134*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
1135*134442a0SFaraz Ata					     "samsung,exynos850-spi";
1136*134442a0SFaraz Ata				reg = <0x10d00000 0x30>;
1137*134442a0SFaraz Ata				interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>;
1138*134442a0SFaraz Ata				pinctrl-names = "default";
1139*134442a0SFaraz Ata				pinctrl-0 = <&spi13_bus &spi13_cs_func>;
1140*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
1141*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>;
1142*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
1143*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
1144*134442a0SFaraz Ata				dmas = <&pdma1 9>, <&pdma1 8>;
1145*134442a0SFaraz Ata				dma-names = "tx", "rx";
1146*134442a0SFaraz Ata				num-cs = <1>;
1147*134442a0SFaraz Ata				#address-cells = <1>;
1148*134442a0SFaraz Ata				#size-cells = <0>;
1149*134442a0SFaraz Ata				fifo-depth = <64>;
1150*134442a0SFaraz Ata				status = "disabled";
1151*134442a0SFaraz Ata			};
11521a6ee48dSFaraz Ata		};
11531a6ee48dSFaraz Ata
11541a6ee48dSFaraz Ata		usi_14: usi@10d200c0 {
11551a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
11561a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
11571a6ee48dSFaraz Ata			reg = <0x10d200c0 0x20>;
11581a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1028>;
11591a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
11601a6ee48dSFaraz Ata			#address-cells = <1>;
11611a6ee48dSFaraz Ata			#size-cells = <1>;
11621a6ee48dSFaraz Ata			ranges;
11631a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
11641a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>;
11651a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
11661a6ee48dSFaraz Ata			status = "disabled";
11671a6ee48dSFaraz Ata
11681a6ee48dSFaraz Ata			serial_14: serial@10d20000 {
11691a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
11701a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
11711a6ee48dSFaraz Ata				reg = <0x10d20000 0xc0>;
11721a6ee48dSFaraz Ata				interrupts = <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>;
11731a6ee48dSFaraz Ata				pinctrl-names = "default";
11741a6ee48dSFaraz Ata				pinctrl-0 = <&uart14_bus>;
11751a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
11761a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>;
11771a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
11781a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
11791a6ee48dSFaraz Ata				status = "disabled";
11801a6ee48dSFaraz Ata			};
1181*134442a0SFaraz Ata
1182*134442a0SFaraz Ata			spi_14: spi@10d20000 {
1183*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
1184*134442a0SFaraz Ata					     "samsung,exynos850-spi";
1185*134442a0SFaraz Ata				reg = <0x10d20000 0x30>;
1186*134442a0SFaraz Ata				interrupts = <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>;
1187*134442a0SFaraz Ata				pinctrl-names = "default";
1188*134442a0SFaraz Ata				pinctrl-0 = <&spi14_bus &spi14_cs_func>;
1189*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
1190*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>;
1191*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
1192*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
1193*134442a0SFaraz Ata				dmas = <&pdma1 11>, <&pdma1 10>;
1194*134442a0SFaraz Ata				dma-names = "tx", "rx";
1195*134442a0SFaraz Ata				num-cs = <1>;
1196*134442a0SFaraz Ata				#address-cells = <1>;
1197*134442a0SFaraz Ata				#size-cells = <0>;
1198*134442a0SFaraz Ata				fifo-depth = <64>;
1199*134442a0SFaraz Ata				status = "disabled";
1200*134442a0SFaraz Ata			};
12011a6ee48dSFaraz Ata		};
12021a6ee48dSFaraz Ata
12031a6ee48dSFaraz Ata		usi_15: usi@10d400c0 {
12041a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
12051a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
12061a6ee48dSFaraz Ata			reg = <0x10d400c0 0x20>;
12071a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1030>;
12081a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
12091a6ee48dSFaraz Ata			#address-cells = <1>;
12101a6ee48dSFaraz Ata			#size-cells = <1>;
12111a6ee48dSFaraz Ata			ranges;
12121a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
12131a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>;
12141a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
12151a6ee48dSFaraz Ata			status = "disabled";
12161a6ee48dSFaraz Ata
12171a6ee48dSFaraz Ata			serial_15: serial@10d40000 {
12181a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
12191a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
12201a6ee48dSFaraz Ata				reg = <0x10d40000 0xc0>;
12211a6ee48dSFaraz Ata				interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
12221a6ee48dSFaraz Ata				pinctrl-names = "default";
12231a6ee48dSFaraz Ata				pinctrl-0 = <&uart15_bus>;
12241a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
12251a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>;
12261a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
12271a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
12281a6ee48dSFaraz Ata				status = "disabled";
12291a6ee48dSFaraz Ata			};
1230*134442a0SFaraz Ata
1231*134442a0SFaraz Ata			spi_15: spi@10d40000 {
1232*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
1233*134442a0SFaraz Ata					     "samsung,exynos850-spi";
1234*134442a0SFaraz Ata				reg = <0x10d40000 0x30>;
1235*134442a0SFaraz Ata				interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
1236*134442a0SFaraz Ata				pinctrl-names = "default";
1237*134442a0SFaraz Ata				pinctrl-0 = <&spi15_bus &spi15_cs_func>;
1238*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
1239*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>;
1240*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
1241*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
1242*134442a0SFaraz Ata				dmas = <&pdma1 13>, <&pdma1 12>;
1243*134442a0SFaraz Ata				dma-names = "tx", "rx";
1244*134442a0SFaraz Ata				num-cs = <1>;
1245*134442a0SFaraz Ata				#address-cells = <1>;
1246*134442a0SFaraz Ata				#size-cells = <0>;
1247*134442a0SFaraz Ata				fifo-depth = <64>;
1248*134442a0SFaraz Ata				status = "disabled";
1249*134442a0SFaraz Ata			};
12501a6ee48dSFaraz Ata		};
12511a6ee48dSFaraz Ata
12521a6ee48dSFaraz Ata		usi_16: usi@10d600c0 {
12531a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
12541a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
12551a6ee48dSFaraz Ata			reg = <0x10d600c0 0x20>;
12561a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1038>;
12571a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
12581a6ee48dSFaraz Ata			#address-cells = <1>;
12591a6ee48dSFaraz Ata			#size-cells = <1>;
12601a6ee48dSFaraz Ata			ranges;
12611a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
12621a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>;
12631a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
12641a6ee48dSFaraz Ata			status = "disabled";
12651a6ee48dSFaraz Ata
12661a6ee48dSFaraz Ata			serial_16: serial@10d60000 {
12671a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
12681a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
12691a6ee48dSFaraz Ata				reg = <0x10d60000 0xc0>;
12701a6ee48dSFaraz Ata				interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
12711a6ee48dSFaraz Ata				pinctrl-names = "default";
12721a6ee48dSFaraz Ata				pinctrl-0 = <&uart16_bus>;
12731a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
12741a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>;
12751a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
12761a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
12771a6ee48dSFaraz Ata				status = "disabled";
12781a6ee48dSFaraz Ata			};
1279*134442a0SFaraz Ata
1280*134442a0SFaraz Ata			spi_16: spi@10d60000 {
1281*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
1282*134442a0SFaraz Ata					     "samsung,exynos850-spi";
1283*134442a0SFaraz Ata				reg = <0x10d60000 0x30>;
1284*134442a0SFaraz Ata				interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1285*134442a0SFaraz Ata				pinctrl-names = "default";
1286*134442a0SFaraz Ata				pinctrl-0 = <&spi16_bus &spi16_cs_func>;
1287*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
1288*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>;
1289*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
1290*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
1291*134442a0SFaraz Ata				dmas = <&pdma1 15>, <&pdma1 14>;
1292*134442a0SFaraz Ata				dma-names = "tx", "rx";
1293*134442a0SFaraz Ata				num-cs = <1>;
1294*134442a0SFaraz Ata				#address-cells = <1>;
1295*134442a0SFaraz Ata				#size-cells = <0>;
1296*134442a0SFaraz Ata				fifo-depth = <64>;
1297*134442a0SFaraz Ata				status = "disabled";
1298*134442a0SFaraz Ata			};
12991a6ee48dSFaraz Ata		};
13001a6ee48dSFaraz Ata
13011a6ee48dSFaraz Ata		usi_17: usi@10d800c0 {
13021a6ee48dSFaraz Ata			compatible = "samsung,exynosautov920-usi",
13031a6ee48dSFaraz Ata				     "samsung,exynos850-usi";
13041a6ee48dSFaraz Ata			reg = <0x10d800c0 0x20>;
13051a6ee48dSFaraz Ata			samsung,sysreg = <&syscon_peric1 0x1040>;
13061a6ee48dSFaraz Ata			samsung,mode = <USI_V2_UART>;
13071a6ee48dSFaraz Ata			#address-cells = <1>;
13081a6ee48dSFaraz Ata			#size-cells = <1>;
13091a6ee48dSFaraz Ata			ranges;
13101a6ee48dSFaraz Ata			clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
13111a6ee48dSFaraz Ata				 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>;
13121a6ee48dSFaraz Ata			clock-names = "pclk", "ipclk";
13131a6ee48dSFaraz Ata			status = "disabled";
13141a6ee48dSFaraz Ata
13151a6ee48dSFaraz Ata			serial_17: serial@10d80000 {
13161a6ee48dSFaraz Ata				compatible = "samsung,exynosautov920-uart",
13171a6ee48dSFaraz Ata					     "samsung,exynos850-uart";
13181a6ee48dSFaraz Ata				reg = <0x10d80000 0xc0>;
13191a6ee48dSFaraz Ata				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
13201a6ee48dSFaraz Ata				pinctrl-names = "default";
13211a6ee48dSFaraz Ata				pinctrl-0 = <&uart17_bus>;
13221a6ee48dSFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
13231a6ee48dSFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>;
13241a6ee48dSFaraz Ata				clock-names = "uart", "clk_uart_baud0";
13251a6ee48dSFaraz Ata				samsung,uart-fifosize = <64>;
13261a6ee48dSFaraz Ata				status = "disabled";
13271a6ee48dSFaraz Ata			};
1328*134442a0SFaraz Ata
1329*134442a0SFaraz Ata			spi_17: spi@10d80000 {
1330*134442a0SFaraz Ata				compatible = "samsung,exynosautov920-spi",
1331*134442a0SFaraz Ata					     "samsung,exynos850-spi";
1332*134442a0SFaraz Ata				reg = <0x10d80000 0x30>;
1333*134442a0SFaraz Ata				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1334*134442a0SFaraz Ata				pinctrl-names = "default";
1335*134442a0SFaraz Ata				pinctrl-0 = <&spi17_bus &spi17_cs_func>;
1336*134442a0SFaraz Ata				clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
1337*134442a0SFaraz Ata					 <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>;
1338*134442a0SFaraz Ata				clock-names = "spi", "spi_busclk0";
1339*134442a0SFaraz Ata				samsung,spi-src-clk = <0>;
1340*134442a0SFaraz Ata				dmas = <&pdma1 17>, <&pdma1 16>;
1341*134442a0SFaraz Ata				dma-names = "tx", "rx";
1342*134442a0SFaraz Ata				num-cs = <1>;
1343*134442a0SFaraz Ata				#address-cells = <1>;
1344*134442a0SFaraz Ata				#size-cells = <0>;
1345*134442a0SFaraz Ata				fifo-depth = <64>;
1346*134442a0SFaraz Ata				status = "disabled";
1347*134442a0SFaraz Ata			};
13481a6ee48dSFaraz Ata		};
13491a6ee48dSFaraz Ata
13504d060009SSunyeal Hong		cmu_top: clock-controller@11000000 {
13514d060009SSunyeal Hong			compatible = "samsung,exynosautov920-cmu-top";
13524d060009SSunyeal Hong			reg = <0x11000000 0x8000>;
13534d060009SSunyeal Hong			#clock-cells = <1>;
13544d060009SSunyeal Hong
13554d060009SSunyeal Hong			clocks = <&xtcxo>;
13564d060009SSunyeal Hong			clock-names = "oscclk";
13574d060009SSunyeal Hong		};
13584d060009SSunyeal Hong
1359c96dab19SJaewon Kim		pinctrl_alive: pinctrl@11850000 {
1360c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
1361c96dab19SJaewon Kim			reg = <0x11850000 0x10000>;
1362c96dab19SJaewon Kim
1363c96dab19SJaewon Kim			wakeup-interrupt-controller {
1364c96dab19SJaewon Kim				compatible = "samsung,exynosautov920-wakeup-eint";
1365c96dab19SJaewon Kim			};
1366c96dab19SJaewon Kim		};
1367c96dab19SJaewon Kim
1368c96dab19SJaewon Kim		pmu_system_controller: system-controller@11860000 {
1369c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pmu",
1370c96dab19SJaewon Kim				     "samsung,exynos7-pmu","syscon";
1371c96dab19SJaewon Kim			reg = <0x11860000 0x10000>;
1372c96dab19SJaewon Kim		};
1373c96dab19SJaewon Kim
1374ef1c2a54SSunyeal Hong		cmu_hsi0: clock-controller@16000000 {
1375ef1c2a54SSunyeal Hong			compatible = "samsung,exynosautov920-cmu-hsi0";
1376ef1c2a54SSunyeal Hong			reg = <0x16000000 0x8000>;
1377ef1c2a54SSunyeal Hong			#clock-cells = <1>;
1378ef1c2a54SSunyeal Hong
1379ef1c2a54SSunyeal Hong			clocks = <&xtcxo>,
1380ef1c2a54SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_HSI0_NOC>;
1381ef1c2a54SSunyeal Hong			clock-names = "oscclk",
1382ef1c2a54SSunyeal Hong				      "noc";
1383ef1c2a54SSunyeal Hong		};
1384ef1c2a54SSunyeal Hong
1385c96dab19SJaewon Kim		pinctrl_hsi0: pinctrl@16040000 {
1386c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
1387c96dab19SJaewon Kim			reg = <0x16040000 0x10000>;
1388c96dab19SJaewon Kim			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
1389c96dab19SJaewon Kim		};
1390c96dab19SJaewon Kim
1391ef1c2a54SSunyeal Hong		cmu_hsi1: clock-controller@16400000 {
1392ef1c2a54SSunyeal Hong			compatible = "samsung,exynosautov920-cmu-hsi1";
1393ef1c2a54SSunyeal Hong			reg = <0x16400000 0x8000>;
1394ef1c2a54SSunyeal Hong			#clock-cells = <1>;
1395ef1c2a54SSunyeal Hong
1396ef1c2a54SSunyeal Hong			clocks = <&xtcxo>,
1397ef1c2a54SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_HSI1_NOC>,
1398ef1c2a54SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>,
1399ef1c2a54SSunyeal Hong				 <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>;
1400ef1c2a54SSunyeal Hong			clock-names = "oscclk",
1401ef1c2a54SSunyeal Hong				      "noc",
1402ef1c2a54SSunyeal Hong				      "usbdrd",
1403ef1c2a54SSunyeal Hong				      "mmc_card";
1404ef1c2a54SSunyeal Hong		};
1405ef1c2a54SSunyeal Hong
1406c96dab19SJaewon Kim		pinctrl_hsi1: pinctrl@16450000 {
1407c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
1408c96dab19SJaewon Kim			reg = <0x16450000 0x10000>;
1409c96dab19SJaewon Kim			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
1410c96dab19SJaewon Kim		};
1411c96dab19SJaewon Kim
1412e2016763SRaghav Sharma		cmu_hsi2: clock-controller@16b00000 {
1413e2016763SRaghav Sharma			compatible = "samsung,exynosautov920-cmu-hsi2";
1414e2016763SRaghav Sharma			reg = <0x16b00000 0x8000>;
1415e2016763SRaghav Sharma			#clock-cells = <1>;
1416e2016763SRaghav Sharma
1417e2016763SRaghav Sharma			clocks = <&xtcxo>,
1418e2016763SRaghav Sharma				 <&cmu_top DOUT_CLKCMU_HSI2_NOC>,
1419e2016763SRaghav Sharma				 <&cmu_top DOUT_CLKCMU_HSI2_NOC_UFS>,
1420e2016763SRaghav Sharma				 <&cmu_top DOUT_CLKCMU_HSI2_UFS_EMBD>,
1421e2016763SRaghav Sharma				 <&cmu_top DOUT_CLKCMU_HSI2_ETHERNET>;
1422e2016763SRaghav Sharma			clock-names = "oscclk",
1423e2016763SRaghav Sharma				      "noc",
1424e2016763SRaghav Sharma				      "ufs",
1425e2016763SRaghav Sharma				      "embd",
1426e2016763SRaghav Sharma				      "ethernet";
1427e2016763SRaghav Sharma		};
1428e2016763SRaghav Sharma
1429c96dab19SJaewon Kim		pinctrl_hsi2: pinctrl@16c10000 {
1430c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
1431c96dab19SJaewon Kim			reg = <0x16c10000 0x10000>;
1432c96dab19SJaewon Kim			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1433c96dab19SJaewon Kim		};
1434c96dab19SJaewon Kim
1435c96dab19SJaewon Kim		pinctrl_hsi2ufs: pinctrl@16d20000 {
1436c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
1437c96dab19SJaewon Kim			reg = <0x16d20000 0x10000>;
1438c96dab19SJaewon Kim			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439c96dab19SJaewon Kim		};
1440c96dab19SJaewon Kim
14415893f538SSowon Na		ufs_0_phy: phy@16e04000 {
14425893f538SSowon Na			compatible = "samsung,exynosautov920-ufs-phy";
14435893f538SSowon Na			reg = <0x16e04000 0x4000>;
14445893f538SSowon Na			reg-names = "phy-pma";
14455893f538SSowon Na			clocks = <&xtcxo>;
14465893f538SSowon Na			clock-names = "ref_clk";
14475893f538SSowon Na			samsung,pmu-syscon = <&pmu_system_controller>;
14485893f538SSowon Na			#phy-cells = <0>;
14495893f538SSowon Na			status = "disabled";
14505893f538SSowon Na		};
14515893f538SSowon Na
1452c96dab19SJaewon Kim		pinctrl_aud: pinctrl@1a460000 {
1453c96dab19SJaewon Kim			compatible = "samsung,exynosautov920-pinctrl";
1454c96dab19SJaewon Kim			reg = <0x1a460000 0x10000>;
1455c96dab19SJaewon Kim		};
14562a4067c8SShin Son
14572a4067c8SShin Son		cmu_cpucl0: clock-controller@1ec00000 {
14582a4067c8SShin Son			compatible = "samsung,exynosautov920-cmu-cpucl0";
14592a4067c8SShin Son			reg = <0x1ec00000 0x8000>;
14602a4067c8SShin Son			#clock-cells = <1>;
14612a4067c8SShin Son
14622a4067c8SShin Son			clocks = <&xtcxo>,
14632a4067c8SShin Son				 <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>,
14642a4067c8SShin Son				 <&cmu_top DOUT_CLKCMU_CPUCL0_CLUSTER>,
14652a4067c8SShin Son				 <&cmu_top DOUT_CLKCMU_CPUCL0_DBG>;
14662a4067c8SShin Son			clock-names = "oscclk",
14672a4067c8SShin Son				      "switch",
14682a4067c8SShin Son				      "cluster",
14692a4067c8SShin Son				      "dbg";
14702a4067c8SShin Son		};
1471aa833db4SShin Son
1472aa833db4SShin Son		cmu_cpucl1: clock-controller@1ed00000 {
1473aa833db4SShin Son			compatible = "samsung,exynosautov920-cmu-cpucl1";
1474aa833db4SShin Son			reg = <0x1ed00000 0x8000>;
1475aa833db4SShin Son			#clock-cells = <1>;
1476aa833db4SShin Son
1477aa833db4SShin Son			clocks = <&xtcxo>,
1478aa833db4SShin Son				 <&cmu_top DOUT_CLKCMU_CPUCL1_SWITCH>,
1479aa833db4SShin Son				 <&cmu_top DOUT_CLKCMU_CPUCL1_CLUSTER>;
1480aa833db4SShin Son			clock-names = "oscclk",
1481aa833db4SShin Son				      "switch",
1482aa833db4SShin Son				      "cluster";
1483aa833db4SShin Son		};
1484aa833db4SShin Son
1485aa833db4SShin Son		cmu_cpucl2: clock-controller@1ee00000 {
1486aa833db4SShin Son			compatible = "samsung,exynosautov920-cmu-cpucl2";
1487aa833db4SShin Son			reg = <0x1ee00000 0x8000>;
1488aa833db4SShin Son			#clock-cells = <1>;
1489aa833db4SShin Son
1490aa833db4SShin Son			clocks = <&xtcxo>,
1491aa833db4SShin Son				 <&cmu_top DOUT_CLKCMU_CPUCL2_SWITCH>,
1492aa833db4SShin Son				 <&cmu_top DOUT_CLKCMU_CPUCL2_CLUSTER>;
1493aa833db4SShin Son			clock-names = "oscclk",
1494aa833db4SShin Son				      "switch",
1495aa833db4SShin Son				      "cluster";
1496aa833db4SShin Son		};
1497c96dab19SJaewon Kim	};
1498c96dab19SJaewon Kim
1499c96dab19SJaewon Kim	timer {
1500c96dab19SJaewon Kim		compatible = "arm,armv8-timer";
1501c96dab19SJaewon Kim		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1502c96dab19SJaewon Kim			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1503c96dab19SJaewon Kim			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1504c96dab19SJaewon Kim			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1505c96dab19SJaewon Kim			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1506c96dab19SJaewon Kim	};
1507c96dab19SJaewon Kim};
1508c96dab19SJaewon Kim
1509c96dab19SJaewon Kim#include "exynosautov920-pinctrl.dtsi"
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